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git-svn-id: http://moon:8086/svn/vhdl/trunk@1244 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-05-27 16:17:43 +00:00
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lib/uart/src/core/uart_tx.vhd
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008/10/20 19:26:01 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity uart_tx is
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
baud16_en : in STD_LOGIC;
din_vld : in STD_LOGIC;
din : in unsigned(7 downto 0);
din_rdy : out STD_LOGIC;
txd : out STD_LOGIC
);
end uart_tx;
architecture Behavioral of uart_tx is
signal din_reg : unsigned(7 downto 0);
signal tx_reg : unsigned(7 downto 0);
signal din_request : std_logic;
signal din_ack : std_logic;
type line_state_t is (idle, start, data, stop);
signal s, sn : line_state_t;
begin
din_rdy <= not din_request;
din_register:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
din_request <= '0'
elsif din_request = '1' then
if din_ack = '1' then
din_request <= '0'
end if;
elsif din_vld = '1' then
din_request <= '1';
din_reg <= din;
end if;
end if;
end process;
line_state_now:
process(s, din_request)
begin
txd <= '1';
sn <= s;
case s is
when idle =>
when start =>
when data =>
when stop =>
when others =>
sn <= idle;
end case;
end process;
line_state_next:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= idle;
else
s <= sn;
end if;
end if;
end process;
end Behavioral;