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- simplified PHY control signals

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1261 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 09:07:36 +00:00
parent 4646c2ef34
commit ec35a40898
1 changed files with 55 additions and 58 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
+55 -58
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@@ -61,7 +61,6 @@ end sdram_phy;
architecture tech of sdram_phy is
signal drive : std_logic;
signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal part_ctrl_reg : part_ctrl_t;
signal we_reg : std_logic;
@@ -76,8 +75,11 @@ architecture tech of sdram_phy is
signal reset_counter : unsigned(7 downto 0) := (others => '1');
signal reset : STD_LOGIC := '1';
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal u_tag_pipe : u_tag_array_t;
signal we_cl_pipe : unsigned(TCAS-1 downto 0);
signal re_cl_pipe : unsigned(TCAS+2 downto 0); -- +2 = number of pipe registers used here
type u_tag_array_t is array (natural range 0 to TCAS+3) of user_tag_t;
signal u_tag_pipe : u_tag_array_t;
attribute KEEP : string;
attribute KEEP of clk0 : signal is "TRUE";
@@ -89,6 +91,11 @@ begin
clk0_out <= clk0_temp;
clk0 <= clk0_temp after 10 ps; -- fix delta delay
rst0_out <= rst0;
-- clk0_rd <= clk_fb; -- no feedback pin on DE0-Nano, use shifted clk1_0_out from clock gen
phy_out.wr_data_re <= we_cl_pipe(we_cl_pipe'left);
phy_out.rd_data_we <= re_cl_pipe(re_cl_pipe'left);
phy_out.tag_rd <= u_tag_pipe(u_tag_pipe'high);
phy_out.tag_wr <= u_tag_pipe(1);
------------------------------------------------------------------------------------------------------------------------------------------------
@@ -126,39 +133,49 @@ rst0_gen:
end if;
end process;
------------------------------------------------------------------------------------------------------------------------------------------------
utag_pipe:
process(clk0)
begin
if rising_edge(clk0) then
for i in u_tag_pipe'length-1 downto 1 loop
u_tag_pipe(i) <= u_tag_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
u_tag_pipe(0) <= phy_ctrl.u_tag;
end if;
------------------------------------------------------------------------------------------------------------------------------------------------
utag_pipe:
process(clk0)
begin
if rising_edge(clk0) then
for i in u_tag_pipe'length-1 downto 1 loop
u_tag_pipe(i) <= u_tag_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
u_tag_pipe(0) <= phy_ctrl.u_tag;
end if;
end if;
end process;
we_pipe:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
we_cl_pipe <= (others => '0');
else
for i in we_cl_pipe'length-1 downto 1 loop
we_cl_pipe(i) <= we_cl_pipe(i-1);
end loop;
we_cl_pipe(0) <= phy_ctrl.we;
end if;
end if;
end process;
re_pipe:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
re_cl_pipe <= (others => '0');
else
for i in re_cl_pipe'length-1 downto 1 loop
re_cl_pipe(i) <= re_cl_pipe(i-1);
end loop;
re_cl_pipe(0) <= phy_ctrl.re;
end if;
end if;
end process;
WE_REGISTER:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
we_reg <= '0';
else
we_reg <= phy_ctrl.we;
end if;
end if;
end process;
DATA_DRIVE_GEN:
process(clk0)
begin
if falling_edge(clk0) then
drive <= phy_ctrl.drive_en;
end if;
end process;
end process;
------------------------------------------------------------------------------------------------------------------------------------------------
-- SDRAM Clock
@@ -169,7 +186,7 @@ part_clk <= clk0 after TPD_BOARD_SIM;
process (clk0) is
begin
if falling_edge(clk0) then
part_data <= (others => 'Z') after TPD_BOARD_SIM;
part_data <= (others => 'Z') after TPD_BOARD_SIM;
if (phy_ctrl.we = '1') then
part_data <= phy_in.wr_data after TPD_BOARD_SIM;
end if;
@@ -223,31 +240,11 @@ data_sample_stage:
data_reg_r <= part_data;
end if;
end process;
register_data_out:
process (clk0)
process (clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
p := (others => '0');
phy_out.rd_data_we <= '0';
phy_out.wr_data_re <= '0';
else
phy_out.rd_data <= data_reg_r;
if p(3) = '1' then
phy_out.tag_rd <= u_tag_pipe(4);
end if;
if phy_ctrl.we = '1' then
phy_out.tag_wr <= u_tag_pipe(0);
end if;
phy_out.wr_data_re <= phy_ctrl.drive_en;
phy_out.rd_data_we <= p(2);
if phy_ctrl.re = '1' then
p := p(p'left-1 downto 0) & '1';
else
p := p(p'left-1 downto 0) & '0';
end if;
if rising_edge(clk0) then
phy_out.rd_data <= data_reg_r;
end if;
end process;