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- simplified PHY control signals

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- revert apparent BURST fix

git-svn-id: http://moon:8086/svn/vhdl/trunk@1260 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 08:31:08 +00:00
parent b2c5bcb279
commit 4646c2ef34
4 changed files with 72 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo
+3 -3
View File
@@ -36,6 +36,8 @@ add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_data
add wave -noupdate -divider PHY
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/we_cl_pipe
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/re_cl_pipe
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/f_sdrclk
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/tpd_board_sim
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/rst
@@ -71,15 +73,13 @@ add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/dqs_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/wr_data
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/drive270
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/part_ctrl_reg
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/we_reg
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/read_en
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/clk0_temp
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/rst0
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/locked
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/error
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/uut/inst_sdram_phy/u_tag_pipe
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {199958908 ps} 0}
WaveRestoreCursors {{Cursor 1} {197881118 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+50 -49
View File
@@ -64,19 +64,17 @@ entity sdram_phy is
end sdram_phy;
architecture tech of sdram_phy is
signal dqs_drive : std_logic;
signal drive : std_logic;
signal dqs : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_zen : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_rst : std_logic;
signal wr_data : unsigned(PART_DATA_WIDTH-1 downto 0);
signal wr_data : unsigned(PART_DATA_WIDTH-1 downto 0);
signal data_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal drive270 : unsigned(PART_DATA_WIDTH-1 downto 0);
signal part_ctrl_reg : part_ctrl_t;
signal we_reg : std_logic;
signal read_en : std_logic;
signal clk0 : std_logic;
signal clk0_temp : std_logic;
@@ -88,8 +86,11 @@ architecture tech of sdram_phy is
signal locked : std_logic;
signal error : std_logic;
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal we_cl_pipe : unsigned(TCAS-1 downto 0);
signal re_cl_pipe : unsigned(TCAS+2 downto 0); -- +2 = number of pipe registers used here
type u_tag_array_t is array (natural range 0 to TCAS+3) of user_tag_t;
signal u_tag_pipe : u_tag_array_t;
attribute KEEP : string;
@@ -100,6 +101,10 @@ begin
clk0_out <= clk0_temp;
clk0 <= clk0_temp after 10 ps; -- fix delta delay
rst0_out <= rst0;
phy_out.wr_data_re <= we_cl_pipe(we_cl_pipe'left);
phy_out.rd_data_we <= re_cl_pipe(re_cl_pipe'left);
phy_out.tag_rd <= u_tag_pipe(u_tag_pipe'high);
phy_out.tag_wr <= u_tag_pipe(1);
------------------------------------------------------------------------------------------------------------------------------------------------
@@ -139,30 +144,48 @@ utag_pipe:
if rising_edge(clk0) then
for i in u_tag_pipe'length-1 downto 1 loop
u_tag_pipe(i) <= u_tag_pipe(i-1);
if phy_ctrl.utag_we = '1' then
u_tag_pipe(0) <= phy_ctrl.u_tag;
end if;
end loop;
if phy_ctrl.utag_we = '1' then
u_tag_pipe(0) <= phy_ctrl.u_tag;
end if;
end if;
end process;
WE_REGISTER:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
we_reg <= '0';
else
we_reg <= phy_ctrl.we;
end if;
end if;
end process;
we_pipe:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
we_cl_pipe <= (others => '0');
else
for i in we_cl_pipe'length-1 downto 1 loop
we_cl_pipe(i) <= we_cl_pipe(i-1);
end loop;
we_cl_pipe(0) <= phy_ctrl.we;
end if;
end if;
end process;
re_pipe:
process(clk0)
begin
if rising_edge(clk0) then
if rst0 = '1' then
re_cl_pipe <= (others => '0');
else
for i in re_cl_pipe'length-1 downto 1 loop
re_cl_pipe(i) <= re_cl_pipe(i-1);
end loop;
re_cl_pipe(0) <= phy_ctrl.re;
end if;
end if;
end process;
DATA_DRIVE_GEN:
process(clk0)
begin
dqs_rst <= not we_reg;
drive <= we_reg;
if falling_edge(clk0) then
dqs_rst <= not we_cl_pipe(we_cl_pipe'left);
drive <= we_cl_pipe(we_cl_pipe'left);
end if;
end process;
@@ -171,7 +194,7 @@ DQS_DRIVE_GEN:
process(clk0)
variable p : unsigned(1 downto 0);
begin
if phy_ctrl.drive_en = '1' then
if rising_edge(clk0) then
if phy_ctrl.we = '1' then
p := (others => '1');
else
@@ -363,7 +386,7 @@ gen_ddr_data_in:
(
Q1 => data_r(n), -- 1-bit output for positive edge of clock
Q2 => data_r(n + PART_DATA_WIDTH), -- 1-bit output for negative edge of clock
CE => read_en, -- 1-bit clock enable input
C => clk270_rd, -- 1-bit clock input
CE => re_cl_pipe(TCAS), -- 1-bit clock enable input
D => part_data(n), -- 1-bit DDR data input
R => '0', -- 1-bit reset
@@ -379,33 +402,11 @@ data_sample_stage:
data_reg_r <= data_r;
end if;
end process;
misc_flags_and_data_out:
data_out_register:
variable p : unsigned(3 downto 0);
process (clk0)
begin
if rst0 = '1' then
p := (others => '0');
read_en <= '0';
phy_out.rd_data_we <= '0';
phy_out.wr_data_re <= '0';
else
phy_out.rd_data <= data_reg_r;
if p(3) = '1' then
phy_out.tag_rd <= u_tag_pipe(4);
end if;
if phy_ctrl.we = '1' then
phy_out.tag_wr <= u_tag_pipe(0);
end if;
phy_out.wr_data_re <= phy_ctrl.we;
phy_out.rd_data_we <= p(3);
read_en <= p(1);
if phy_ctrl.re = '1' then
p := p(p'left-1 downto 0) & '1';
else
p := p(p'left-1 downto 0) & '0';
end if;
end if;
if rising_edge(clk0) then
phy_out.rd_data <= data_reg_r;
end if;
end process;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+19 -26
View File
@@ -57,7 +57,6 @@ architecture behaviour of sdram_cmd is
signal cycle_finished : std_logic;
signal cycle_cnt : cycle_cnt_t;
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
signal burst_cnt : burst_cnt_t;
@@ -90,10 +89,8 @@ fsm_sdr_state:
phy_ctrl.part.cke <= '1';
phy_ctrl.u_tag <= tag;
cc_load_en <= '0';
burst_load_en <= '0';
cmd_ack <= '0';
phy_ctrl.re <= '0';
phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0';
phy_ctrl.utag_we <= '0';
phy_ctrl.part.addr <= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right);
@@ -121,7 +118,6 @@ fsm_sdr_state:
if cmd_we = '1' then
cmd_ack <= '1';
cc_load_en <= '1';
burst_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
case cmd is
when SD_PRE =>
@@ -138,7 +134,7 @@ fsm_sdr_state:
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when SD_WRITE =>
phy_ctrl.utag_we <= '1';
phy_ctrl.drive_en <= '1';
phy_ctrl.we <= '1';
st_sdr_next <= WRITE;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when others => null;
@@ -146,37 +142,34 @@ fsm_sdr_state:
end if;
when WRITE =>
phy_ctrl.drive_en <= '1';
phy_ctrl.we <= '1';
phy_ctrl.part.cmd <= COMMAND(SD_NOP);
if cmd_we = '1' and cmd = SD_WRITE then
cc_load_en <= '1';
cmd_ack <= '1';
phy_ctrl.utag_we <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
burst_load_en <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_WRITE then
cmd_ack <= '1';
cc_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
phy_ctrl.we <= '0';
st_sdr_next <= IDLE_WAIT;
end if;
else
phy_ctrl.drive_en <= '0';
st_sdr_next <= IDLE_WAIT;
end if;
when READ =>
phy_ctrl.re <= '1';
phy_ctrl.part.cmd <= COMMAND(SD_NOP);
if cmd_we = '1' and cmd = SD_READ then
cc_load_en <= '1';
cmd_ack <= '1';
phy_ctrl.utag_we <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
burst_load_en <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_READ then
cmd_ack <= '1';
cc_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
st_sdr_next <= IDLE_WAIT;
end if;
else
st_sdr_next <= IDLE_WAIT;
end if;
when PRECHARGE =>
@@ -248,7 +241,7 @@ burst_counter:
process (clk)
begin
if rising_edge(clk) then
if burst_load_en = '1' then
if cc_load_en = '1' then
burst_finished <= '0';
burst_cnt <= burst_cnt_t'high;
if 2**(LMR_BL_CURR) = DATA_RATE_FACTOR then
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
-1
View File
@@ -64,7 +64,6 @@ package sdram_types is
type phy_ctrl_t is
record
drive_en : std_logic;
re : std_logic;
we : std_logic;
utag_we : std_logic;