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- adde SIPO and PISO

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1263 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 12:27:20 +00:00
parent 5e4798bbab
commit 99b30ba0cc
4 changed files with 150 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.fdo
+3 -1
View File
@@ -19,6 +19,8 @@ vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/sdr_clk_cycloneive.vhd"
vcom -explicit -93 "../src/sdr_phy_de0nano.vhd"
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../emac/src/piso.vhd"
vcom -explicit -93 "../../../emac/src/sipo.vhd"
vcom -explicit -93 "../src/sdram_ctrl_frontend_wb16.vhd"
vcom -explicit -93 "../src/ctrl_sdr_wb32.vhd"
vcom -explicit -93 "../src/mti_pkg.vhd"
@@ -30,4 +32,4 @@ do {tb_ctrl_sdr_wb32_de0nano.wdo}
view wave
view structure
view signals
run 120us
run 220us
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo
+61 -4
View File
@@ -32,6 +32,65 @@ add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/part_dqm
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/sd_cmd
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_data
add wave -noupdate -divider Frontend
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/f_sysclk
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/f_sdrclk
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/fifo_depth
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/rst_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/clk_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/sdram_rst0
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/sdram_clk0
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cyc_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/stb_i
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/sel_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/we_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/ack_o
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/mrdy_i
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/srdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/phy_ctrl
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/phy_in
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/phy_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/u_addr
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/u_tag_in
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/u_cmd
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/u_cmd_we
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/u_busy
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_dout
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_re
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_we
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_full
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cat_fifo_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_dout
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_re
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_we
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_full
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_dout
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_re
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_we
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_full
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_empty
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_data_avail
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/read_fifo_data_in
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_dm_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_data_out
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_dm_in
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/write_fifo_data_in
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/addr_fifo_out
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/tag_fifo_out
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cmd_fifo_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/addr_fifo_in
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/tag_fifo_in
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/cmd_fifo_in
add wave -noupdate -divider PHY
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/f_sdrclk
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst
@@ -39,7 +98,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_fb
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_out
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0_out
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_out
add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_ctrl
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_clk
@@ -53,7 +112,6 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_we_n
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cas_n
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ras_n
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cke
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/drive
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/data_reg_r
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ctrl_reg
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/we_reg
@@ -81,7 +139,6 @@ add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb1
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_load_en
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_finished
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_cnt
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_load_en
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_finished
add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_cnt
add wave -noupdate -divider {Main FSM}
@@ -130,7 +187,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_activate
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_clr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {82985000 ps} 0}
WaveRestoreCursors {{Cursor 1} {119326322 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
+85 -20
View File
@@ -80,20 +80,23 @@ architecture struct of sdram_ctrl_frontend_wb16 is
signal cat_fifo_full : std_logic;
signal cat_fifo_empty : std_logic;
signal write_fifo_din : unsigned(BUS_DATA_WIDTH + BUS_DM_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(BUS_DATA_WIDTH + BUS_DM_WIDTH-1 downto 0);
signal write_fifo_din : unsigned(32 + 4-1 downto 0);
signal write_fifo_dout : unsigned(32 + 4-1 downto 0);
signal write_fifo_re : std_logic;
signal write_fifo_we : std_logic;
signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic;
signal read_fifo_din : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal read_fifo_dout : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal read_fifo_din : unsigned(32-1 downto 0);
signal read_fifo_dout : unsigned(32-1 downto 0);
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_full : std_logic;
signal read_fifo_empty : std_logic;
signal write_fifo_data_avail : std_logic;
signal read_fifo_rdy : std_logic;
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
@@ -101,10 +104,10 @@ architecture struct of sdram_ctrl_frontend_wb16 is
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto BUS_DM_WIDTH);
alias write_fifo_dm_in is write_fifo_din(BUS_DM_WIDTH-1 downto 0);
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto BUS_DM_WIDTH);
alias write_fifo_dm_out is write_fifo_dout(BUS_DM_WIDTH-1 downto 0);
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
alias write_fifo_dm_in is write_fifo_din(4-1 downto 0);
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
alias write_fifo_dm_out is write_fifo_dout(4-1 downto 0);
alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
@@ -154,6 +157,48 @@ begin
data_r => write_fifo_dout
);
write_fifo_data_avail <= not write_fifo_empty;
inst_write_piso_data: entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => PART_DATA_WIDTH
)
PORT MAP
(
rst => SDRAM_RST0,
clk => SDRAM_CLK0,
din_vld => write_fifo_data_avail,
din_rdy => write_fifo_re,
din_be => "11",
din => write_fifo_data_out,
dout_vld => open,
dout_en => phy_out.wr_data_re,
dout => phy_in.wr_data
);
inst_write_piso_dm: entity work.piso
GENERIC MAP
(
data_width_in => 4,
data_width_out => PART_DM_WIDTH
)
PORT MAP
(
rst => SDRAM_RST0,
clk => SDRAM_CLK0,
din_vld => write_fifo_data_avail,
din_rdy => write_fifo_re,
din_be => "11",
din => write_fifo_dm_out,
dout_vld => open,
dout_en => phy_out.wr_data_re,
dout => phy_in.wr_dm
);
-- Instantiate synchronous FIFO
inst_read_fifo: entity work.fifo_async
GENERIC MAP
@@ -176,6 +221,27 @@ begin
data_r => read_fifo_dout
);
read_fifo_rdy <= not read_fifo_full;
inst_read_sipo: entity work.sipo
GENERIC MAP
(
data_width_in => PART_DATA_WIDTH,
data_width_out => 32
)
PORT MAP
(
rst => SDRAM_RST0,
clk => SDRAM_CLK0,
din_en => '1',
din_vld => phy_out.rd_data_we,
din => phy_out.rd_data,
dout_vld => read_fifo_we,
dout_en => read_fifo_rdy,
dout => read_fifo_data_in
);
-- DDR SDRAM Controller Core
inst_sdram_ctrl_top : entity work.sdram_ctrl_top
Generic map
@@ -208,27 +274,26 @@ begin
------------------------------------------------------------------------------------------
SRDY_O <= rdy;
ACK_O <= not (read_fifo_empty);
DAT_O <= read_fifo_data_out & read_fifo_data_out;
rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
DAT_O <= read_fifo_data_out;
rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I and not SDRAM_RST0;
write_fifo_we <= STB_I and WE_I and rdy;
write_fifo_data_in <= DAT_I(15 downto 0);
write_fifo_dm_in <= not SEL_I(1 downto 0);
write_fifo_data_in <= DAT_I;
write_fifo_dm_in <= not SEL_I;
cat_fifo_we <= STB_I and rdy;
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
addr_fifo_in <= "000" & ADDR_I(22 downto 2);
addr_fifo_in <= "00" & ADDR_I(22 downto 1);
tag_fifo_in <= "000" & ADDR_I(2);
cat_fifo_re <= u_cmd_we and (not u_busy);
u_cmd_we <= (not cat_fifo_empty);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
phy_in.wr_dm <= write_fifo_dm_out;
u_tag_in <= tag_fifo_out;
phy_in.wr_data <= write_fifo_data_out;
write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we and (not u_busy);
-- phy_in.wr_dm <= write_fifo_dm_out;
-- phy_in.wr_data <= write_fifo_data_out;
-- write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= phy_out.rd_data_we;
read_fifo_data_in <= phy_out.rd_data;
-- read_fifo_we <= phy_out.rd_data_we;
-- read_fifo_data_in <= phy_out.rd_data & phy_out.rd_data;
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd
+1 -1
View File
@@ -228,7 +228,7 @@ STIMULUS: process
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"0000_1234";
DAT_O <= X"1234_1000";
ADDR_O <= X"0000_0000";
for i in 0 to 8192 loop