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- update fixed_pkg

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1323 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-10-24 14:56:24 +00:00
parent 6226f79562
commit deb2fdbb90
11 changed files with 2783 additions and 3058 deletions
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Common/sim/compile_fixed.do
-13
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@@ -1,13 +0,0 @@
#
# Compile script for Modeltech
#
vlib ieee_proposed
vmap ieee_proposedx ieee_proposed
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_additions_c.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/env_c.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_textio_additions_c.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/std_logic_1164_additions.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_additions.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_unsigned_c.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/math_utility_pkg_c.vhdl"
vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/fixed_pkg_c.vhdl"
Common/sim/compile_ieee_proposed.do
+1 -1
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@@ -17,6 +17,6 @@ vcom -work ieee_proposed ../../ieee_proposed/modelsim/env_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/std_logic_1164_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/math_utility_pkg_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_float_types_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_pkg_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/float_pkg_c.vhdl
Common/sim/ieee_proposed/modelsim/README
+3 -3
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@@ -72,7 +72,7 @@ C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
1) Short had aliases:
a) to_bv - calls "to_BitVector"
b) to_slv - calls "to_StdLogicVector"
c) to_suv - calls "to_stdULogicVector"
c) to_sulv - calls "to_stdULogicVector"
2) Long hand aliases:
a) to_bit_vector - calls "to_BitVector"
b) to_std_logic_vector - calls "to_StdLogicVector"
@@ -157,7 +157,7 @@ F) For fixed point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
See fixed point package documentation
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
@@ -166,7 +166,7 @@ G) For floating point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
See floating point package documentation
Common/sim/ieee_proposed/modelsim/compile.mti
+2 -2
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@@ -2,13 +2,13 @@
# Compile script for Modeltech
#
vlib ieee_proposed.lib
vmap ieee_proposedx ieee_proposed.lib
vmap ieee_proposed ieee_proposed.lib
vcom -work ieee_proposed standard_additions_c.vhdl
vcom -work ieee_proposed standard_textio_additions_c.vhdl
vcom -work ieee_proposed env_c.vhdl
vcom -work ieee_proposed std_logic_1164_additions.vhdl
vcom -work ieee_proposed numeric_std_additions.vhdl
vcom -work ieee_proposed numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed math_utility_pkg_c.vhdl
vcom -work ieee_proposed fixed_float_types_c.vhdl
vcom -work ieee_proposed fixed_pkg_c.vhdl
vcom -work ieee_proposed float_pkg_c.vhdl
Common/sim/ieee_proposed/modelsim/fixed_pkg_c.vhdl
+750 -992
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Common/sim/ieee_proposed/modelsim/float_pkg_c.vhdl
+1016 -747
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Common/sim/ieee_proposed/modelsim/math_utility_pkg_c.vhdl
-38
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@@ -1,38 +0,0 @@
-- --------------------------------------------------------------------
-- "math_utility_pkg" package contains types used by the both the fixed
-- and floating point packages.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.math_utility.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.1 $
-- Date : $Date: 2007-04-04 14:00:18-04 $
-- --------------------------------------------------------------------
package math_utility_pkg is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package math_utility_pkg;
Common/sim/ieee_proposed/modelsim/numeric_std_additions.vhdl
+554 -608
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Common/sim/ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
+47 -38
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@@ -1,29 +1,3 @@
-- --------------------------------------------------------------------
--
--
-- Copyright©2006 by the Institute of Electrical and Electronics Engineers, Inc.
-- Three Park Avenue
-- New York, NY 10016-5997, USA
-- All rights reserved.
--
-- This document is an unapproved draft of a proposed IEEE Standard. As such,
-- this document is subject to change. USE AT YOUR OWN RISK! Because this
-- is an unapproved draft, this document must not be utilized for any
-- conformance/compliance purposes. Permission is hereby granted for IEEE
-- Standards Committee participants to reproduce this document for purposes
-- of IEEE standardization activities only. Prior to submitting this document
-- to another standards development organization for standardization
-- activities, permission must first be obtained from the Manager, Standards
-- Licensing and Contracts, IEEE Standards Activities Department. Other
-- entities seeking permission to reproduce this document, in whole or in
-- part, must obtain permission from the Manager, Standards Licensing and
-- Contracts, IEEE Standard Activities Department.
--
-- IEEE Standards Activities Department
-- Standards Licensing and Contracts
-- 445 Hoes Lane, P.O. Box 1331
-- Piscataway, NJ 08855-1331, USA
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
@@ -40,16 +14,12 @@
--
-- Other changes will be noted here.
--
-- Version: $Revision: 1.1 $
-- Date: $Date: 2006-06-13 15:53:20-04 $
--
-- Created for VHDL-200X-ft, David Bishop (dbishop@vhdl.org)
-- -----------------------------------------------------------------------------
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2006 IEEE. All rights reserved.";
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
@@ -560,6 +530,9 @@ package NUMERIC_STD_UNSIGNED is
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
@@ -581,19 +554,27 @@ package NUMERIC_STD_UNSIGNED is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SUV is
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
@@ -1117,6 +1098,9 @@ package NUMERIC_STD_UNSIGNED is
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
@@ -1128,6 +1112,7 @@ package NUMERIC_STD_UNSIGNED is
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
@@ -1144,8 +1129,8 @@ end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.1 $
-- Date: $Date: 2006-06-13 15:53:20-04 $
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
-------------------------------------------------------------------------------
@@ -1644,6 +1629,13 @@ package body NUMERIC_STD_UNSIGNED is
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
@@ -1659,6 +1651,11 @@ package body NUMERIC_STD_UNSIGNED is
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
@@ -1666,6 +1663,11 @@ package body NUMERIC_STD_UNSIGNED is
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
@@ -2171,6 +2173,13 @@ package body NUMERIC_STD_UNSIGNED is
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
Common/sim/ieee_proposed/modelsim/standard_textio_additions_c.vhdl
+2 -2
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@@ -3,8 +3,8 @@
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007-03-13 14:25:58-04 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007-03-13 14:25:58-04 l435385 Exp $
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
Common/sim/ieee_proposed/modelsim/std_logic_1164_additions.vhdl
+408 -614
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