- added altera_mf
- fixed compile scripts git-svn-id: http://moon:8086/svn/vhdl/trunk@1254 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
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--
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-- Copyright (C) 1988-2002 Altera Corporation
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--
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-- Any megafunction design, and related net list (encrypted or decrypted),
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-- support information, device programming or simulation file, and any
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-- other associated documentation or information provided by Altera or a
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-- partner under Altera's Megafunction Partnership Program may be used only
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-- to program PLD devices (but not masked PLD devices) from Altera. Any
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-- other use of such megafunction design, net list, support information,
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-- device programming or simulation file, or any other related
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-- documentation or information is prohibited for any other purpose,
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-- including, but not limited to modification, reverse engineering, de-
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-- compiling, or use with any other silicon devices, unless such use is
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-- explicitly licensed under a separate agreement with Altera or a
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-- megafunction partner. Title to the intellectual property, including
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-- patents, copyrights, trademarks, trade secrets, or maskworks, embodied
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-- in any such megafunction design, net list, support information, device
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-- programming or simulation file, or any other related documentation or
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-- information provided by Altera or a megafunction partner, remains with
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-- Altera, the megafunction partner, or their respective licensors. No
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-- other licenses, including any licenses needed under any third party's
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-- intellectual property, are provided herein.
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- ALtera Stratix GX Megafunction Component Declaration File
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package stratixgx_mf_components is
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function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
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channel_width : integer) return integer;
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function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
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dwidth_factor : integer) return integer;
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component altgxb
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generic (
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operation_mode : string := "DUPLEX";
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loopback_mode : string := "NONE";
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reverse_loopback_mode : string := "NONE";
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protocol : string := "CUSTOM";
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number_of_channels: integer := 20;
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number_of_quads : integer := 1;
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channel_width : positive := 20;
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pll_inclock_period : integer := 20000;
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data_rate : integer := 0;
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data_rate_remainder : integer := 0;
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rx_data_rate : integer := 0;
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rx_data_rate_remainder : integer := 0;
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use_8b_10b_mode : string := "OFF";
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use_double_data_mode : string := "OFF";
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dwidth_factor : integer := 1;
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-- RX Mode
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disparity_mode : string := "OFF";
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cru_inclock_period : integer := 0; -- Units in ps
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run_length : integer := 128;
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run_length_enable : string := "OFF";
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use_channel_align : string := "OFF";
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use_auto_bit_slip : string := "OFF";
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use_rate_match_fifo : string := "OFF";
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use_symbol_align : string := "OFF";
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align_pattern : string := "X";
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align_pattern_length : integer := 0;
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infiniband_invalid_code : integer := 0;
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clk_out_mode_reference : string := "ON";
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-- TX Mode
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use_fifo_mode : string := "ON";
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intended_device_family : string := "STRATIXGX";
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force_disparity_mode : string := "OFF";
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lpm_type : string := "altgxb";
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tx_termination : integer := 0;
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-- Quartus 2.2 New Parameters
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-- common
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use_self_test_mode : string := "OFF";
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self_test_mode : integer := 0;
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-- Receiver
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use_equalizer_ctrl_signal : string := "OFF";
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equalizer_ctrl_setting : integer := 0;
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signal_threshold_select : integer := 80;
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rx_bandwidth_type : string := "NEW_MEDIUM";
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rx_enable_dc_coupling : string := "OFF";
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use_vod_ctrl_signal : string := "OFF";
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vod_ctrl_setting : integer := 1000;
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use_preemphasis_ctrl_signal : string := "OFF";
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preemphasis_ctrl_setting : integer := 0;
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use_phase_shift : string := "ON";
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pll_bandwidth_type : string := "LOW";
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pll_use_dc_coupling : string := "OFF";
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rx_ppm_setting : integer := 1000;
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use_generic_fifo : string := "OFF";
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use_rx_cruclk : string := "OFF";
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use_rx_clkout : string := "OFF";
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use_rx_coreclk : string := "OFF";
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use_tx_coreclk : string := "OFF";
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instantiate_transmitter_pll : string := "OFF";
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consider_instantiate_transmitter_pll_param : string := "OFF";
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rx_force_signal_detect : string := "OFF";
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flip_rx_out : string := "OFF";
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flip_tx_in : string := "OFF";
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add_generic_fifo_we_synch_register : string := "OFF";
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consider_enable_tx_8b_10b_i1i2_generation : string := "OFF";
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enable_tx_8b_10b_i1i2_generation : string := "OFF";
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for_engineering_sample_device : string := "ON";
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device_family : string := ""
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);
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port (
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inclk : in std_logic_vector(number_of_quads-1 downto 0) := (others => '0');
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rx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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pll_areset : in std_logic_vector(number_of_quads-1 downto 0):= (others => '0');
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rx_cruclk : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '0');
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rx_in : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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rx_bitslip : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_enacdet : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
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rx_we: in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_re: in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
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rx_slpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_a1a2size : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_equalizerctrl : in std_logic_vector(number_of_channels * 3 -1 downto 0) := (others => '0');
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rx_locktorefclk : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
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rx_locktodata : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
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tx_in : in std_logic_vector(channel_width * number_of_channels-1 downto 0) := (others => '0');
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tx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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tx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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tx_ctrlenable : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
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tx_forcedisparity : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
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tx_srlpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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tx_vodctrl : in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
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tx_preemphasisctrl: in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
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-- XGM Input ports, common for Both Rx and Tx Mode
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txdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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rxdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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rxanalogreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
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pllenable : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '1');
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pll_locked : out std_logic_vector(number_of_quads-1 downto 0);
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coreclk_out : out std_logic_vector(number_of_quads-1 downto 0);
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rx_out : out std_logic_vector(get_rx_channel_width(use_generic_fifo,
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clk_out_mode_reference, channel_width) * number_of_channels-1 downto 0);
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rx_clkout : out std_logic_vector(number_of_channels-1 downto 0);
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rx_locked : out std_logic_vector(number_of_channels-1 downto 0);
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rx_freqlocked : out std_logic_vector(number_of_channels-1 downto 0);
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rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
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rx_syncstatus : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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rx_patterndetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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rx_ctrldetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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rx_errdetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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rx_disperr : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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rx_signaldetect : out std_logic_vector(number_of_channels-1 downto 0);
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rx_fifoalmostempty : out std_logic_vector(number_of_channels-1 downto 0);
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rx_fifoalmostfull : out std_logic_vector(number_of_channels-1 downto 0);
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rx_channelaligned : out std_logic_vector(number_of_quads-1 downto 0);
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rx_bisterr : out std_logic_vector(number_of_channels-1 downto 0);
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rx_bistdone : out std_logic_vector(number_of_channels-1 downto 0);
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rx_a1a2sizeout : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
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clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
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tx_out : out std_logic_vector(number_of_channels-1 downto 0)
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);
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end component;
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end;
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package body stratixgx_mf_components is
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function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
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channel_width : integer) return integer is
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variable rx_channel_width : integer;
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begin
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rx_channel_width := channel_width;
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if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
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if (channel_width = 16) or (channel_width = 20) then
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rx_channel_width := channel_width/2;
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end if;
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end if;
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return rx_channel_width;
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end get_rx_channel_width;
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function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
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dwidth_factor : integer) return integer is
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variable rx_dwidth_factor : integer;
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begin
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rx_dwidth_factor := dwidth_factor;
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if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
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if (dwidth_factor = 2) then
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rx_dwidth_factor := dwidth_factor/2;
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end if;
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end if;
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return rx_dwidth_factor;
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end get_rx_dwidth_factor;
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end;
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@@ -1,32 +1,36 @@
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vlib build
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vlib build/altera
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vlib build/altera
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vlib build/altera/altera
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vmap altera build/altera/altera
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if {![file exists build]} {mkdir build}
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cd build
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if {![file exists altera]} {mkdir altera}
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cd altera
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vcom -93 -work altera altera/libsrc/altera/altera_primitives_components.vhd
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vcom -93 -work altera altera/libsrc/altera/altera_primitives.vhd
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vcom -93 -work altera altera/libsrc/altera/altera_internal_syn.vhd
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vcom -93 -work altera altera/libsrc/altera/altera_europa_support_lib.vhd
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vcom -93 -work altera altera/libsrc/altera/altera_standard_functions.vhd
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vcom -93 -work altera altera/libsrc/altera/altera_syn_attributes.vhd
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if {[file exists altera]} {vdel -lib altera -all}
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vlib altera
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vlib build/altera/cycloneive
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vmap cycloneive build/altera/cycloneive
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vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives_components.vhd
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vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives.vhd
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vcom -93 -work altera ../../altera/libsrc/altera/altera_internal_syn.vhd
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vcom -93 -work altera ../../altera/libsrc/altera/altera_europa_support_lib.vhd
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vcom -93 -work altera ../../altera/libsrc/altera/altera_standard_functions.vhd
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vcom -93 -work altera ../../altera/libsrc/altera/altera_syn_attributes.vhd
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vcom -93 -work cycloneive altera/libsrc/cycloneive/cycloneive_atoms.vhd
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vcom -93 -work cycloneive altera/libsrc/cycloneive/cycloneive_components.vhd
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vlib altera_mf
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vcom -93 -work altera ../../altera/libsrc/altera_mf/altera_mf_components.vhd
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vlib build/altera/altera_lnsim
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vmap altera_lnsim build/altera/altera_lnsim
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vlib cycloneive
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vcom -93 -work altera_lnsim altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
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vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_atoms.vhd
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vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_components.vhd
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vlib build/altera/cyclonev
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vmap cyclonev build/altera/cyclonev
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vlib altera_lnsim
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vcom -93 -work cyclonev altera/libsrc/cyclonev/cyclonev_atoms.vhd
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vcom -93 -work cyclonev altera/libsrc/cyclonev/cyclonev_components.vhd
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vcom -93 -work altera_lnsim ../../altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
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vlib cyclonev
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vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_atoms.vhd
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vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_components.vhd
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cd ..
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cd ..
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@@ -1,10 +1,15 @@
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vlib build
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vlib build/xilinx
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if {![file exists build]} {mkdir build}
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cd build
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if {![file exists xilinx]} {mkdir xilinx}
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cd xilinx
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vlib build/xilinx/unisim
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vmap unisim build/xilinx/unisim
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if {[file exists unisim]} {vdel -lib unisim -all}
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vlib unisim
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vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vpkg.vhd
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vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vcomp.vhd
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vcom -93 -work unisim xilinx/libsrc/unisims/unisim_smodel.vhd
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vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vital.vhd
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vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vpkg.vhd
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vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vcomp.vhd
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vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_smodel.vhd
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vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vital.vhd
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cd ..
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cd ..
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Reference in New Issue
Block a user