commit stale changes

- updated .gitignore.templ

Common/make/ghdl.mk

@@ -11,13 +11,14 @@ LANG_STD ?= 93c
 IEEE_STD ?= standard
 RUN_TIME ?= 1000ns
 WAVE_FORMAT ?= fst
+EXTRA_OPTS ?=
 
 # Build path
 BUILD_DIR ?= build/$(TARGET)
 WORK_DIR ?= $(BUILD_DIR)/$(WORK_LIB)
 
 # Can be pre-initialized by user
-RUN_OPTS += --stop-time=$(RUN_TIME)
+RUN_OPTS += --stop-time=$(RUN_TIME) $(EXTRA_OPTS) 
 GHDL_OPTS += --work=$(WORK_LIB) --workdir=$(WORK_DIR) --std=$(LANG_STD) --ieee=$(IEEE_STD)
 
 # -------------------------------------------------
@@ -49,7 +50,7 @@ SIM_FILE-fst := $(BUILD_DIR)/$(TARGET).fst
 GTK_OPTS-fst := --fst=$(SIM_FILE-fst)
 
 SIM_FILE-ghw := $(BUILD_DIR)/$(TARGET).ghw
-GTK_OPTS-ghw := --wave=$(SIM_FILE-ghw)
+GTK_OPTS-ghw := --wave=$(SIM_FILE-ghw) --read-wave-opt=$(TARGET).wopt
 
 SIM_FILE := $(SIM_FILE-$(WAVE_FORMAT))
 GTK_OPTS := $(GTK_OPTS-$(WAVE_FORMAT))
@@ -62,8 +63,6 @@ all:  analyze
 
 $(WORK_DIR):
 	mkdir -p $@
-	touch $(TARGET).gtkw
-	cp -n $(TARGET).gtkw $(BUILD_DIR)
 
 syntax: 
 	$(GHDL) -s $(GHDL_OPTS) $(SRCS)
@@ -95,16 +94,20 @@ run_wave: analyze
 synth: analyze
 	$(GHDL) --synth $(GHDL_OPTS) $(ENTITY)
 
-wave: run_wave
-	exec gtkwave -f $(SIM_FILE) -a $(BUILD_DIR)/$(TARGET).gtkw &
-	
-result:
-	exec gtkwave -f $(SIM_FILE) -a $(BUILD_DIR)/$(TARGET).gtkw &
-
 tree: analyze
 	$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS) --no-run --disp-tree=inst
 	
+genwopt: analyze
+	rm -rf $(TARGET).wopt.templ
+	$(GHDL) -r $(GHDL_OPTS) $(ENTITY) --stop-time=0ps --write-wave-opt=$(TARGET).wopt.templ --wave=$(BUILD_DIR)/$(TARGET).ghw
+
+wave: run_wave
+	exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
 	
+result:
+	exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
+
+
 .PHONY: list
 INSTR = $(foreach number,$(SRCS),echo $(number);)
 list:

Common/make/ise.mk

@@ -13,6 +13,10 @@ NETLIST_DIR ?= ./
 MAP_EFFORT ?= high
 PAR_EFFORT ?= high
 
+BUILD_DIR := ./
+XST_DIR := $(BUILD_DIR)/xst/tmp
+DIRS := $(XST_DIR)
+
 # Netlist
 $(PRJ).ngc: $(DIRS) $(PREQ) ./project/$(PRJ).ucf
 	xst -intstyle xflow -ifn ./project/$(PRJ).xst

Common/make/package_new.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include package_other.inc
 

Common/make/tb_new.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include package1.inc
 include package2.inc

Common/sim/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

Common/sim/ieee_proposed.make

@@ -1,7 +1,7 @@
 # -------------------------------------------------
 # Compile script for GHDL
 # -------------------------------------------------
-include ../make/defs.mk
+include $(VHDL_HOME)/make/defs.mk
 
 # -------------------------------------------------
 # Global options
@@ -9,20 +9,21 @@ include ../make/defs.mk
 LANG_STD := 93c
 IEEE_STD := standard
 WORK_LIB := ieee_proposed
-TARGET := ieee_proposed
+TARGET := ghdl
 
+STD_LIB_PATH := ieee_proposed/modelsim
 # -------------------------------------------------
 # Target options
 # -------------------------------------------------
-SRCS := $(LIB_PATH)/standard_additions_c.vhdl
-SRCS += $(LIB_PATH)/standard_textio_additions_c.vhdl
-SRCS += $(LIB_PATH)/env_c.vhdl
-SRCS += $(LIB_PATH)/std_logic_1164_additions.vhdl
-SRCS += $(LIB_PATH)/numeric_std_additions.vhdl
-SRCS += $(LIB_PATH)/numeric_std_unsigned_c.vhdl
-SRCS += $(LIB_PATH)/fixed_float_types_c.vhdl
-SRCS += $(LIB_PATH)/fixed_pkg_c.vhdl
-SRCS += $(LIB_PATH)/float_pkg_c.vhdl
+SRCS := $(STD_LIB_PATH)/standard_additions_c.vhdl
+SRCS += $(STD_LIB_PATH)/standard_textio_additions_c.vhdl
+SRCS += $(STD_LIB_PATH)/env_c.vhdl
+SRCS += $(STD_LIB_PATH)/std_logic_1164_additions.vhdl
+SRCS += $(STD_LIB_PATH)/numeric_std_additions.vhdl
+SRCS += $(STD_LIB_PATH)/numeric_std_unsigned_c.vhdl
+SRCS += $(STD_LIB_PATH)/fixed_float_types_c.vhdl
+SRCS += $(STD_LIB_PATH)/fixed_pkg_c.vhdl
+SRCS += $(STD_LIB_PATH)/float_pkg_c.vhdl
 
-include ../make/ghdl.mk
+include $(VHDL_HOME)/make/ghdl.mk
 

Common/sim/unisim.make

@@ -1,7 +1,7 @@
 # -------------------------------------------------
 # Compile script for GHDL
 # -------------------------------------------------
-include ../make/defs.mk
+include $(VHDL_HOME)/make/defs.mk
 
 # -------------------------------------------------
 # Global options
@@ -9,18 +9,19 @@ include ../make/defs.mk
 LANG_STD := 93c
 IEEE_STD := standard
 WORK_LIB := unisim
-TARGET := unisim
+TARGET := ghdl
 
+STD_LIB_PATH := xilinx/libsrc/unisims
 # -------------------------------------------------
 # Target options
 # -------------------------------------------------
-SRCS := $(LIB_PATH)/unisims/unisim_VPKG.vhd
-SRCS += $(LIB_PATH)/unisims/unisim_VCOMP.vhd
-SRCS += $(LIB_PATH)/unisims/unisim_SMODEL.vhd
-SRCS += $(LIB_PATH)/unisims/unisim_VITAL.vhd
+SRCS := $(STD_LIB_PATH)/unisim_VPKG.vhd
+SRCS += $(STD_LIB_PATH)/unisim_VCOMP.vhd
+SRCS += $(STD_LIB_PATH)/unisim_SMODEL.vhd
+SRCS += $(STD_LIB_PATH)/unisim_VITAL.vhd
 
 GHDL_OPTS := -fsynopsys -fexplicit
 
-include ../make/ghdl.mk
+include $(VHDL_HOME)/make/ghdl.mk
 
 

Common/tools/jcpu/eval_scan.rb

@@ -0,0 +1,42 @@
+#!/usr/bin/env ruby
+
+str1 = %Q!lbl:		dc		"Hallo", ", ", 0, 1, " der","Jens"!
+
+i=0;
+
+def get_stri_lit (str)
+	res = [""];
+	state = "out"
+	
+	j = 0;
+	k = 0;
+	for i in (0..str.length-1)
+		c = str[i];
+		nstate = state
+		case state 
+		when "out"
+			if c == "\""[0]
+				nstate = "in"
+			end
+		when "in"	
+			if c == "\""[0]
+				nstate = "out"
+				if j > 0
+					k = k + 1;
+					res[k] = ""
+				end	
+			else
+				res[k] = res[k] + format("%c", c);
+				j = j + 1;
+			end
+		end
+		state = nstate
+	end;
+	return res
+end		
+	
+get_stri_lit(str1).each do |word|
+	puts word
+end	
+ 	
+ 

Common/tools/jcpu/insrom.rb

@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "JASM_ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end

Common/tools/jcpu/irom.vhd.tpl

@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+

Common/tools/jcpu/irom_ld.vhd.tpl

@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

Common/tools/jcpu/jasm.bak.rb

@@ -0,0 +1,494 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+
+# Copyright (C) 2007 J. Ahrensfeld
+
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+# For questions and ideas, please contact the author at jens@jayfield.org
+
+# ---------------------------------------------------------------------
+
+arg = $*
+MAX_SIZE_ROM = 1024
+PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
+ENTITY_NAME = "rom"
+ENTITY_DATA_TYPE = "inst_t"
+ENTITY_ADDR_TYPE = "inst_addr_t"
+OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg.to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+lc = 0	# Line counter
+pc = 0	# Program counter
+chip_dc = [0,0,0,0]	# chip data counter
+xmem_dc = 0	# xmem data counter
+curr_segment = "UNDEF";
+page = 0
+
+label_list=[[],[]]
+instr_list=[nil]
+file = File.open(filename, "r")
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip.upcase
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if label_list.rindex(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	case iline_member[mc]
+	when nil
+		value = format("0x%3.3X",pc)
+	when "EQU"
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
+		else 	
+			value = iline_member[mc+1]
+		end 	
+	when "ORG", "CODE"
+		pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
+		value = format("0x%3.3X",pc)
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
+			exit 1
+		end 	
+		curr_segment = "CMEM";
+		page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| 
+			len += 1
+		end	
+		if curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
+			exit 1
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	when "DB"
+		len = iline_member[mc+1].to_i
+		if curr_segment == "CMEM"
+			value = format("0x%2.2X",chip_dc[page])
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
+			chip_dc[page] += len
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	else
+		op_line = iline_member[mc+1..iline_member.nitems].to_s
+		value = format("0x%3.3X",pc)
+		opc = iline_member[mc]
+		if iline_member[mc+1] != nil
+			op1 = op_line.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
+		end	
+		if instr_list[pc] == nil
+			instr_list[pc] = [lc, pc, opc , op1 , op2]
+			pc += 1
+		else
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
+			exit 1
+		end
+	end;	
+
+	# Push labels
+	if label	
+		label_list = label_list + [label, value]
+	end
+end
+file.close
+
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..3)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+#		instruct[subst_pos] = instruct[subst_pos].delete(" ")
+
+		# checks R0 .. R16, Mnemonics
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\//)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = instruct[opc_start+i+1].delete("()").to_i(16)
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	when "NOP", "HALT", "RET", "RETI"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", ENTITY_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("ROM file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+
+	filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (MAX_SIZE_ROM-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(MAX_SIZE_ROM-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("PREINIT file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+	filename = format("rom_%s.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("TCL snippet written to \"%s\"\n",filename)
+	file.close
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{pc} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	

Common/tools/jcpu/jasm.rb

@@ -0,0 +1,811 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+FILE_SUFFIX = "jsm"
+IROM_MAX_SIZE = 1024
+IROM_ENTITY_NAME = "irom"
+IROM_DATA_TYPE = "inst_t"
+IROM_ADDR_TYPE = "inst_addr_t"
+XROM_MAX_SIZE = 256
+XROM_DATA_TYPE = "dmem_data_t"
+XROM_ADDR_TYPE = "dmem_addr_t"
+XROM_ENTITY_NAME = "xrom"
+OPC_LIST_NAME = __dir__ + "/opc.list"
+
+# --------------------------------------------------------
+class Parser
+	def curr_segment
+		@curr_segment
+	end	
+	def curr_segment=(arg)
+		@curr_segment=arg
+	end	
+	def add_label(labelname, addr)
+		@label_list = @label_list + [labelname, addr]
+	end
+	def	getLabelIdByName(label)
+		return @label_list.rindex(label)
+	end
+	def	getLabelNameById(id)
+		return @label_list[id]
+	end
+	def put_instr(name, lc, opc , op1 , op2)
+		if get_instr != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
+			exit 1
+		end
+		@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
+	end
+	def	get_instr
+		return @instr_list[@pc]
+	end
+	def put_xmem(value, lc)
+		if get_xmem != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
+			exit 1
+		end
+		@xmem[xmem_dc] = value
+		@xmem_dc = xmem_dc + 1
+	end	
+	def get_xmem
+		return @xmem[xmem_dc]
+	end	
+	def xmem
+		return @xmem
+	end	
+	def put_cmem(value, lc)
+		if get_cmem(page) != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
+			exit 1
+		end
+		@cmem[page][cmem_dc] = value
+		@cmem_dc[page] = cmem_dc + 1
+	end	
+	def get_cmem(pg)
+		return @cmem[pg][cmem_dc]
+	end	
+	def cmem(page)
+		return @cmem[page]
+	end	
+	def	cmem_dc=(addr)
+		@cmem_dc[page] = addr
+	end	
+	def	cmem_dc
+		@cmem_dc[page]
+	end	
+	def	xmem_dc=(addr)
+		@xmem_dc = addr
+	end	
+	def	xmem_dc
+		@xmem_dc
+	end	
+	def page=(page)
+		@page = page;
+	end	
+	def page
+		@page;
+	end	
+	def pc=(pc)
+		@pc = pc;
+		if (pc > @pc_max)
+			@pc_max = pc
+		end	
+	end	
+	def pc
+		@pc;
+	end	
+	def pc_max
+		@pc_max;
+	end	
+	def	instr_list
+		@instr_list
+	end
+	def	label_list
+		@label_list
+	end
+	
+	def initialize()
+		@pc_max = 0
+		@pc = 0					# Program counter
+		@cmem_dc = [0,0,0,0]	# chip data counter
+		@xmem_dc = 0			# xmem data counter
+		@curr_segment = "UNDEF";
+		@page = 0
+		@label_list=[[],[]]
+		@instr_list=[nil]
+		@cmem = [[],[]];
+		@xmem = [];
+	end
+	def method_missing(name, *args)
+		puts "I don't know the method #{name}"
+	end
+end	
+
+# --------------------------------------------------------
+def parse(name, obj)
+
+lc = 0	# Line counter
+file = File.open(name, "r")
+
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if obj.getLabelIdByName(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	token = iline_member[mc]
+	mcnt = iline_member.count{|x| !x.nil?}
+	if token
+		token = token.upcase
+	end
+	
+	case token
+	when nil
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%3.3X",obj.cmem_dc)
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%3.3X",obj.xmem_dc)
+		elsif obj.curr_segment == "CODE"
+			curr_addr = format("0x%3.3X",obj.pc)
+		else
+			STDERR.puts format("Error in line %d: Undefined segment", lc)
+			exit 1
+		end
+	when "INCLUDE"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		inc_name = iline_member[mc+1].delete("\"")
+		puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
+		parse(inc_name, obj)
+	when "EQU"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			curr_addr = format("0x%2.2X",eval(iline_member[mc+1..mcnt][0].to_s))
+		else 	
+			curr_addr = iline_member[mc+1]
+		end 	
+	when "ORG"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		offset = eval(iline_member[mc+1..mcnt][0].to_s)
+		case obj.curr_segment
+			when "CODE"
+			obj.pc = offset
+			curr_addr = format("0x%3.3X",obj.pc)
+			when "CMEM"
+			obj.cmem_dc = offset
+			when "XMEM"
+			obj.xmem_dc = offset
+			
+		end	
+	when "CODE"
+		curr_addr = format("0x%3.3X",obj.pc)
+		obj.curr_segment = "CODE";
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		obj.curr_segment = "CMEM";
+		obj.page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		obj.curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if obj.curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
+			exit 1
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			dc_old = obj.xmem_dc;
+			val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
+			
+			# Parse string literals
+			val_array.each do |item| 
+				if 0 == (item =~ /.*\".*\"/)
+					str = item.delete("\"")
+					for nn in (0..str.length-1)
+						value = str[nn].ord
+						obj.put_xmem(value, lc);
+						len += 1
+					end;
+				else
+					argument = item
+					obj.put_xmem(eval(argument), lc);
+					len += 1
+				end	
+			end	
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	when "DB"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		len = eval(iline_member[mc+1]).to_i
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%2.2X",obj.cmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
+			for nn in (1..len)
+				obj.put_cmem(0, lc)
+			end	
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
+			for nn in (1..len)
+				obj.put_xmem(0, lc)
+			end	
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	else
+		if obj.curr_segment != "CODE"
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end			
+
+		op_line = iline_member[mc+1..mcnt]
+		curr_addr = format("0x%3.3X",obj.pc)
+		opc = token
+		if iline_member[mc+1] != nil
+			op1 = op_line[0].to_s.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line[1].to_s.gsub(/,+.*$/, "")
+		end	
+		obj.put_instr(name, lc, opc, op1, op2)
+		obj.pc = obj.pc + 1
+	end;	
+
+	# Push labels
+	if label	
+		obj.add_label(label, curr_addr)
+	end
+end
+file.close
+return obj
+end
+
+# --------------------------------------------------------
+# Instruction formatting
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg[0].to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+first_pass = Parser.new();
+parse(filename, first_pass)
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+
+# ToDo: Use class-methods
+label_list = first_pass.label_list
+instr_list = first_pass.instr_list
+
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..2)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+		# checks R0 .. R16, Mnemonics
+		instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
+		if (nil != (instruct[subst_pos] =~ /'high/))
+			instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
+		end	
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = eval(instruct[opc_start+i+1].delete("()"))
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	if error
+		num_errors += 1
+		break
+	end
+
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	# Native instructions
+	when "NOP", "HALT", "RET", "RETI", "SETC"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "SUB|K|R", "SUBC|K|R"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	# Synthetic instructions
+	when "CLRC"
+		kk = 0;
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NEG|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|K|R").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NOT|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("XOR|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	# I-ROM VHDL-ROM
+	filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", IROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..[IROM_MAX_SIZE, pc].min-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("I-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM VHDL-ROM (loadable)
+	filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
+	file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (IROM_MAX_SIZE-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(IROM_MAX_SIZE-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM TCL-Loader
+	filename = format("%s.irom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
+	file.puts format("# User 1")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM
+	filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", XROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("X-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM (loadable)
+	filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
+	file.puts format("\t);\n")
+	puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM JTAG-Loader
+	filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
+	file.puts format("# User 2")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
+	for i in (0..first_pass.xmem.length-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
+	end;
+	puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{first_pass.pc_max} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	
+

Common/tools/jcpu/lib/cg.inc.jsm

@@ -0,0 +1,72 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xio-address equates for
+; reg_cg_char_addr:	equ		0xXX	; RW
+; reg_cg_line_addr:	equ		0xXX	; RW
+; reg_cg_data:		equ		0xXX	; RW
+; reg_cg_ctrl:		equ		0xXX	; WO
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+cg_clr_line:	push	R0
+				mov		R0, 2
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+cg_clr_screen:	push	R0
+				mov		R0, 1
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+; R0 : char address
+; R1 : line address
+cg_set_addr:	call	cg_wait_rdy
+				xout	(reg_cg_line_addr), R1
+				xout	(reg_cg_char_addr), R0
+				ret
+
+; -------------------------------------------------
+; R0 : character
+cg_putchar:		call	cg_wait_rdy
+				xout	(reg_cg_data), R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts:		push	R0
+cg_p_lp:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		ex_cgp
+				call	cg_putchar
+				jmp		cg_p_lp
+ex_cgp:			pop		R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_clr_puts:	call	cg_clr_line
+				call	cg_puts
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts_clr:	call	cg_puts
+				call	cg_clr_line
+				ret				
+
+; -------------------------------------------------
+cg_wait_rdy:	push	R0
+cg_wr_lp:		xin		R0, (reg_hwstat)
+				and		R0, 0x02
+				jz		cg_wr_lp
+				pop		R0
+				ret
+
+; -------------------------------------------------

Common/tools/jcpu/lib/cregs.inc.jsm

@@ -0,0 +1,7 @@
+; JCPU On-Chip register
+cpu_revision:		equ		0x00	; RO
+cpu_control:		equ		0x01	; R/W
+cpu_status:			equ		0x02	; RO
+cpu_int_ctrl:		equ		0x03	; RW
+cpu_cmem_high:		equ		0x04	; RW
+cpu_stack_high:		equ		0x05	; RW

Common/tools/jcpu/lib/delays.inc.jsm

@@ -0,0 +1,64 @@
+; -------------------------------------------------
+; Delays
+; -------------------------------------------------
+delay1s:		push	R15
+				mov		R15, 10
+loop1s:			call 	delay100ms		
+				dec		R15
+				jnz		loop1s
+				pop		R15
+				ret
+
+delay100ms:		push	R15
+				mov		R15, 10
+loop100ms:		call 	delay10ms		
+				dec		R15
+				jnz		loop100ms
+				pop		R15
+				ret
+			
+delay10ms:		push	R15
+				mov		R15, 10
+loop10ms:		call	delay1ms		
+				dec		R15
+				jnz		loop10ms
+				pop		R15
+				ret
+		
+delay1ms:		push	R15
+				mov		R15, 10
+loop1ms:		call	delay100us
+				dec		R15
+				jnz		loop1ms
+				pop		R15
+				ret
+
+delay100us:		push	R15
+				mov		R15, 10
+loop100us:		call	delay10us
+				dec		R15
+				jnz		loop100us
+				pop		R15
+				ret
+
+delay10us:		push	R15
+				mov		R15, 99
+loop10us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop10us
+				pop		R15
+				ret
+
+delay1us:		push	R15
+				mov		R15, 9
+loop1us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop1us
+				pop		R15
+				ret
+				
+; -------------------------------------------------

Common/tools/jcpu/lib/lcd.inc.jsm

@@ -0,0 +1,208 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - lcd_port (LCD-Base)
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+lcd_cmd:		equ		0x00
+lcd_rd:			equ		0x20
+lcd_data:		equ		0x40
+lcd_enable:		equ		0x80
+
+LCD_CMD_Z1:		equ		0x80
+LCD_CMD_Z2:		equ		0xC0
+LCD_CMD_CLEAR:	equ		0x01
+
+; -------------------------------------------------
+; Init LCD
+; -------------------------------------------------
+LCD_init:		mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+				mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+
+				mov		R2, 0x00		
+				mov		R0, 0x02
+				call	_write_lcd
+				call	delay1ms
+
+				; 1. Function set: 4-Bit mode, two display lines
+				mov		R0, 0x28
+				call	LCD_writecmd
+
+				; 2. Display on, no cursor
+				mov		R0, 0x0C		
+				call	LCD_writecmd
+
+				; 3. Cursor shift during write
+				mov		R0, 0x06
+				call	LCD_writecmd
+
+				; 4. Display clear
+				mov		R0, 0x01
+				call	LCD_writecmd
+
+				ret
+				
+; -------------------------------------------------
+; LCD_waitbsy
+; -------------------------------------------------
+LCD_waitbsy:	push	R0
+bsy_loop:		call	LCD_readstat
+				and		R0, 0x80
+				jz		ex_bsy
+				call	delay1us
+				jmp		bsy_loop
+ex_bsy:			pop		R0
+				ret
+
+; -------------------------------------------------
+; LCD_writecmd
+; -------------------------------------------------
+; R0 = cmd
+LCD_writeaddr:
+LCD_writecmd:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_write
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_putsx
+; -------------------------------------------------
+; R1 = address of null-terminated string in XMEM
+LCD_putsx:		push	R0
+putsx_loop:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsx_ex
+				call	LCD_writechar
+				jmp		putsx_loop
+putsx_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_putsc
+; -------------------------------------------------
+; R1 = address of null-terminated string in CMEM
+LCD_putsc:		push	R0
+putsc_loop:		movc	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsc_ex
+				call	LCD_writechar
+				jmp		putsc_loop
+putsc_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_writechar
+; -------------------------------------------------
+; R0 = char
+LCD_writedata:
+LCD_writechar:	push	R2
+				mov		R2, lcd_data
+				call	LCD_write
+				pop		R2
+				ret
+				
+; -------------------------------------------------
+; LCD_write
+; -------------------------------------------------
+; R0 = input
+; R2 = register
+LCD_write:		call	LCD_waitbsy
+				push	R0
+				swap	R0
+				call	_write_lcd
+				pop		R0
+				call	_write_lcd
+				ret
+
+; -------------------------------------------------
+; LCD_readstat
+; -------------------------------------------------
+; R0 = status
+LCD_readstat:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_read
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_read
+; -------------------------------------------------
+; R0 = output
+; R2 = register
+LCD_read:		call	_read_lcd
+				swap	R0
+				push	R0
+				call	_read_lcd
+				pop		R2
+				or		R0, R2
+				ret
+				
+; -------------------------------------------------
+; _write
+; -------------------------------------------------
+; R0 = input
+_write_lcd:		push	R1
+
+				and		R0, 0x0F
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				or		R1, lcd_rd
+				xout	(lcd_port), R1
+
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; _read
+; -------------------------------------------------
+; R0 = output
+_read_lcd:		push	R1
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+				xin		R0, (lcd_port)
+				and		R0, 0x0F
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				pop		R1
+				ret
+
+				

Common/tools/jcpu/lib/mul8x8.inc.jsm

@@ -0,0 +1,42 @@
+; -------------------------------------------------
+; mul8x8.inc.jsm
+; -------------------------------------------------
+
+; -------------------------------------------------
+; Parameter:
+; R0 : operand 1
+; R1 : operand 2
+; Return:
+; R0 : product low
+; R1 : product high
+mul8x8:			push	R2
+				push	R3
+				push	R4
+				
+				mov		R4, R1
+				mov		R1, 0
+				mov		R2, 0
+				mov		R3, 0
+				
+loop1:			cmp		R4, 0x01
+				jeq		ende1
+
+				shr		R4
+				jnc		next1
+
+				add		R2, R0
+				addc	R3, R1
+
+next1:			shl		R0
+				rolc	R1
+				jmp		loop1
+				
+ende1:			add		R0, R2
+				addc	R1, R3
+				
+				pop		R4
+				pop		R3
+				pop		R2
+				ret
+
+; -------------------------------------------------

Common/tools/jcpu/lib/uart.inc.jsm

@@ -0,0 +1,58 @@
+; -------------------------------------------------
+; uart.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - uart_status (Status register)
+; - uart_data	(Data register)
+UART_TX_EMPTY:		equ		0x01
+UART_TX_FULL:		equ		0x02
+UART_TX_CMPL:		equ		0x04
+UART_RX_PRESENT:	equ		0x10
+
+; -------------------------------------------------
+; uart_puts
+; -------------------------------------------------
+; R1 : ptr to string
+uart_puts:		push	R0
+u_p_lp:			movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		ex_ugp
+				call	uart_putchar
+				jmp		u_p_lp
+ex_ugp:			pop		R0
+				ret				
+
+
+; -------------------------------------------------
+; uart_putchar
+; -------------------------------------------------
+; R0 = input
+uart_putchar:	jmp sout
+
+; -------------------------------------------------
+; sout
+; -------------------------------------------------
+; R0 = input
+sout:			push 	R1
+sout1:			xin		R1, (uart_status)
+				and		R1, UART_TX_FULL
+				jnz		sout1
+				xout	(uart_data), R0
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; sin
+; -------------------------------------------------
+; R0 = output
+sin:			push 	R1
+sin1:			xin		R1, (uart_status)
+				and		R1, UART_RX_PRESENT
+				jnz		sin1
+				xin		R0, (uart_data)
+				pop		R1
+				ret
+
+; -------------------------------------------------
+

Common/tools/jcpu/lib/utils.inc.jsm

@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; utils.inc.jsm
+; -------------------------------------------------
+
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value in lower nibble
+; Return
+; R0 : Hex character representing lower nibble
+nibble2hex:		and		R0, 0x0F
+				cmp		R0, 0x0A
+				jlt		isNum1
+				add		R0, 0x07
+isNum1:			add		R0, 0x30
+				ret
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value
+; Return
+; R0 : Hex character high
+; R1 : Hex character low
+bin2hex:		push	R0
+				call	nibble2hex
+				mov		R1, R0
+				pop		R0
+				swap	R0
+				call	nibble2hex
+				ret
+
+; -------------------------------------------------

Common/tools/jcpu/opc.list

@@ -0,0 +1,64 @@
+0 NOP         
+1 HALT        
+2 MOV|R|R     
+3 MOV|R|K     
+4 MOVX|R|Ri   
+5 MOVX|R|Ki   
+6 MOVX|Ri|R   
+7 MOVX|Ri|K   
+8 MOVX|Ki|R   
+9 MOVC|R|Ri   
+10 MOVC|R|Ki   
+11 MOVC|Ri|R   
+12 MOVC|Ri|K   
+13 MOVC|Ki|R   
+14 CMP|R|R     
+15 CMP|R|K     
+16 ADD|R|R     
+17 ADD|R|K     
+18 ADDC|R|R    
+19 ADDC|R|K    
+20 SUB|R|R     
+21 SUB|R|K     
+22 SUBC|R|R    
+23 SUBC|R|K    
+24 AND|R|R     
+25 AND|R|K     
+26 OR|R|R      
+27 OR|R|K      
+28 XOR|R|R     
+29 XOR|R|K     
+30 SHL|R       
+31 SHR|R       
+32 ROL|R       
+33 ROR|R       
+34 ROLC|R      
+35 RORC|R      
+36 XOUT|Ki|R   
+37 XOUT|Ri|K   
+38 COUT|Ki|R   
+39 COUT|Ri|K   
+40 XIN|R|Ki    
+41 CIN|R|Ki    
+42 SWAP|R      
+43 SETC        
+44 UNDEF       
+45 UNDEF       
+46 SUB|K|R     
+47 SUBC|K|R    
+48 JMP|K       
+49 JZ|K        
+50 JNZ|K       
+51 JC|K        
+52 JNC|K       
+53 JLT|K       
+54 JGT|K       
+55 JLE|K       
+56 JGE|K       
+57 JEQ|K       
+58 JNE|K       
+59 CALL|K      
+60 PUSH|R      
+61 POP|R       
+62 RET         
+63 RETI        

Common/tools/jcpu/regx.rb

@@ -0,0 +1,20 @@
+#!/usr/bin/env ruby
+
+st = "\033[7m"
+en = "\033[m"
+
+ while TRUE
+   print "str> "
+   STDOUT.flush
+   str = gets
+   break if not str
+   str.chop!
+   print "pat> "
+   STDOUT.flush
+   re = gets
+   break if not re
+   re.chop!
+   str.gsub! re, "#{st}\\&#{en}"
+   print str, "\n"
+end
+print "\n"

Common/tools/jcpu/rom.tcl.tpl

@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

Common/tools/jcpu/templates.rb

@@ -0,0 +1,44 @@
+#!/usr/bin/env ruby
+
+
+template = <<'END'
+		-- (tv #1342) read output FIFO
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait while FIFO is read
+		(
+			cycles		=>	2,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait for ack
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_read_ack(dat => #{exp_data}),
+			irq			=>	(others => '0')
+		),
+
+END
+
+puts "KS-128 testvectors:\n"
+puts "\n" * 3
+
+
+0.upto(10) { |sk_no|
+	3.downto(0) { |sl_no|
+		exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
+		t = template.gsub(/"/, '\\"')
+		puts eval("format(\"#{t}\")")
+	}
+}

Common/tools/jcpu/xrom.vhd.tpl

@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+

Common/tools/jcpu/xrom_ld.vhd.tpl

@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

Common/tools/mips/Makefile

@@ -0,0 +1,26 @@
+CFLAGS=-O2
+CC=gcc
+PREFIX=/usr/local
+all: romgen ramgen flashgen flashgen_tlb packhex
+
+romgen: ./src/romgen.c
+	$(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen
+
+ramgen: ./src/ramgen.c
+	$(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen
+
+flashgen: ./src/flashgen.c
+	$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen
+
+flashgen_tlb: ./src/flashgen.c
+	$(CC) $(CFLAGS) -DSDRAM_BASE=0x80000000 -DFLASH_BASE_MEM=0x88000000 ./src/flashgen.c -lm -o ./flashgen_tlb
+
+packhex: ./src/packhex.c
+	$(CC) $(CFLAGS) ./src/packhex.c -lm -o ./packhex
+
+install:
+	cp romgen $(PREFIX)/bin
+	cp ramgen $(PREFIX)/bin
+	cp flashgen $(PREFIX)/bin
+clean:
+	rm -rf romgen* ramgen* flashgen*

Common/tools/mips/src/flashgen.c

@@ -0,0 +1,187 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include <stdint.h>
+
+#ifndef SDRAM_BASE
+#define SDRAM_BASE			0x40000000
+#endif
+#ifndef FLASH_BASE_MEM
+#define FLASH_BASE_MEM		0x00000000
+#endif
+
+#define	MAGIC		0x4A464931	// "JFI1" in big-endian;
+
+uint8_t _g_bytes[4] = {0x12, 0x34, 0x56, 0x78};
+uint8_t _g_bytes2[4] = {0};
+
+int IsEndianBig(void)
+{
+	int i, result;
+
+	uint8_t *pBuf8;
+	uint16_t *pBuf16;
+	uint32_t *pBuf32;
+	uint16_t halve;
+	uint32_t word;
+
+
+	halve = 0x1234;
+	word = 0x12345678;
+
+	result = -1;
+
+	for (i=0; i < 4; i++)
+		_g_bytes2[i] = _g_bytes[i];
+
+	pBuf8 = (uint8_t*)&word;
+	if (((*pBuf8+0) == 0x12) && (*(pBuf8+1) == 0x34) && (*(pBuf8+2) == 0x56) && (*(pBuf8+3) == 0x78))
+	{
+		pBuf8 = (uint8_t*)&halve;
+		if (((*pBuf8+0) == 0x12) && (*(pBuf8+1) == 0x34))
+		{
+			result = 1;
+		}
+	}
+
+	pBuf8 = (uint8_t*)&word;
+	if (((*pBuf8+0) == 0x78) && (*(pBuf8+1) == 0x56) && (*(pBuf8+2) == 0x34) && (*(pBuf8+3) == 0x12))
+	{
+		pBuf8 = (uint8_t*)&halve;
+		if (((*pBuf8+0) == 0x34) && (*(pBuf8+1) == 0x12))
+		{
+			result = 0;
+		}
+	}
+	return result;
+}
+
+uint32_t conv_endian32(uint32_t src)
+{
+	uint32_t dst;
+
+	dst = (0xFF000000 & (src << 24))
+		| (0x00FF0000 & (src << 8))
+		| (0x0000FF00 & (src >> 8))
+		| (0x000000FF & (src >> 24));
+
+	return dst;
+};
+
+// --------------------------------------------------------------
+typedef struct _sflash_img_hdr_t
+{
+	uint32_t magic;
+	uint32_t target_addr;
+	uint32_t img_offset;
+	uint32_t img_size;
+	uint32_t hdr_next;
+	uint8_t img_name[128];
+	uint8_t res[108];
+
+} flash_img_hdr_t;
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+// --------------------------------------------------------------
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_flash[1024];
+	char name_prj[1024];
+	char *pBuf;
+	uint32_t *pBuf32;
+	flash_img_hdr_t img_hdr = {0};
+
+	FILE *pFile;
+	int filesize;
+	long start, end;
+	int i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: flashgen <input file> [-{EL|EB}]\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	pFile = fopen(pFilenameIn, "rb");
+	if (!pFile)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_flash, "%s.flash.bin", name_prj);
+
+	// determine filesize
+	fseek(pFile, 0, SEEK_SET);
+	start = ftell(pFile);
+	fseek(pFile, 0, SEEK_END);
+	end = ftell(pFile);
+	fseek(pFile, 0, SEEK_SET);
+	filesize = (end-start);
+
+	pBuf = (char*)malloc(filesize);
+	filesize = fread(pBuf, 1, filesize, pFile);
+
+	fclose(pFile);
+
+	pFile = fopen(name_flash, "wb");
+	if (!pFile)
+	{
+		fprintf(stderr, "Error opening file %s\n", name_flash);
+		return 1;
+	}
+
+	img_hdr.magic = MAGIC;
+
+	img_hdr.target_addr = SDRAM_BASE;
+	img_hdr.img_size = filesize;
+	img_hdr.img_offset = FLASH_BASE_MEM + sizeof(flash_img_hdr_t);
+	img_hdr.hdr_next = FLASH_BASE_MEM;
+
+	if (argc == 3)
+	{
+		if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B'))
+		{
+			if (1 == IsEndianBig())
+			{
+				img_hdr.magic = conv_endian32(MAGIC);
+				pBuf32 = (uint32_t*)pBuf;
+				for (i=0; i < filesize/4; i ++)
+					pBuf32[i] = pBuf32[i];			// don't convert data
+			}
+			else
+			{
+				pBuf32 = (uint32_t*)pBuf;
+				for (i=0; i < filesize/4; i ++)
+					pBuf32[i] = conv_endian32(pBuf32[i]);	// convert data
+			}
+		}
+	}
+	fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
+	fwrite(pBuf, 1, filesize, pFile);
+
+	fclose(pFile);
+
+	return 0;
+}
+

Common/tools/mips/src/packhex.c

@@ -0,0 +1,568 @@
+
+/*****  P A C K H E X . C  ************************************************
+ *
+ *   Packhex is a hex-file compaction utility.  It attempts to concatenate
+ *   hex records to produce more size-efficient packaging.
+ *
+ *   Limitations: Input files must be correctly formatted.  This utility
+ *                is not robust enough to detect hex-record formatting
+ *                errors.
+ *
+ *   Published:   May 1993 Embedded Systems Programming magazine
+ *                "Creating Faster Hex Files"
+ *
+ *   URL:         ESP magazine: http://www.embedded.com
+ *                Source Code:  ftp://ftp.mfi.com/pub/espmag/1993/pakhex.zip
+ *
+ *   Author:      Mark Gringrich
+ *
+ *   Compiler:    Microsoft C 6.0
+ *                cl /F 1000 packhex.c
+ *
+ *
+ *   $Id: packhex.c,v 1.9 2004/04/20 07:07:08 ralf Exp $
+ *
+ **************************************************************************/
+
+
+/* #define SMALLER_RECORDS */
+#ifdef SMALLER_RECORDS
+#define MAX_LEN_S1_RECS 128
+#define MAX_LEN_S2_RECS 128
+#define MAX_LEN_S3_RECS 128
+#else
+#define MAX_LEN_S1_RECS 252
+#define MAX_LEN_S2_RECS 251
+#define MAX_LEN_S3_RECS 250
+#endif
+
+
+/*--------------------------------- includes ---------------------------------*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#if 0
+#include "config.h"
+
+#ifndef VMS
+#ifndef HAVE_STRERROR
+extern int sys_nerr;
+extern char *sys_errlist[];
+
+#define strerror( _err ) \
+  ((_err) < sys_nerr) ? sys_errlist [(_err)] : "unknown error"
+
+#else   /* HAVE_STRERROR */
+char *strerror ();
+#endif
+#else   /* VMS */
+char *strerror (int,...);
+#endif
+#endif
+
+#if defined(__unix__) && !defined(EXIT_FAILURE)
+#define EXIT_FAILURE -1
+#define EXIT_SUCCESS  0
+#endif
+
+/*--------------------------------- defines ----------------------------------*/
+
+#define YES                   1
+#define MAX_LINE_SIZE       600
+#define EOS                 '\0'
+
+
+/*---------------------------------- macros ----------------------------------*/
+
+/* Convert ASCII hexadecimal digit to value. */
+
+#define HEX_DIGIT( C )   ( ( ( ( C ) > '9' ) ? ( C ) + 25 : ( C ) ) & 0xF )
+
+
+/*--------------------------------- typedefs ---------------------------------*/
+
+typedef unsigned char   Boolean;
+typedef unsigned char   Uchar;
+typedef unsigned int    Uint;
+typedef unsigned long   Ulong;
+
+typedef struct   /* Functions and constant returning Hex-record vital stats. */
+{
+    Boolean    ( *is_data_record  )( char *              );
+    Ulong      ( *get_address     )( char *              );
+    Uint       ( *get_data_count  )( char *              );
+    const Uint    max_data_count;
+    char      *( *get_data_start  )( char *              );
+    void       ( *put_data_record )( Uint, Ulong, char * );
+} Rec_vitals;
+
+
+/*--------------------------- function prototypes ----------------------------*/
+
+Rec_vitals  * identify_first_data_record( char *, int );
+Ulong         get_ndigit_hex( char *, int );
+
+
+/*----------------------------- Intel Hex format -----------------------------*/
+
+/*
+ *    Intel Hex data-record layout
+ *
+ *    :aabbbbccd...dee
+ *
+ *    :      - header character
+ *    aa     - record data byte count, a 2-digit hex value
+ *    bbbb   - record address, a 4-digit hex value
+ *    cc     - record type, a 2-digit hex value:
+ *              "00" is a data record
+ *              "01" is an end-of-data record
+ *              "02" is an extended-address record
+ *              "03" is a start record
+ *    d...d  - data (always an even number of chars)
+ *    ee     - record checksum, a 2-digit hex value
+ *             checksum = 2's complement
+ *                 [ (sum of bytes: aabbbbccd...d) modulo 256 ]
+ */
+
+
+Boolean is_intel_data_rec( char * rec_str )
+{
+    return( ( rec_str[ 0 ] == ':' )  &&  ( rec_str[ 8 ] == '0' ) );
+}
+
+Uint get_intel_rec_data_count( char * rec_str )
+{
+    return( ( Uint ) get_ndigit_hex( rec_str + 1, 2 ) );
+}
+
+Ulong get_intel_rec_address( char * rec_str )
+{
+    return( get_ndigit_hex( rec_str + 3, 4 ) );
+}
+
+char * get_intel_rec_data_start( char * rec_str )
+{
+    return( rec_str + 9 );
+}
+
+void put_intel_data_rec( Uint count, Ulong address, char * data_str )
+{
+    char    *ptr;
+    Uint    sum = count + ( address >> 8 & 0xff ) + ( address & 0xff );
+
+    for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
+        sum += ( Uint ) get_ndigit_hex( ptr, 2 );
+
+    printf(
+      ":%02X%04lX00%s%02X\n", count, address, data_str, (~sum + 1) & 0xff
+    );
+}
+
+
+Rec_vitals  intel_hex =
+{
+    is_intel_data_rec,
+    get_intel_rec_address,
+    get_intel_rec_data_count,
+    255,                        /* Maximum data bytes in a record. */
+    get_intel_rec_data_start,
+    put_intel_data_rec
+};
+
+
+/*------------------------- Motorola S1-record format ------------------------*/
+
+/*
+ *    Motorola S-record data-record layout
+ *
+ *    Sabbc...cd...dee
+ *
+ *    S      - header character
+ *    a      - record type, a 1-digit value:
+ *               "0" is a header record
+ *               "1" is a 2-byte-address data record
+ *               "2" is a 3-byte-address data record
+ *               "3" is a 4-byte-address data record
+ *               "7" is a 4-byte-address end-of-data record
+ *               "8" is a 3-byte-address end-of-data record
+ *               "9" is a 2-byte-address end-of-data record
+ *    bb     - record length in bytes, a 2-digit hex value
+ *             (record length doesn't count the header/type
+ *              chars and checksum byte)
+ *    c...c  - record address, a 4-, 6-, or 8-digit value,
+ *               depending on record type
+ *    d...d  - data (always an even number of chars)
+ *    ee     - record checksum, a 2-digit hex value
+ *             checksum = 1's complement
+ *             [ (sum of all bytes: bbc..cd...d) modulo 256 ]
+ */
+
+#define S1_COUNT_OFFSET         3
+
+
+Boolean is_moto_s1_data_rec( char * rec_str )
+{
+    return ( ( rec_str[ 0 ] == 'S' )  &&  ( rec_str[ 1 ] == '1' ) );
+}
+
+Uint get_moto_s1_rec_data_count( char * rec_str )
+{
+    return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S1_COUNT_OFFSET );
+}
+
+Ulong get_moto_s1_rec_address( char * rec_str )
+{
+    return( get_ndigit_hex( rec_str + 4, 4 ) );
+}
+
+char * get_moto_s1_rec_data_start( char * rec_str )
+{
+    return( rec_str + 8 );
+}
+
+void put_moto_s1_data_rec( Uint count, Ulong address, char * data_str )
+{
+    char   *ptr;
+    Uint    sum = S1_COUNT_OFFSET + count +
+                    ( address >> 8 & 0xff ) + ( address & 0xff );
+
+    for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
+        sum += ( Uint ) get_ndigit_hex( ptr, 2 );
+
+    printf(
+      "S1%02X%04lX%s%02X\n",
+      count + S1_COUNT_OFFSET, address, data_str, ~sum & 0xff
+    );
+}
+
+
+Rec_vitals  motorola_s1_rec =
+{
+    is_moto_s1_data_rec,
+    get_moto_s1_rec_address,
+    get_moto_s1_rec_data_count,
+    MAX_LEN_S1_RECS,            /* Maximum data bytes in a record. */
+    get_moto_s1_rec_data_start,
+    put_moto_s1_data_rec
+};
+
+
+/*------------------------- Motorola S2-record format ------------------------*/
+
+#define S2_COUNT_OFFSET         4
+
+Boolean is_moto_s2_data_rec( char * rec_str )
+{
+    return ( ( rec_str[ 0 ] == 'S' )  &&  ( rec_str[ 1 ] == '2' ) );
+}
+
+Uint get_moto_s2_rec_data_count( char * rec_str )
+{
+    return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S2_COUNT_OFFSET );
+}
+
+Ulong get_moto_s2_rec_address( char * rec_str )
+{
+    return( get_ndigit_hex( rec_str + 4, 6 ) );
+}
+
+char * get_moto_s2_rec_data_start( char * rec_str )
+{
+    return( rec_str + 10 );
+}
+
+void put_moto_s2_data_rec( Uint count, Ulong address, char * data_str )
+{
+    char    *ptr;
+    Uint    sum = S2_COUNT_OFFSET + count + ( address >> 16 & 0xff ) +
+                                            ( address >>  8 & 0xff ) +
+                                            ( address       & 0xff );
+
+    for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
+        sum += ( Uint ) get_ndigit_hex( ptr, 2 );
+
+    printf(
+      "S2%02X%06lX%s%02X\n",
+      count + S2_COUNT_OFFSET, address, data_str, ~sum & 0xff
+    );
+}
+
+
+Rec_vitals  motorola_s2_rec =
+{
+    is_moto_s2_data_rec,
+    get_moto_s2_rec_address,
+    get_moto_s2_rec_data_count,
+    MAX_LEN_S2_RECS,            /* Maximum data bytes in a record. */
+    get_moto_s2_rec_data_start,
+    put_moto_s2_data_rec
+};
+
+
+/*------------------------- Motorola S3-record format ------------------------*/
+
+#define S3_COUNT_OFFSET         5
+
+Boolean is_moto_s3_data_rec( char * rec_str )
+{
+    return ( ( rec_str[ 0 ] == 'S' )  &&  ( rec_str[ 1 ] == '3' ) );
+}
+
+Uint get_moto_s3_rec_data_count( char * rec_str )
+{
+    return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S3_COUNT_OFFSET );
+}
+
+Ulong get_moto_s3_rec_address( char * rec_str )
+{
+    return( get_ndigit_hex( rec_str + 4, 8 ) );
+}
+
+char * get_moto_s3_rec_data_start( char * rec_str )
+{
+    return( rec_str + 12 );
+}
+
+void put_moto_s3_data_rec( Uint count, Ulong address, char * data_str )
+{
+    char    *ptr;
+    Uint     sum = S3_COUNT_OFFSET + count + ( address >> 24 & 0xff ) +
+                                             ( address >> 16 & 0xff ) +
+                                             ( address >>  8 & 0xff ) +
+                                             ( address       & 0xff );
+
+    for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
+        sum += ( Uint ) get_ndigit_hex( ptr, 2 );
+
+    printf(
+      "S3%02X%08lX%s%02X\n",
+      count + S3_COUNT_OFFSET, address, data_str, ~sum & 0xff
+   );
+}
+
+
+Rec_vitals  motorola_s3_rec =
+{
+    is_moto_s3_data_rec,
+    get_moto_s3_rec_address,
+    get_moto_s3_rec_data_count,
+    MAX_LEN_S3_RECS,            /* Maximum data bytes in a record. */
+    get_moto_s3_rec_data_start,
+    put_moto_s3_data_rec
+};
+
+
+/*-------------------- Put your favorite hex format here ---------------------*/
+
+/*
+ *    * * *  The following is a template for an additional hex format:  * * *
+ *
+ *
+ *    Boolean is_X_data_rec( char * rec_str ) {}
+ *
+ *    Uint get_X_rec_data_count( char * rec_str ) {}
+ *
+ *    Ulong get_X_rec_address( char * rec_str ) {}
+ *
+ *    char * get_X_rec_data_start( char * rec_str ) {}
+ *
+ *    void put_X_data_rec( Uint count, Ulong address, char * data_str ) {}
+ *
+ *    Rec_vitals  X_rec =
+ *    {
+ *        is_X_data_rec,
+ *        get_X_rec_address,
+ *        get_X_rec_data_count,
+ *        MAXIMUM DATA BYTES IN A RECORD,
+ *        get_X_rec_data_start,
+ *        put_X_data_rec
+ *    };
+ *
+ */
+
+/*----------------------------------------------------------------------------*/
+
+
+/*
+ *   Put address of additional Rec_vitals structures
+ *   in this array, before the NULL entry.
+ */
+
+Rec_vitals  *formats[] =
+{
+    &intel_hex,
+    &motorola_s1_rec,
+    &motorola_s2_rec,
+    &motorola_s3_rec,
+    ( Rec_vitals * ) NULL
+};
+
+
+/****   main   *****************************************************************
+*
+*
+*       Expects: Nothing (no command-line parameters).
+*
+*       Returns: Exit status (EXIT_SUCCESS or EXIT_FAILURE).
+*
+*       Reads hex records on the standard input and attempts to
+*       splice adjacent data fields together.  Results appear on
+*       the standard output.
+*
+*******************************************************************************/
+
+int main(
+  int argc,
+  char **argv
+)
+{
+
+    char       inbuff[ MAX_LINE_SIZE ], outbuff[ MAX_LINE_SIZE ];
+    char       *in_dptr, *out_dptr;
+    int        d_total, d_count, d_excess, n;
+    int        length;
+    Ulong      in_rec_addr, out_rec_addr = 0;
+    Rec_vitals *rptr;
+
+
+    /* Sift through file until first hex record is identified.    */
+
+    rptr = identify_first_data_record( inbuff, MAX_LINE_SIZE );
+    if ( rptr == NULL )
+    {
+        fputs( "No hex records found.\n", stderr );
+        exit( EXIT_FAILURE );
+    }
+
+
+    /* Attempt data-record splicing until end-of-file is reached. */
+    d_total = 0;
+    for (;;) {
+        if ( rptr->is_data_record( inbuff ) == YES )
+        { /* Input record is a data record. */
+            d_count     = rptr->get_data_count( inbuff );
+            in_rec_addr = rptr->get_address( inbuff );
+            in_dptr     = rptr->get_data_start( inbuff );
+
+            if ( d_total == 0  ||  in_rec_addr != out_rec_addr + d_total )
+            { /* Begin a new output record. */
+                if ( d_total != 0 )
+                    rptr->put_data_record( d_total, out_rec_addr, outbuff );
+                out_dptr     = outbuff;
+                n = d_total  = d_count;
+                out_rec_addr = in_rec_addr;
+            }
+            else if
+              ( ( d_excess = d_total + d_count - rptr->max_data_count ) > 0 )
+            { /* Output a maximum-length record, then start a new record. */
+                strncat( outbuff, in_dptr, 2 * ( d_count - d_excess ) );
+                rptr->put_data_record(
+                  rptr->max_data_count, out_rec_addr, outbuff
+                );
+                in_dptr      += 2 * ( d_count - d_excess );
+                out_dptr      = outbuff;
+                n = d_total   = d_excess;
+                out_rec_addr += rptr->max_data_count;
+            }
+            else
+            { /* Append input record's data field with accumulated data. */
+                out_dptr = outbuff + ( 2 * d_total );
+                d_total += n = d_count;
+            }
+            strncpy( out_dptr, in_dptr, 2 * n );
+            out_dptr[ 2 * n ] = EOS;
+        }
+        else
+        { /* Not a data record;
+           * flush accumulated data then echo non-data record.
+           */
+            if ( d_total != 0 )
+            {
+                rptr->put_data_record( d_total, out_rec_addr, outbuff );
+                d_total = 0;
+            }
+            puts( inbuff );
+        }
+
+        inbuff[ MAX_LINE_SIZE - 1 ] = '\0';
+        if ( !fgets( inbuff, MAX_LINE_SIZE, stdin ) )
+           break;
+        if ( inbuff[ MAX_LINE_SIZE - 1 ] ) {
+           fprintf( stderr, "Input line too long" );
+           exit( 1 );
+        }
+        length = strlen(inbuff);
+        inbuff[length - 1] = '\0';
+
+    }
+
+
+    return ( EXIT_SUCCESS );
+
+}
+
+
+/****   identify_first_data_record   *******************************************
+*
+*       Expects: Pointer to hex-record line buffer.
+*
+*       Returns: Pointer to hex-record structure (NULL if no match found).
+*
+*       Reads the standard input, line by line, searching for a valid
+*       record header character.  If a valid header is found, a pointer
+*       to the hex-record's type structure is returned, otherwise NULL.
+*
+*       The input-stream pointer is left pointing to the first valid hex record.
+*
+*******************************************************************************/
+
+Rec_vitals * identify_first_data_record( char * buff_ptr, int max_length )
+{
+    Rec_vitals  ** ptr;
+    int            length;
+
+
+
+    for ( ;; ) {
+
+        buff_ptr[ max_length - 1 ] = '\0';
+        if ( !fgets( buff_ptr, max_length, stdin ) )
+           break;
+        if ( buff_ptr[ max_length - 1 ] ) {
+           fprintf( stderr, "Input line too long" );
+           exit( 1 );
+        }
+        length = strlen(buff_ptr);
+        buff_ptr[length - 1] = '\0';
+
+        for ( ptr = formats ; *ptr != ( Rec_vitals * ) NULL ; ptr++ )
+            if ( ( *ptr )->is_data_record( buff_ptr ) == YES )
+                return( *ptr );        /* Successful return.        */
+
+        puts( buff_ptr );              /* Echo non-hex-record line. */
+    }
+
+    return( ( Rec_vitals * ) NULL );   /* Unsuccessful return.      */
+}
+
+
+/****   get_ndigit_hex   *******************************************************
+*
+*       Expects: Pointer to first ASCII hexadecimal digit, number of digits.
+*
+*       Returns: Value of hexadecimal string as an unsigned long.
+*
+*******************************************************************************/
+
+Ulong get_ndigit_hex( char * cptr, int digits )
+{
+    Ulong    value;
+
+    for ( value = 0 ; --digits >= 0 ; cptr++ )
+        value = ( value * 16L ) + HEX_DIGIT( *cptr );
+
+    return( value );
+}
+

Common/tools/mips/src/ramgen.c

@@ -0,0 +1,387 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"ram"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) then\n");
+	fprintf(pFileOut, "\t\t\tif ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 2\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom_tcl[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+

Common/tools/mips/src/romgen.c

@@ -0,0 +1,430 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define INT8    char
+#define INT16   short
+#define INT32   long
+#define UINT8   unsigned char
+#define UINT16  unsigned short
+#define UINT32  unsigned long
+#define INT     int
+#define UINT    unsigned int
+#define FLOAT32 float
+#define FLOAT64 double
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"rom"
+#define JTAG_ADDR_WIDTH		16
+
+UINT32 g_endianess_EB;
+
+// --------------------------------------------------------------
+UINT32 conv_endian32(UINT32 src)
+{
+	UINT32 dst;
+
+	dst = (0xFF000000 & (src << 24))
+		| (0x00FF0000 & (src << 8))
+		| (0x0000FF00 & (src >> 8))
+		| (0x000000FF & (src >> 24));
+
+	return dst;
+};
+
+UINT32 to_big_endian32(UINT32 src)
+{
+#ifndef NATIVE_IS_BIG_ENDIAN
+	return conv_endian32(src);
+#else
+	return src;
+#endif
+}
+
+UINT32 from_big_endian32(UINT32 src)
+{
+#ifndef NATIVE_IS_BIG_ENDIAN
+	return conv_endian32(src);
+#else
+	return src;
+#endif
+}
+
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		if (g_endianess_EB)
+			fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
+		else
+			fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) then\n");
+	fprintf(pFileOut, "\t\t\tif ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		if (g_endianess_EB)
+			fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
+		else
+			fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] =
+	{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 1\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		if (g_endianess_EB)
+			fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word));
+		else
+			fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+	char name_rom_tcl[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: romgen <input file> <num. word address bits> [-{EL|EB}]\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	nbits_addr = atoi(argv[2]);
+
+	g_endianess_EB = 0;
+	if (argc == 4)
+	{
+		if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B'))
+			g_endianess_EB = 1;
+	}
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+

defs.mk

@@ -0,0 +1,2 @@
+LIB_PATH := $(VHDL_HOME)/lib
+VHDL_MAKE_HOME := $(VHDL_HOME)/Common/make

lib/CPUs/JCpu/Makefile

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 TOOL_PATH := $(VHDL_HOME)/tools/jcpu
 
 .PHONY: install uninstall

lib/CPUs/JCpu/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+*.wopt
+

lib/CPUs/JCpu/ghdl/cpu_embedded.gtkw

@@ -1,24 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Sun Mar 21 20:24:10 2021
-[*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_embedded/cpu_embedded.ghw"
-[dumpfile_mtime] "Sun Mar 21 20:24:02 2021"
-[dumpfile_size] 23928
-[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_embedded/cpu_embedded.gtkw"
-[timestart] 0
-[size] 1000 600
-[pos] -1 -1
-*-28.221537 367000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] top.
-[treeopen] top.tb_cpu_embedded.
-[sst_width] 233
-[signals_width] 78
-[sst_expanded] 1
-[sst_vpaned_height] 144
-@28
-top.tb_cpu_embedded.uut.clk
-@29
-top.tb_cpu_embedded.uut.rst
-[pattern_trace] 1
-[pattern_trace] 0

lib/CPUs/JCpu/ghdl/cpu_itest.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
 
@@ -12,6 +12,7 @@ SRCS += ../src/tb_cpu_itest.vhd
 # Compile
 TARGET := cpu_itest
 ENTITY := tb_cpu
+WAVE_FORMAT := ghw
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/JCpu/ghdl/jcpu_core.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := JCPU_CORE
 

lib/CPUs/JCpu/ghdl/mul8x8.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
 
@@ -11,6 +11,7 @@ SRCS += ../src/tb_cpu_embedded.vhd
 # Compile
 TARGET := mul8x8
 ENTITY := tb_cpu_embedded
+WAVE_FORMAT := ghw
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/JCpu/ghdl/reti_issue.gtkw

@@ -1,24 +1,33 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Sun Mar 21 20:25:04 2021
+[*] Sat Jul  2 11:00:05 2022
 [*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.ghw"
-[dumpfile_mtime] "Sun Mar 21 20:25:01 2021"
+[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.ghw"
+[dumpfile_mtime] "Sat Jul  2 10:56:29 2022"
 [dumpfile_size] 22085
-[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.gtkw"
+[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/reti_issue.gtkw"
 [timestart] 0
-[size] 1000 600
-[pos] -1 -1
-*-28.221537 563000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 1854 1136
+[pos] -51 -51
+*-28.221537 446000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.tb_cpu.
 [sst_width] 233
-[signals_width] 78
+[signals_width] 266
 [sst_expanded] 1
-[sst_vpaned_height] 144
+[sst_vpaned_height] 330
 @28
 top.tb_cpu.uut.clk
-@29
 top.tb_cpu.uut.rst
+top.tb_cpu.uut.cio_sel
+top.tb_cpu.uut.stk_pop
+top.tb_cpu.uut.stk_push
+top.tb_cpu.uut.was_pop2pc
+top.tb_cpu.uut.was_pcld
+@420
+top.tb_cpu.uut.ctrl_iphase
+@22
+#{top.tb_cpu.irom_addr[11:0]} top.tb_cpu.irom_addr[11] top.tb_cpu.irom_addr[10] top.tb_cpu.irom_addr[9] top.tb_cpu.irom_addr[8] top.tb_cpu.irom_addr[7] top.tb_cpu.irom_addr[6] top.tb_cpu.irom_addr[5] top.tb_cpu.irom_addr[4] top.tb_cpu.irom_addr[3] top.tb_cpu.irom_addr[2] top.tb_cpu.irom_addr[1] top.tb_cpu.irom_addr[0]
+#{top.tb_cpu.irom_data[17:0]} top.tb_cpu.irom_data[17] top.tb_cpu.irom_data[16] top.tb_cpu.irom_data[15] top.tb_cpu.irom_data[14] top.tb_cpu.irom_data[13] top.tb_cpu.irom_data[12] top.tb_cpu.irom_data[11] top.tb_cpu.irom_data[10] top.tb_cpu.irom_data[9] top.tb_cpu.irom_data[8] top.tb_cpu.irom_data[7] top.tb_cpu.irom_data[6] top.tb_cpu.irom_data[5] top.tb_cpu.irom_data[4] top.tb_cpu.irom_data[3] top.tb_cpu.irom_data[2] top.tb_cpu.irom_data[1] top.tb_cpu.irom_data[0]
 [pattern_trace] 1
 [pattern_trace] 0

lib/CPUs/JCpu/ghdl/reti_issue.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
 
@@ -12,6 +12,7 @@ SRCS += ../src/tb_cpu_itest.vhd
 # Compile
 TARGET := reti_issue
 ENTITY := tb_cpu
+WAVE_FORMAT := ghw
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/JCpu/ghdl/tb_cpu_embedded.gtkw

@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Mon Sep 12 21:25:14 2022
+[*]
+[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/build/tb_cpu_embedded/tb_cpu_embedded.ghw"
+[dumpfile_mtime] "Mon Sep 12 21:24:27 2022"
+[dumpfile_size] 23396
+[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/tb_cpu_embedded.gtkw"
+[timestart] 0
+[size] 1854 1136
+[pos] -1 -1
+*-28.221537 367000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.tb_cpu_embedded.
+[treeopen] top.tb_cpu_embedded.uut.
+[sst_width] 233
+[signals_width] 242
+[sst_expanded] 1
+[sst_vpaned_height] 330
+@28
+top.tb_cpu_embedded.uut.rst
+top.tb_cpu_embedded.uut.clk
+@22
+#{top.tb_cpu_embedded.uut.irom_data[17:0]} top.tb_cpu_embedded.uut.irom_data[17] top.tb_cpu_embedded.uut.irom_data[16] top.tb_cpu_embedded.uut.irom_data[15] top.tb_cpu_embedded.uut.irom_data[14] top.tb_cpu_embedded.uut.irom_data[13] top.tb_cpu_embedded.uut.irom_data[12] top.tb_cpu_embedded.uut.irom_data[11] top.tb_cpu_embedded.uut.irom_data[10] top.tb_cpu_embedded.uut.irom_data[9] top.tb_cpu_embedded.uut.irom_data[8] top.tb_cpu_embedded.uut.irom_data[7] top.tb_cpu_embedded.uut.irom_data[6] top.tb_cpu_embedded.uut.irom_data[5] top.tb_cpu_embedded.uut.irom_data[4] top.tb_cpu_embedded.uut.irom_data[3] top.tb_cpu_embedded.uut.irom_data[2] top.tb_cpu_embedded.uut.irom_data[1] top.tb_cpu_embedded.uut.irom_data[0]
+#{top.tb_cpu_embedded.uut.irom_addr[11:0]} top.tb_cpu_embedded.uut.irom_addr[11] top.tb_cpu_embedded.uut.irom_addr[10] top.tb_cpu_embedded.uut.irom_addr[9] top.tb_cpu_embedded.uut.irom_addr[8] top.tb_cpu_embedded.uut.irom_addr[7] top.tb_cpu_embedded.uut.irom_addr[6] top.tb_cpu_embedded.uut.irom_addr[5] top.tb_cpu_embedded.uut.irom_addr[4] top.tb_cpu_embedded.uut.irom_addr[3] top.tb_cpu_embedded.uut.irom_addr[2] top.tb_cpu_embedded.uut.irom_addr[1] top.tb_cpu_embedded.uut.irom_addr[0]
+#{top.tb_cpu_embedded.uut.xmem_addr[7:0]} top.tb_cpu_embedded.uut.xmem_addr[7] top.tb_cpu_embedded.uut.xmem_addr[6] top.tb_cpu_embedded.uut.xmem_addr[5] top.tb_cpu_embedded.uut.xmem_addr[4] top.tb_cpu_embedded.uut.xmem_addr[3] top.tb_cpu_embedded.uut.xmem_addr[2] top.tb_cpu_embedded.uut.xmem_addr[1] top.tb_cpu_embedded.uut.xmem_addr[0]
+#{top.tb_cpu_embedded.uut.xmem_dout[7:0]} top.tb_cpu_embedded.uut.xmem_dout[7] top.tb_cpu_embedded.uut.xmem_dout[6] top.tb_cpu_embedded.uut.xmem_dout[5] top.tb_cpu_embedded.uut.xmem_dout[4] top.tb_cpu_embedded.uut.xmem_dout[3] top.tb_cpu_embedded.uut.xmem_dout[2] top.tb_cpu_embedded.uut.xmem_dout[1] top.tb_cpu_embedded.uut.xmem_dout[0]
+#{top.tb_cpu_embedded.uut.xmem_din[7:0]} top.tb_cpu_embedded.uut.xmem_din[7] top.tb_cpu_embedded.uut.xmem_din[6] top.tb_cpu_embedded.uut.xmem_din[5] top.tb_cpu_embedded.uut.xmem_din[4] top.tb_cpu_embedded.uut.xmem_din[3] top.tb_cpu_embedded.uut.xmem_din[2] top.tb_cpu_embedded.uut.xmem_din[1] top.tb_cpu_embedded.uut.xmem_din[0]
+@28
+top.tb_cpu_embedded.uut.xmem_re
+top.tb_cpu_embedded.uut.xmem_we
+top.tb_cpu_embedded.uut.io_sel
+top.tb_cpu_embedded.uut.int_ack
+@29
+top.tb_cpu_embedded.uut.int_in
+[pattern_trace] 1
+[pattern_trace] 0

lib/CPUs/JCpu/ghdl/tb_cpu_embedded.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
 
@@ -9,8 +9,9 @@ SRCS += ../src/cpu_embedded.vhd
 SRCS += ../src/tb_cpu_embedded.vhd
 
 # Compile
-TARGET := cpu_embedded
+TARGET := tb_cpu_embedded
 ENTITY := tb_cpu_embedded
+WAVE_FORMAT := ghw
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/JCpu/ghdl/tb_cpu_embedded.wopt.templ

@@ -0,0 +1,199 @@
+$ version 1.1
+
+# Signals in packages :
+
+# Signals in entities :
+/tb_cpu_embedded/rst
+/tb_cpu_embedded/clk
+/tb_cpu_embedded/ce
+/tb_cpu_embedded/int_in
+/tb_cpu_embedded/int_ack
+/tb_cpu_embedded/xmem_din
+/tb_cpu_embedded/xmem_dout
+/tb_cpu_embedded/xmem_addr
+/tb_cpu_embedded/xmem_we
+/tb_cpu_embedded/xmem_re
+/tb_cpu_embedded/io_sel
+/tb_cpu_embedded/sram
+/tb_cpu_embedded/uut/rst
+/tb_cpu_embedded/uut/clk
+/tb_cpu_embedded/uut/ce
+/tb_cpu_embedded/uut/int_in
+/tb_cpu_embedded/uut/int_ack
+/tb_cpu_embedded/uut/xmem_we
+/tb_cpu_embedded/uut/xmem_re
+/tb_cpu_embedded/uut/xmem_din
+/tb_cpu_embedded/uut/xmem_dout
+/tb_cpu_embedded/uut/xmem_addr
+/tb_cpu_embedded/uut/io_sel
+/tb_cpu_embedded/uut/irom_data
+/tb_cpu_embedded/uut/irom_addr
+/tb_cpu_embedded/uut/inst_cpu/rst
+/tb_cpu_embedded/uut/inst_cpu/clk
+/tb_cpu_embedded/uut/inst_cpu/ce
+/tb_cpu_embedded/uut/inst_cpu/int_in
+/tb_cpu_embedded/uut/inst_cpu/int_ack
+/tb_cpu_embedded/uut/inst_cpu/xmem_we
+/tb_cpu_embedded/uut/inst_cpu/xmem_re
+/tb_cpu_embedded/uut/inst_cpu/instr_din
+/tb_cpu_embedded/uut/inst_cpu/instr_addr
+/tb_cpu_embedded/uut/inst_cpu/xmem_din
+/tb_cpu_embedded/uut/inst_cpu/xmem_dout
+/tb_cpu_embedded/uut/inst_cpu/xmem_addr
+/tb_cpu_embedded/uut/inst_cpu/io_sel
+/tb_cpu_embedded/uut/inst_cpu/cpu_status
+/tb_cpu_embedded/uut/inst_cpu/status_reg
+/tb_cpu_embedded/uut/inst_cpu/ctrl
+/tb_cpu_embedded/uut/inst_cpu/stk_out
+/tb_cpu_embedded/uut/inst_cpu/stk_in
+/tb_cpu_embedded/uut/inst_cpu/stk_reg
+/tb_cpu_embedded/uut/inst_cpu/pc_in
+/tb_cpu_embedded/uut/inst_cpu/pc_out
+/tb_cpu_embedded/uut/inst_cpu/pc_next
+/tb_cpu_embedded/uut/inst_cpu/idata
+/tb_cpu_embedded/uut/inst_cpu/int_pc_addr
+/tb_cpu_embedded/uut/inst_cpu/iphase
+/tb_cpu_embedded/uut/inst_cpu/const_data
+/tb_cpu_embedded/uut/inst_cpu/reg_a_dout
+/tb_cpu_embedded/uut/inst_cpu/reg_b_dout
+/tb_cpu_embedded/uut/inst_cpu/reg_din
+/tb_cpu_embedded/uut/inst_cpu/alu_op1
+/tb_cpu_embedded/uut/inst_cpu/alu_op2
+/tb_cpu_embedded/uut/inst_cpu/alu_result
+/tb_cpu_embedded/uut/inst_cpu/alu_status
+/tb_cpu_embedded/uut/inst_cpu/pc_inc
+/tb_cpu_embedded/uut/inst_cpu/pc_load
+/tb_cpu_embedded/uut/inst_cpu/cpu_active
+/tb_cpu_embedded/uut/inst_cpu/stk_we
+/tb_cpu_embedded/uut/inst_cpu/cmem_we
+/tb_cpu_embedded/uut/inst_cpu/creg_we
+/tb_cpu_embedded/uut/inst_cpu/ctrl_inst
+/tb_cpu_embedded/uut/inst_cpu/ctrl_iphase
+/tb_cpu_embedded/uut/inst_cpu/was_pcld
+/tb_cpu_embedded/uut/inst_cpu/was_pop2pc
+/tb_cpu_embedded/uut/inst_cpu/int_pc_load
+/tb_cpu_embedded/uut/inst_cpu/int_stk_push
+/tb_cpu_embedded/uut/inst_cpu/int_stk_pop
+/tb_cpu_embedded/uut/inst_cpu/stk_push
+/tb_cpu_embedded/uut/inst_cpu/stk_pop
+/tb_cpu_embedded/uut/inst_cpu/status_save
+/tb_cpu_embedded/uut/inst_cpu/status_restore
+/tb_cpu_embedded/uut/inst_cpu/creg_dout
+/tb_cpu_embedded/uut/inst_cpu/cmem_din
+/tb_cpu_embedded/uut/inst_cpu/cmem_dout
+/tb_cpu_embedded/uut/inst_cpu/stk_addr
+/tb_cpu_embedded/uut/inst_cpu/cmem_addr
+/tb_cpu_embedded/uut/inst_cpu/stk_ptr
+/tb_cpu_embedded/uut/inst_cpu/creg_ctrl_out
+/tb_cpu_embedded/uut/inst_cpu/creg_ctrl_in
+/tb_cpu_embedded/uut/inst_cpu/xio_sel
+/tb_cpu_embedded/uut/inst_cpu/cio_sel
+/tb_cpu_embedded/uut/inst_cpu/mem_data
+/tb_cpu_embedded/uut/inst_cpu/mem_addr
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/rst
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/push
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/pop
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/ptr_out
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/din
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/dout
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/mem_we
+/tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/ptr
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/rst
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/inc
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/load
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_in
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_out
+/tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_next
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/inst_in
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/iphase_in
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/status_in
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ctrl_out
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/idout
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ddout
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/opcode
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ctrl_lines
+/tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/rst
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/ctrl_in
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_in
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_exit
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/iphase_in
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_addr_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_ack_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stat_save_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stat_rest_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_load_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_push_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_pop_out
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_state
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_state_next
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_load
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_ack
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_push
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_pop
+/tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_request
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/we_a
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/ptr_a
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/ptr_b
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/din_a
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/dout_a
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/dout_b
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/addr_a
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/addr_b
+/tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/clka
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/clkb
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/en_a
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/en_b
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/we_a
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/we_b
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/addr_a
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/addr_b
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/din_a
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/din_b
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/dout_a
+/tb_cpu_embedded/uut/inst_cpu/inst_chipram/dout_b
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/rst
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/we
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/addr
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/din
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/dout
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/ctrl_in
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/ctrl_out
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_bank_sel
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_int_ctrl
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_stk_high
+/tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_cmem_high
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/rst
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/clk
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/op_en
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/cy_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/op1_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/op2_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/opsel
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/res_out
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_load
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_out
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_cy
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_cy
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_cy_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_cy_in
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/left_shift
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/add_subn
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/result
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_res
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/lf_res
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_res
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/res_reg
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/status
+/tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_reg
+/tb_cpu_embedded/uut/inst_irom/clk
+/tb_cpu_embedded/uut/inst_irom/ce
+/tb_cpu_embedded/uut/inst_irom/addr
+/tb_cpu_embedded/uut/inst_irom/dout

lib/CPUs/JCpu/ghdl/tb_cpu_embedded_with_uart.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
 include jcpu_core.inc
@@ -16,5 +16,5 @@ TARGET := tb_cpu_embedded_with_uart
 ENTITY := tb_cpu_embedded_with_uart
 RUN_TIME := 100us
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/MIPS/doc/Mips Basic Pipe.drawio

@@ -0,0 +1 @@
+<mxfile host="app.diagrams.net" modified="2022-09-11T17:00:05.394Z" agent="5.0 (X11)" etag="ULt_GwP94m2c2vBAbY-Z" version="20.3.0" type="device"><diagram id="XI_-d3d4CUWLWsZJCx82" name="Seite-1">7VxNj9owEP01HLsidkLCcZfttmpVqRKHtqcqIl6w1sTImAL99XWITWIbmizN1ya9IDzEjjPvjT0znjCCs/XhAws3qy80QmQExtFhBB9HAEyhJz4TwTEVeME0FSwZjlKRkwnm+DeSwrGU7nCEttqFnFLC8UYXLmgcowXXZCFjdK9f9kyJftdNuESWYL4IiS39hiO+SqUB8DP5R4SXK3VnZyKfbx2qi+WTbFdhRPc5EXw/gjNGKU+/rQ8zRBLdKb2k/Z6u/HqeGEMxL9PhZffpeYp/ftzsHZ89LcE8+EzeyVF+hWQnH1hOlh+VBhjdxRFKBhmP4MN+hTmab8JF8uteQC5kK74mouWIr3I4xDg6XJ2nc356wRpE14izo7hEdXCkBiVjHKXAfaZ/V4pWedVPpDCUkC/PQ2daEV+kYl6hJLd7SoKdU5JfrCQxijBb0XgQtrBJhAtCd1EjCgOmwlyvlMJgXfoKSugrju6TJeykqHC7xQtdLTrphCLY8XvSuPMcXwl+nASO6yrB4yF//eMx3/qKGBZPh5gUpjNCkbVEGloXa3LIlogX0cNGJ6d974L2lYwhEnL8S5/GJUjkHb5SLCaYgQ918AMD1C3dsQWSnfJLqDEOnOjjWOxI1WANdCLI+alv58y0Ps7ofAFeEV0OmKdcC3xPttOuqpV1TBr5frezLMWpeBEqZKPbKht9g0XurXQExpo2bZaOykerZQ1zJjolvbKUdDQ6ggI+/tuyV0jIt7E8TlydR35VhDQHqpuQtjs754mDD8ZiIuMZZ8QiqHApuE7JLWf0Bc0ooQkhYhonHsszJsQQhQQv44TXghUJdx4SBwWL0OFe/rDGUZTc5qJ7oxO/Cg9nrCvfsz3CSZMOjgNKgDHGcX8RcTzDHGDbkMAh20fn0CgRV+a2T6nVq3tn2V2rrV3GjOtv9sIdw5sHZkxb9y7jDQu3InWXxs0rIEDduE0GhZuZIro96m3b3sqklnqEW1X2Btu2txpTXHps6BfFhmUxLxGptcqNqjIHjhErnOfXFDXsTJZwRE/9xhZHeuOBmvaoNqS2HFB1ZvCGDPTt5+zMXdkcqGbLAxdTJKd+jgV+byyve6ZnJ0f+ZnpFPs1WsIari6kYVMmeMNEP0bprYmacAUFV8WHDfg+wsyxDxxbC4C6oBl17qMbxHVbexq/ILL1pwUB1w2anbWbkpb97nrnlqcPB1ra8MumXFitE3K5ViIDX5T06VSJSGEYrNnRmmXMrqhHxWq4RAY1lXbpQJFJ4AN89nlUVSXrmetVwWlad9Q+k+uPtrWhm/tciSGmmtVzWoVbQC8fWQik9P7Z2O1bWAa/X2GRg9Lqsw7KrtgsJoJ1MGpB9dA6NEumfpl8XsHyF1l8XgMNKopgA3B5etHwYD4dV/FKo7tK4tXwYD6stfulDUtqrLiltD9U4vjUmi3p2lmua4u1x0bTdCBzaqR5ORVs5fzYDeuP1WRhe8PqCRr2+yrMhXTcjvyIrst73bdiKlN+bQ+6Z0XXOjtRbPH00JDO1c8GOpk3akVvijfT/+1gasNWVSW66Jsm9mL849evxFmYmLmqsSRLN7H8mUtSyP+uA7/8A</diagram></mxfile>

lib/CPUs/MIPS/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/CPUs/MIPS/ghdl/mips_core.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
 

lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw

@@ -1,30 +1,136 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Mar 23 20:38:28 2021
+[*] Tue Sep 13 09:25:38 2022
 [*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/MIPS/ghdl/build/tb_mips_top/tb_mips_top.vcd"
-[dumpfile_mtime] "Tue Mar 23 20:38:01 2021"
-[dumpfile_size] 395823834
-[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/MIPS/ghdl/build/tb_mips_top/tb_mips_top.gtkw"
-[timestart] 0
-[size] 1856 1136
-[pos] -51 -51
-*-37.625370 355000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] tb_mips_top.
-[treeopen] tb_mips_top.inst_uart.
-[sst_width] 233
-[signals_width] 288
+[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/build/tb_mips_top/tb_mips_top.ghw"
+[dumpfile_mtime] "Tue Sep 13 05:37:30 2022"
+[dumpfile_size] 284165098
+[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw"
+[timestart] 1624938400000
+[size] 1920 1163
+[pos] -1987 -28
+*-24.584558 1625004800000 1624975000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.tb_mips_top.
+[treeopen] top.tb_mips_top.uut.
+[treeopen] top.tb_mips_top.uut.inst_biu.inst_icache.
+[treeopen] top.tb_mips_top.uut.inst_cop.
+[treeopen] top.tb_mips_top.uut.inst_cop.ctrl_in.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.c0_ctrl_in.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.c0_ctrl_out.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.ex_stage.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.id_stage.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.mem_stage.
+[treeopen] top.tb_mips_top.uut.inst_pipeline.wb_stage.
+[sst_width] 358
+[signals_width] 296
 [sst_expanded] 1
-[sst_vpaned_height] 330
+[sst_vpaned_height] 667
+@200
+-MIPS_R13
 @28
-tb_mips_top.clk
-tb_mips_top.rst
+top.tb_mips_top.uut.cpu_clk
+top.tb_mips_top.uut.clk_i
+top.tb_mips_top.uut.stb_o
 @22
-tb_mips_top.flash_a[16:0]
-tb_mips_top.flash_d[31:0]
-tb_mips_top.gpi_0[31:0]
-tb_mips_top.gpo_0[31:0]
-@23
-tb_mips_top.inst_uart.reg_uart_tx[7:0]
+#{top.tb_mips_top.uut.addr_o[31:0]} top.tb_mips_top.uut.addr_o[31] top.tb_mips_top.uut.addr_o[30] top.tb_mips_top.uut.addr_o[29] top.tb_mips_top.uut.addr_o[28] top.tb_mips_top.uut.addr_o[27] top.tb_mips_top.uut.addr_o[26] top.tb_mips_top.uut.addr_o[25] top.tb_mips_top.uut.addr_o[24] top.tb_mips_top.uut.addr_o[23] top.tb_mips_top.uut.addr_o[22] top.tb_mips_top.uut.addr_o[21] top.tb_mips_top.uut.addr_o[20] top.tb_mips_top.uut.addr_o[19] top.tb_mips_top.uut.addr_o[18] top.tb_mips_top.uut.addr_o[17] top.tb_mips_top.uut.addr_o[16] top.tb_mips_top.uut.addr_o[15] top.tb_mips_top.uut.addr_o[14] top.tb_mips_top.uut.addr_o[13] top.tb_mips_top.uut.addr_o[12] top.tb_mips_top.uut.addr_o[11] top.tb_mips_top.uut.addr_o[10] top.tb_mips_top.uut.addr_o[9] top.tb_mips_top.uut.addr_o[8] top.tb_mips_top.uut.addr_o[7] top.tb_mips_top.uut.addr_o[6] top.tb_mips_top.uut.addr_o[5] top.tb_mips_top.uut.addr_o[4] top.tb_mips_top.uut.addr_o[3] top.tb_mips_top.uut.addr_o[2] top.tb_mips_top.uut.addr_o[1] top.tb_mips_top.uut.addr_o[0]
+#{top.tb_mips_top.uut.dat_o[31:0]} top.tb_mips_top.uut.dat_o[31] top.tb_mips_top.uut.dat_o[30] top.tb_mips_top.uut.dat_o[29] top.tb_mips_top.uut.dat_o[28] top.tb_mips_top.uut.dat_o[27] top.tb_mips_top.uut.dat_o[26] top.tb_mips_top.uut.dat_o[25] top.tb_mips_top.uut.dat_o[24] top.tb_mips_top.uut.dat_o[23] top.tb_mips_top.uut.dat_o[22] top.tb_mips_top.uut.dat_o[21] top.tb_mips_top.uut.dat_o[20] top.tb_mips_top.uut.dat_o[19] top.tb_mips_top.uut.dat_o[18] top.tb_mips_top.uut.dat_o[17] top.tb_mips_top.uut.dat_o[16] top.tb_mips_top.uut.dat_o[15] top.tb_mips_top.uut.dat_o[14] top.tb_mips_top.uut.dat_o[13] top.tb_mips_top.uut.dat_o[12] top.tb_mips_top.uut.dat_o[11] top.tb_mips_top.uut.dat_o[10] top.tb_mips_top.uut.dat_o[9] top.tb_mips_top.uut.dat_o[8] top.tb_mips_top.uut.dat_o[7] top.tb_mips_top.uut.dat_o[6] top.tb_mips_top.uut.dat_o[5] top.tb_mips_top.uut.dat_o[4] top.tb_mips_top.uut.dat_o[3] top.tb_mips_top.uut.dat_o[2] top.tb_mips_top.uut.dat_o[1] top.tb_mips_top.uut.dat_o[0]
+#{top.tb_mips_top.uut.dat_i[31:0]} top.tb_mips_top.uut.dat_i[31] top.tb_mips_top.uut.dat_i[30] top.tb_mips_top.uut.dat_i[29] top.tb_mips_top.uut.dat_i[28] top.tb_mips_top.uut.dat_i[27] top.tb_mips_top.uut.dat_i[26] top.tb_mips_top.uut.dat_i[25] top.tb_mips_top.uut.dat_i[24] top.tb_mips_top.uut.dat_i[23] top.tb_mips_top.uut.dat_i[22] top.tb_mips_top.uut.dat_i[21] top.tb_mips_top.uut.dat_i[20] top.tb_mips_top.uut.dat_i[19] top.tb_mips_top.uut.dat_i[18] top.tb_mips_top.uut.dat_i[17] top.tb_mips_top.uut.dat_i[16] top.tb_mips_top.uut.dat_i[15] top.tb_mips_top.uut.dat_i[14] top.tb_mips_top.uut.dat_i[13] top.tb_mips_top.uut.dat_i[12] top.tb_mips_top.uut.dat_i[11] top.tb_mips_top.uut.dat_i[10] top.tb_mips_top.uut.dat_i[9] top.tb_mips_top.uut.dat_i[8] top.tb_mips_top.uut.dat_i[7] top.tb_mips_top.uut.dat_i[6] top.tb_mips_top.uut.dat_i[5] top.tb_mips_top.uut.dat_i[4] top.tb_mips_top.uut.dat_i[3] top.tb_mips_top.uut.dat_i[2] top.tb_mips_top.uut.dat_i[1] top.tb_mips_top.uut.dat_i[0]
+@200
+-PC
+@28
+top.tb_mips_top.uut.inst_pipeline.pc.branch_take
+@22
+#{top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[31] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[30] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[29] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[28] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[27] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[26] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[25] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[24] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[23] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[22] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[21] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[20] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[19] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[18] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[17] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[16] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[15] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[14] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[13] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[12] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[11] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[10] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[9] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[8] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[7] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[6] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[5] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[4] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[3] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[2] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[1] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[0]
+#{top.tb_mips_top.uut.inst_pipeline.pc.nxt[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.nxt[31] top.tb_mips_top.uut.inst_pipeline.pc.nxt[30] top.tb_mips_top.uut.inst_pipeline.pc.nxt[29] top.tb_mips_top.uut.inst_pipeline.pc.nxt[28] top.tb_mips_top.uut.inst_pipeline.pc.nxt[27] top.tb_mips_top.uut.inst_pipeline.pc.nxt[26] top.tb_mips_top.uut.inst_pipeline.pc.nxt[25] top.tb_mips_top.uut.inst_pipeline.pc.nxt[24] top.tb_mips_top.uut.inst_pipeline.pc.nxt[23] top.tb_mips_top.uut.inst_pipeline.pc.nxt[22] top.tb_mips_top.uut.inst_pipeline.pc.nxt[21] top.tb_mips_top.uut.inst_pipeline.pc.nxt[20] top.tb_mips_top.uut.inst_pipeline.pc.nxt[19] top.tb_mips_top.uut.inst_pipeline.pc.nxt[18] top.tb_mips_top.uut.inst_pipeline.pc.nxt[17] top.tb_mips_top.uut.inst_pipeline.pc.nxt[16] top.tb_mips_top.uut.inst_pipeline.pc.nxt[15] top.tb_mips_top.uut.inst_pipeline.pc.nxt[14] top.tb_mips_top.uut.inst_pipeline.pc.nxt[13] top.tb_mips_top.uut.inst_pipeline.pc.nxt[12] top.tb_mips_top.uut.inst_pipeline.pc.nxt[11] top.tb_mips_top.uut.inst_pipeline.pc.nxt[10] top.tb_mips_top.uut.inst_pipeline.pc.nxt[9] top.tb_mips_top.uut.inst_pipeline.pc.nxt[8] top.tb_mips_top.uut.inst_pipeline.pc.nxt[7] top.tb_mips_top.uut.inst_pipeline.pc.nxt[6] top.tb_mips_top.uut.inst_pipeline.pc.nxt[5] top.tb_mips_top.uut.inst_pipeline.pc.nxt[4] top.tb_mips_top.uut.inst_pipeline.pc.nxt[3] top.tb_mips_top.uut.inst_pipeline.pc.nxt[2] top.tb_mips_top.uut.inst_pipeline.pc.nxt[1] top.tb_mips_top.uut.inst_pipeline.pc.nxt[0]
+#{top.tb_mips_top.uut.inst_pipeline.pc.last[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.last[31] top.tb_mips_top.uut.inst_pipeline.pc.last[30] top.tb_mips_top.uut.inst_pipeline.pc.last[29] top.tb_mips_top.uut.inst_pipeline.pc.last[28] top.tb_mips_top.uut.inst_pipeline.pc.last[27] top.tb_mips_top.uut.inst_pipeline.pc.last[26] top.tb_mips_top.uut.inst_pipeline.pc.last[25] top.tb_mips_top.uut.inst_pipeline.pc.last[24] top.tb_mips_top.uut.inst_pipeline.pc.last[23] top.tb_mips_top.uut.inst_pipeline.pc.last[22] top.tb_mips_top.uut.inst_pipeline.pc.last[21] top.tb_mips_top.uut.inst_pipeline.pc.last[20] top.tb_mips_top.uut.inst_pipeline.pc.last[19] top.tb_mips_top.uut.inst_pipeline.pc.last[18] top.tb_mips_top.uut.inst_pipeline.pc.last[17] top.tb_mips_top.uut.inst_pipeline.pc.last[16] top.tb_mips_top.uut.inst_pipeline.pc.last[15] top.tb_mips_top.uut.inst_pipeline.pc.last[14] top.tb_mips_top.uut.inst_pipeline.pc.last[13] top.tb_mips_top.uut.inst_pipeline.pc.last[12] top.tb_mips_top.uut.inst_pipeline.pc.last[11] top.tb_mips_top.uut.inst_pipeline.pc.last[10] top.tb_mips_top.uut.inst_pipeline.pc.last[9] top.tb_mips_top.uut.inst_pipeline.pc.last[8] top.tb_mips_top.uut.inst_pipeline.pc.last[7] top.tb_mips_top.uut.inst_pipeline.pc.last[6] top.tb_mips_top.uut.inst_pipeline.pc.last[5] top.tb_mips_top.uut.inst_pipeline.pc.last[4] top.tb_mips_top.uut.inst_pipeline.pc.last[3] top.tb_mips_top.uut.inst_pipeline.pc.last[2] top.tb_mips_top.uut.inst_pipeline.pc.last[1] top.tb_mips_top.uut.inst_pipeline.pc.last[0]
+#{top.tb_mips_top.uut.inst_pipeline.pc.curr[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.curr[31] top.tb_mips_top.uut.inst_pipeline.pc.curr[30] top.tb_mips_top.uut.inst_pipeline.pc.curr[29] top.tb_mips_top.uut.inst_pipeline.pc.curr[28] top.tb_mips_top.uut.inst_pipeline.pc.curr[27] top.tb_mips_top.uut.inst_pipeline.pc.curr[26] top.tb_mips_top.uut.inst_pipeline.pc.curr[25] top.tb_mips_top.uut.inst_pipeline.pc.curr[24] top.tb_mips_top.uut.inst_pipeline.pc.curr[23] top.tb_mips_top.uut.inst_pipeline.pc.curr[22] top.tb_mips_top.uut.inst_pipeline.pc.curr[21] top.tb_mips_top.uut.inst_pipeline.pc.curr[20] top.tb_mips_top.uut.inst_pipeline.pc.curr[19] top.tb_mips_top.uut.inst_pipeline.pc.curr[18] top.tb_mips_top.uut.inst_pipeline.pc.curr[17] top.tb_mips_top.uut.inst_pipeline.pc.curr[16] top.tb_mips_top.uut.inst_pipeline.pc.curr[15] top.tb_mips_top.uut.inst_pipeline.pc.curr[14] top.tb_mips_top.uut.inst_pipeline.pc.curr[13] top.tb_mips_top.uut.inst_pipeline.pc.curr[12] top.tb_mips_top.uut.inst_pipeline.pc.curr[11] top.tb_mips_top.uut.inst_pipeline.pc.curr[10] top.tb_mips_top.uut.inst_pipeline.pc.curr[9] top.tb_mips_top.uut.inst_pipeline.pc.curr[8] top.tb_mips_top.uut.inst_pipeline.pc.curr[7] top.tb_mips_top.uut.inst_pipeline.pc.curr[6] top.tb_mips_top.uut.inst_pipeline.pc.curr[5] top.tb_mips_top.uut.inst_pipeline.pc.curr[4] top.tb_mips_top.uut.inst_pipeline.pc.curr[3] top.tb_mips_top.uut.inst_pipeline.pc.curr[2] top.tb_mips_top.uut.inst_pipeline.pc.curr[1] top.tb_mips_top.uut.inst_pipeline.pc.curr[0]
+@200
+-REG
+@22
+#{top.tb_mips_top.uut.inst_pipeline.reg_a[31:0]} top.tb_mips_top.uut.inst_pipeline.reg_a[31] top.tb_mips_top.uut.inst_pipeline.reg_a[30] top.tb_mips_top.uut.inst_pipeline.reg_a[29] top.tb_mips_top.uut.inst_pipeline.reg_a[28] top.tb_mips_top.uut.inst_pipeline.reg_a[27] top.tb_mips_top.uut.inst_pipeline.reg_a[26] top.tb_mips_top.uut.inst_pipeline.reg_a[25] top.tb_mips_top.uut.inst_pipeline.reg_a[24] top.tb_mips_top.uut.inst_pipeline.reg_a[23] top.tb_mips_top.uut.inst_pipeline.reg_a[22] top.tb_mips_top.uut.inst_pipeline.reg_a[21] top.tb_mips_top.uut.inst_pipeline.reg_a[20] top.tb_mips_top.uut.inst_pipeline.reg_a[19] top.tb_mips_top.uut.inst_pipeline.reg_a[18] top.tb_mips_top.uut.inst_pipeline.reg_a[17] top.tb_mips_top.uut.inst_pipeline.reg_a[16] top.tb_mips_top.uut.inst_pipeline.reg_a[15] top.tb_mips_top.uut.inst_pipeline.reg_a[14] top.tb_mips_top.uut.inst_pipeline.reg_a[13] top.tb_mips_top.uut.inst_pipeline.reg_a[12] top.tb_mips_top.uut.inst_pipeline.reg_a[11] top.tb_mips_top.uut.inst_pipeline.reg_a[10] top.tb_mips_top.uut.inst_pipeline.reg_a[9] top.tb_mips_top.uut.inst_pipeline.reg_a[8] top.tb_mips_top.uut.inst_pipeline.reg_a[7] top.tb_mips_top.uut.inst_pipeline.reg_a[6] top.tb_mips_top.uut.inst_pipeline.reg_a[5] top.tb_mips_top.uut.inst_pipeline.reg_a[4] top.tb_mips_top.uut.inst_pipeline.reg_a[3] top.tb_mips_top.uut.inst_pipeline.reg_a[2] top.tb_mips_top.uut.inst_pipeline.reg_a[1] top.tb_mips_top.uut.inst_pipeline.reg_a[0]
+#{top.tb_mips_top.uut.inst_pipeline.reg_b[31:0]} top.tb_mips_top.uut.inst_pipeline.reg_b[31] top.tb_mips_top.uut.inst_pipeline.reg_b[30] top.tb_mips_top.uut.inst_pipeline.reg_b[29] top.tb_mips_top.uut.inst_pipeline.reg_b[28] top.tb_mips_top.uut.inst_pipeline.reg_b[27] top.tb_mips_top.uut.inst_pipeline.reg_b[26] top.tb_mips_top.uut.inst_pipeline.reg_b[25] top.tb_mips_top.uut.inst_pipeline.reg_b[24] top.tb_mips_top.uut.inst_pipeline.reg_b[23] top.tb_mips_top.uut.inst_pipeline.reg_b[22] top.tb_mips_top.uut.inst_pipeline.reg_b[21] top.tb_mips_top.uut.inst_pipeline.reg_b[20] top.tb_mips_top.uut.inst_pipeline.reg_b[19] top.tb_mips_top.uut.inst_pipeline.reg_b[18] top.tb_mips_top.uut.inst_pipeline.reg_b[17] top.tb_mips_top.uut.inst_pipeline.reg_b[16] top.tb_mips_top.uut.inst_pipeline.reg_b[15] top.tb_mips_top.uut.inst_pipeline.reg_b[14] top.tb_mips_top.uut.inst_pipeline.reg_b[13] top.tb_mips_top.uut.inst_pipeline.reg_b[12] top.tb_mips_top.uut.inst_pipeline.reg_b[11] top.tb_mips_top.uut.inst_pipeline.reg_b[10] top.tb_mips_top.uut.inst_pipeline.reg_b[9] top.tb_mips_top.uut.inst_pipeline.reg_b[8] top.tb_mips_top.uut.inst_pipeline.reg_b[7] top.tb_mips_top.uut.inst_pipeline.reg_b[6] top.tb_mips_top.uut.inst_pipeline.reg_b[5] top.tb_mips_top.uut.inst_pipeline.reg_b[4] top.tb_mips_top.uut.inst_pipeline.reg_b[3] top.tb_mips_top.uut.inst_pipeline.reg_b[2] top.tb_mips_top.uut.inst_pipeline.reg_b[1] top.tb_mips_top.uut.inst_pipeline.reg_b[0]
+@200
+-ID
+@22
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[0]
+@28
+top.tb_mips_top.uut.inst_pipeline.id_stage.nop
+@420
+top.tb_mips_top.uut.inst_pipeline.id_stage.op
+@28
+top.tb_mips_top.uut.inst_pipeline.id_stage.exc
+top.tb_mips_top.uut.inst_pipeline.sdu.dmem_dep
+top.tb_mips_top.uut.inst_pipeline.sdu.imem_dep
+@22
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.ir[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.ir[31] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[30] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[29] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[28] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[27] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[26] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[25] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[24] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[23] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[22] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[21] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[20] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[19] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[18] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[17] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[16] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[15] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[14] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[13] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[12] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[11] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[10] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[9] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[8] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[7] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[6] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[5] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[4] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[3] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[2] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[1] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[0]
+@28
+top.tb_mips_top.uut.inst_pipeline.id_stage.reg_write
+@22
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[31] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[30] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[29] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[28] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[27] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[26] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[25] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[24] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[23] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[22] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[21] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[20] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[19] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[18] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[17] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[16] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[15] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[14] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[13] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[12] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[11] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[10] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[9] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[8] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[7] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[6] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[5] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[4] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[3] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[2] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[1] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[0]
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[0]
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[4:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[0]
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[31] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[30] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[29] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[28] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[27] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[26] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[25] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[24] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[23] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[22] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[21] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[20] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[19] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[18] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[17] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[16] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[15] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[14] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[13] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[12] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[11] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[10] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[9] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[8] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[7] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[6] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[5] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[0]
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[4:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[0]
+#{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[31] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[30] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[29] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[28] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[27] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[26] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[25] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[24] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[23] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[22] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[21] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[20] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[19] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[18] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[17] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[16] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[15] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[14] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[13] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[12] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[11] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[10] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[9] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[8] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[7] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[6] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[5] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[0]
+@200
+-EX
+@22
+#{top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[0]
+@28
+top.tb_mips_top.uut.inst_pipeline.ex_stage.nop
+@420
+top.tb_mips_top.uut.inst_pipeline.ex_stage.op
+@28
+top.tb_mips_top.uut.inst_pipeline.ex_stage.exc
+top.tb_mips_top.uut.inst_pipeline.ex_stage.reg_write
+top.tb_mips_top.uut.inst_pipeline.ex_stage.wreg_we
+@200
+-MEM
+@22
+#{top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[0]
+@28
+top.tb_mips_top.uut.inst_pipeline.mem_stage.nop
+@420
+top.tb_mips_top.uut.inst_pipeline.mem_stage.op
+@28
+top.tb_mips_top.uut.inst_pipeline.mem_stage.exc
+top.tb_mips_top.uut.inst_pipeline.mem_stage.events.int
+@200
+-WB
+@28
+top.tb_mips_top.uut.inst_pipeline.wb_stage.nop
+@420
+top.tb_mips_top.uut.inst_pipeline.wb_stage.op
+@28
+top.tb_mips_top.uut.inst_pipeline.wb_stage.exc
+top.tb_mips_top.uut.inst_pipeline.wb_stage.events.int
+top.tb_mips_top.uut.inst_pipeline.wb_stage.bd
+top.tb_mips_top.uut.inst_pipeline.wb_stage.events.int
+@200
+-COP
+@421
+top.tb_mips_top.uut.inst_cop.exc_state
+@22
+#{top.tb_mips_top.uut.inst_cop.epc[31:0]} top.tb_mips_top.uut.inst_cop.epc[31] top.tb_mips_top.uut.inst_cop.epc[30] top.tb_mips_top.uut.inst_cop.epc[29] top.tb_mips_top.uut.inst_cop.epc[28] top.tb_mips_top.uut.inst_cop.epc[27] top.tb_mips_top.uut.inst_cop.epc[26] top.tb_mips_top.uut.inst_cop.epc[25] top.tb_mips_top.uut.inst_cop.epc[24] top.tb_mips_top.uut.inst_cop.epc[23] top.tb_mips_top.uut.inst_cop.epc[22] top.tb_mips_top.uut.inst_cop.epc[21] top.tb_mips_top.uut.inst_cop.epc[20] top.tb_mips_top.uut.inst_cop.epc[19] top.tb_mips_top.uut.inst_cop.epc[18] top.tb_mips_top.uut.inst_cop.epc[17] top.tb_mips_top.uut.inst_cop.epc[16] top.tb_mips_top.uut.inst_cop.epc[15] top.tb_mips_top.uut.inst_cop.epc[14] top.tb_mips_top.uut.inst_cop.epc[13] top.tb_mips_top.uut.inst_cop.epc[12] top.tb_mips_top.uut.inst_cop.epc[11] top.tb_mips_top.uut.inst_cop.epc[10] top.tb_mips_top.uut.inst_cop.epc[9] top.tb_mips_top.uut.inst_cop.epc[8] top.tb_mips_top.uut.inst_cop.epc[7] top.tb_mips_top.uut.inst_cop.epc[6] top.tb_mips_top.uut.inst_cop.epc[5] top.tb_mips_top.uut.inst_cop.epc[4] top.tb_mips_top.uut.inst_cop.epc[3] top.tb_mips_top.uut.inst_cop.epc[2] top.tb_mips_top.uut.inst_cop.epc[1] top.tb_mips_top.uut.inst_cop.epc[0]
+#{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
+#{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[0]
+@200
+-I-Cache
+@420
+top.tb_mips_top.uut.inst_biu.inst_icache.s
+@22
+#{top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[31:0]} top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[31] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[30] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[29] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[28] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[27] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[26] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[25] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[24] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[23] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[22] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[21] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[20] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[19] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[18] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[17] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[16] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[15] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[14] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[13] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[12] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[11] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[10] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[9] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[8] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[7] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[6] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[5] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[4] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[3] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[2] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[1] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[0]
+@28
+top.tb_mips_top.uut.inst_biu.inst_icache.cpu_busy
+top.tb_mips_top.uut.inst_biu.inst_icache.cpu_en
+top.tb_mips_top.uut.inst_biu.inst_icache.tag_match
+top.tb_mips_top.uut.inst_biu.inst_icache.cache_hit
+top.tb_mips_top.uut.inst_biu.inst_icache.cache_busy
+top.tb_mips_top.uut.inst_biu.inst_icache.cache_ack
+top.tb_mips_top.uut.inst_biu.inst_icache.cache_req
+@22
+#{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
+#{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
 [pattern_trace] 1
 [pattern_trace] 0

lib/CPUs/MIPS/ghdl/tb_mips_top.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include mips_core.inc
 
@@ -32,7 +32,8 @@ SRCS += ../src/tb_mips_top.vhd
 # Compile
 TARGET := tb_mips_top
 ENTITY := tb_mips_top
-RUN_TIME ?= 1500us
+RUN_TIME ?= 250us
+WAVE_FORMAT ?= ghw
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/CPUs/MIPS/src/core/mips_types.vhd

@@ -585,6 +585,9 @@ package body mips_types is
 		elsif word2_en = '1' then
 			sign	:= signed and x(15);
 			result := (31 downto 16 => sign) & x(15 downto 0);
+		elsif word4_en = '1' then
+			sign	:= signed and x(7);
+			result := (31 downto 8 => sign) & x(7 downto 0);
 		else
 			sign	:= signed and x(7);
 			result := (31 downto 8 => sign) & x(7 downto 0);

lib/CPUs/MIPS/src/tb_mips_top.vhd

@@ -33,6 +33,11 @@ use work.async_types.all;
 use work.async_defs.all;
 
 ENTITY tb_mips_top IS
+	Generic
+	(
+		app	: string := "apps/hello.elf.flash.bin"
+	);
+	
 END tb_mips_top;
 
 ARCHITECTURE behavior OF tb_mips_top IS 
@@ -113,8 +118,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	signal mem_area : mem_area_t;
 
 	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
-	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
-	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
+	signal sram_memory_content : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
+	signal flash_memory_content : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
 	
 BEGIN
 
@@ -356,16 +361,16 @@ SRAM_READ:
 		if sram_oe_n = '0' then
 			if sram_cs_n = '0' then
 				if sram_be_n(0) = '0' then
-					sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
+					sram_d(7 downto 0) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
 				end if;	
 				if sram_be_n(1) = '0' then
-					sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
+					sram_d(15 downto 8) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
 				end if;	
 				if sram_be_n(2) = '0' then
-					sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
+					sram_d(23 downto 16) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
 				end if;	
 				if sram_be_n(3) = '0' then
-					sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
+					sram_d(31 downto 24) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
 				end if;	
 			end if;				
 		end if;	
@@ -377,16 +382,16 @@ SRAM_WRITE:
 		if rising_edge(sram_wr_n) then
 			if sram_cs_n = '0' then
 				if sram_be_n(0) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
 				end if;		
 				if sram_be_n(1) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
 				end if;				
 				if sram_be_n(2) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
 				end if;				
 				if sram_be_n(3) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
 				end if;				
 			end if;	
 		end if;	
@@ -396,7 +401,7 @@ SRAM_WRITE:
 FLASH_READ:
 	process(rst, flash_cs_n, flash_oe_n, flash_a)
 	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "hello.elf.flash.bin";
+	file load_flash : file_t open read_mode is app;
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);
@@ -407,7 +412,7 @@ FLASH_READ:
 			while not endfile(load_flash) loop
 				read(load_flash, instr);
 				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
+				flash_memory_content(index) <= unsigned(temp);
 				index := index + 1;
 			end loop;
 		else
@@ -416,16 +421,16 @@ FLASH_READ:
 			if flash_oe_n = '0' then
 				if flash_cs_n = '0' then
 					if flash_be_n(0) = '0' then
-						flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
+						flash_d(7 downto 0) <= flash_memory_content(index)(7 downto 0) after tpd;
 					end if;	
 					if flash_be_n(1) = '0' then
-						flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
+						flash_d(15 downto 8) <= flash_memory_content(index)(15 downto 8) after tpd;
 					end if;	
 					if flash_be_n(2) = '0' then
-						flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
+						flash_d(23 downto 16) <= flash_memory_content(index)(23 downto 16) after tpd;
 					end if;	
 					if flash_be_n(3) = '0' then
-						flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
+						flash_d(31 downto 24) <= flash_memory_content(index)(31 downto 24) after tpd;
 					end if;	
 				end if;				
 			end if;	

lib/CPUs/MIPS/syn/ise101/Makefile

@@ -1,7 +1,9 @@
-PRJ := mips_top
+include $(VHDL_HOME)/defs.mk
 PRJDIR := ./project
+
+PRJ := mips_top
 PREQ := $(PRJDIR)/$(PRJ).prj $(PRJDIR)/$(PRJ).xst $(PRJDIR)/$(PRJ).lso
-DIRS := ./xst/tmp
+DEVICE := "xc4vsx35-ff668-10"
 
-include $(VHDL_HOME)/make/ise.mk
+include $(VHDL_MAKE_HOME)/ise.mk
 

lib/CPUs/MIPS/syn/ise101/project/mips_top.xst

@@ -1,7 +1,7 @@
-set -xsthdpdir "./xst"
-set -tmpdir "./xst/tmp"
+set -xsthdpdir xst
+set -tmpdir xst/tmp
 run
--ifn ./project/mips_top.prj
+-ifn project/mips_top.prj
 -ifmt mixed
 -ofn mips_top
 -ofmt NGC

lib/FIFO/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/FIFO/ghdl/fifo_async.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIFO_ASYNC
 

lib/FIFO/ghdl/fifo_sync.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIFO_SYNC
 

lib/FIFO/ghdl/tb_fifo_async.gtkw

@@ -1,35 +1,35 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Mar 23 08:22:19 2021
+[*] Thu Jun 30 17:26:51 2022
 [*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.vcd"
-[dumpfile_mtime] "Tue Mar 23 08:21:16 2021"
-[dumpfile_size] 79616
-[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.gtkw"
+[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.fst"
+[dumpfile_mtime] "Thu Jun 30 17:25:34 2022"
+[dumpfile_size] 2432
+[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_fifo_async.gtkw"
 [timestart] 0
 [size] 1000 600
-[pos] 413 163
+[pos] 2275 292
 *-30.757229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 233
 [signals_width] 166
 [sst_expanded] 1
 [sst_vpaned_height] 144
 @29
-tb_fifo_async.rst
+rst
 @28
-tb_fifo_async.clk_w
-tb_fifo_async.fifo_almost_full
-tb_fifo_async.fifo_full
+clk_w
+fifo_almost_full
+fifo_full
 @22
-tb_fifo_async.din[7:0]
+din[7:0]
 @28
-tb_fifo_async.we
-tb_fifo_async.clk_r
-tb_fifo_async.fifo_almost_empty
-tb_fifo_async.fifo_empty
+we
+clk_r
+fifo_almost_empty
+fifo_empty
 @22
-tb_fifo_async.dout[7:0]
+dout[7:0]
 @28
-tb_fifo_async.re
+re
 [pattern_trace] 1
 [pattern_trace] 0

lib/FIFO/ghdl/tb_fifo_async.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fifo_async.inc
 
 ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_async
 ENTITY := tb_fifo_async
 RUN_TIME := 5us
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/FIFO/ghdl/tb_fifo_sync.gtkw

@@ -1,34 +1,34 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Mar 23 08:21:05 2021
+[*] Thu Jun 30 17:29:48 2022
 [*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.vcd"
-[dumpfile_mtime] "Tue Mar 23 08:20:21 2021"
-[dumpfile_size] 38508
-[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.gtkw"
+[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.fst"
+[dumpfile_mtime] "Thu Jun 30 17:29:20 2022"
+[dumpfile_size] 1617
+[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_fifo_sync.gtkw"
 [timestart] 0
 [size] 1000 600
-[pos] -1 -1
+[pos] 395 8
 *-30.891594 2114000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 233
 [signals_width] 215
 [sst_expanded] 1
 [sst_vpaned_height] 144
 @28
-tb_fifo_sync.clk
-tb_fifo_sync.rst
+clk
+rst
 @29
-tb_fifo_sync.we
+we
 @22
-tb_fifo_sync.din[7:0]
+din[7:0]
 @28
-tb_fifo_sync.re
+re
 @22
-tb_fifo_sync.dout[7:0]
+dout[7:0]
 @28
-tb_fifo_sync.fifo_almost_empty
-tb_fifo_sync.fifo_almost_full
-tb_fifo_sync.fifo_empty
-tb_fifo_sync.fifo_full
+fifo_almost_empty
+fifo_almost_full
+fifo_empty
+fifo_full
 [pattern_trace] 1
 [pattern_trace] 0

lib/FIFO/ghdl/tb_fifo_sync.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fifo_sync.inc
 
 ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_sync
 ENTITY := tb_fifo_sync
 RUN_TIME := 5us
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/FIFO/ghdl/tb_gray_counter.gtkw

@@ -1,11 +1,11 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Mar 23 08:23:15 2021
+[*] Thu Jun 30 17:30:57 2022
 [*]
-[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.vcd"
-[dumpfile_mtime] "Tue Mar 23 08:22:40 2021"
-[dumpfile_size] 12229
-[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.gtkw"
+[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.fst"
+[dumpfile_mtime] "Thu Jun 30 17:30:50 2022"
+[dumpfile_size] 565
+[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_gray_counter.gtkw"
 [timestart] 0
 [size] 1000 600
 [pos] -1 -1
@@ -15,13 +15,13 @@
 [sst_expanded] 1
 [sst_vpaned_height] 144
 @28
-tb_gray_counter.rst
-tb_gray_counter.clk
-tb_gray_counter.ce
-tb_gray_counter.bcnt[2:0]
-tb_gray_counter.bnxt[2:0]
-tb_gray_counter.gcnt[2:0]
+rst
+clk
+ce
+bcnt[2:0]
+bnxt[2:0]
+gcnt[2:0]
 @29
-tb_gray_counter.gnxt[2:0]
+gnxt[2:0]
 [pattern_trace] 1
 [pattern_trace] 0

lib/FIFO/ghdl/tb_gray_counter.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 
 SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd
 SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd
@@ -9,5 +9,5 @@ TARGET := tb_gray_counter
 ENTITY := tb_gray_counter
 RUN_TIME := 1us
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/FIFO/ghdl/tb_reg_stage.gtkw

@@ -0,0 +1,26 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Jun 30 17:32:24 2022
+[*]
+[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_reg_stage/tb_reg_stage.fst"
+[dumpfile_mtime] "Thu Jun 30 17:31:56 2022"
+[dumpfile_size] 672
+[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_reg_stage.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-28.283821 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 233
+[signals_width] 102
+[sst_expanded] 1
+[sst_vpaned_height] 144
+@28
+clk
+rst
+@22
+din[7:0]
+dout[7:0]
+@29
+vld_dout
+[pattern_trace] 1
+[pattern_trace] 0

lib/FIFO/ghdl/tb_reg_stage.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 
 SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd
 SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd
@@ -8,5 +8,5 @@ TARGET := tb_reg_stage
 ENTITY := tb_reg_stage
 RUN_TIME := 1us
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/JBUS/busmaster/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/JBUS/busmaster/ghdl/busmaster_async.inc

@@ -0,0 +1,14 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/defs.mk
+include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+# -----------------------------------------------------------
+PKG_NAME := BUSMASTER_ASYNC
+
+# -----------------------------------------------------------
+$(PKG_NAME)_SRCS := $(FIFO_ASYNC_SRCS)
+$(PKG_NAME)_SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+$(PKG_NAME)_SRCS += $(LIB_PATH)/JBUS/busmaster/src/busmaster_types.vhd
+$(PKG_NAME)_SRCS += $(LIB_PATH)/JBUS/busmaster/src/busmaster_async.vhd
+
+# -----------------------------------------------------------
+

lib/JBUS/busmaster/ghdl/busmaster_sync.inc

@@ -0,0 +1,14 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/defs.mk
+include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
+# -----------------------------------------------------------
+PKG_NAME := BUSMASTER_SYNC
+
+# -----------------------------------------------------------
+$(PKG_NAME)_SRCS := $(FIFO_SYNC_SRCS)
+$(PKG_NAME)_SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+$(PKG_NAME)_SRCS += $(LIB_PATH)/JBUS/busmaster/src/busmaster_types.vhd
+$(PKG_NAME)_SRCS += $(LIB_PATH)/JBUS/busmaster/src/busmaster_sync.vhd
+
+# -----------------------------------------------------------
+

lib/JBUS/busmaster/ghdl/tb_busmaster_async.make

@@ -1,18 +1,14 @@
-include $(VHDL_HOME)/make/defs.mk
-include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+include $(VHDL_HOME)/defs.mk
+include $(LIB_PATH)/JBUS/busmaster/ghdl/busmaster_async.inc
 
-MOD_PATH := $(LIB_PATH)/JBUS/busmaster
-
-SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
-SRCS += $(FIFO_ASYNC_SRCS)
-SRCS += $(MOD_PATH)/src/busmaster_types.vhd
-SRCS += $(MOD_PATH)/src/busmaster_async.vhd
-SRCS += $(MOD_PATH)/src/tb_busmaster_async.vhd
+SRCS += $(BUSMASTER_ASYNC_SRCS)
+SRCS += $(LIB_PATH)/JBUS/busmaster/src/tb_busmaster_async.vhd
 
 # Compile
 TARGET := tb_busmaster_async
 ENTITY := tb_busmaster_async
 RUN_TIME := 80us
+WAVE_FORMAT := vcd
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make

@@ -1,18 +1,14 @@
-include $(VHDL_HOME)/make/defs.mk
-include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
+include $(VHDL_HOME)/defs.mk
+include $(LIB_PATH)/JBUS/busmaster/ghdl/busmaster_sync.inc
 
-MOD_PATH := $(LIB_PATH)/JBUS/busmaster
-
-SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
-SRCS += $(FIFO_SYNC_SRCS)
-SRCS += $(MOD_PATH)/src/busmaster_types.vhd
-SRCS += $(MOD_PATH)/src/busmaster_sync.vhd
-SRCS += $(MOD_PATH)/src/tb_busmaster_sync.vhd
+SRCS += $(BUSMASTER_SYNC_SRCS)
+SRCS += $(LIB_PATH)/JBUS/busmaster/src/tb_busmaster_sync.vhd
 
 # Compile
 TARGET := tb_busmaster_sync
 ENTITY := tb_busmaster_sync
 RUN_TIME := 40us
+WAVE_FORMAT := vcd
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/JBUS/dmac/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/JBUS/dmac/ghdl/tb_dmac_sync.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 
 MOD_PATH := $(LIB_PATH)/JBUS
@@ -14,6 +14,7 @@ SRCS += $(MOD_PATH)/dmac/src/tb_dmac.vhd
 TARGET := tb_dmac_sync
 ENTITY := tb_dmac
 RUN_TIME := 6us
+WAVE_FORMAT := vcd
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/JBUS/memory/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/JBUS/memory/ghdl/tb_ram_wb.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 
 MOD_PATH := $(LIB_PATH)/JBUS/memory
 
@@ -11,5 +11,6 @@ SRCS += $(MOD_PATH)/src/tb_ram_wb.vhd
 TARGET := tb_ram_wb
 ENTITY := tb_ram_wb
 RUN_TIME := 1500ns
+WAVE_FORMAT := vcd
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk

lib/JBUS/memory/ghdl/tb_rom_wb.make

@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 
 MOD_PATH := $(LIB_PATH)/JBUS/memory
 
@@ -10,6 +10,7 @@ SRCS += $(MOD_PATH)/src/tb_rom_wb.vhd
 TARGET := tb_rom_wb
 ENTITY := tb_rom_wb
 RUN_TIME := 1500ns
+WAVE_FORMAT := vcd
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/SDRAM/ddr_sdr_v1_5/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -27,8 +27,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb32.vhd
 TARGET := tb_ctrl_ddr_wb32
 ENTITY := tb_ctrl_ddr_wb32
 RUN_TIME := 200us
+WAVE_FORMAT := vcd
 
-GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -26,8 +26,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb64.vhd
 TARGET := tb_ctrl_ddr_wb64
 ENTITY := tb_ctrl_ddr_wb64
 RUN_TIME := 200us
+WAVE_FORMAT := vcd
 
-GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 

lib/VGA_ctrl/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/VGA_ctrl/ghdl/tb_vga_frontend_jb32.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include vga_frontend_jb32.inc
 
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb32
 ENTITY := tb_vga_frontend_jb32
 RUN_TIME := 20ms
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 # -----------------------------------------------------------
 

lib/VGA_ctrl/ghdl/tb_vga_frontend_jb64.make

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include vga_frontend_jb64.inc
 
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb64
 ENTITY := tb_vga_frontend_jb64
 RUN_TIME := 2ms
 
-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk
 # -----------------------------------------------------------
 

lib/VGA_ctrl/ghdl/vga_backend.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 
 # -----------------------------------------------------------
 PKG_NAME := VGA_BACKEND

lib/VGA_ctrl/ghdl/vga_frontend_jb32.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include vga_backend.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
 

lib/VGA_ctrl/ghdl/vga_frontend_jb64.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc

lib/emac/ghdl/.gitignore.templ

@@ -0,0 +1,4 @@
+.gitignore
+build/
+.gitignore
+build/

lib/emac/ghdl/emac_jbus.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/emac/ghdl/emac_tx.inc
 include $(LIB_PATH)/emac/ghdl/emac_rx.inc

lib/emac/ghdl/emac_rx.inc

@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc