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tb_mips_sys_sim compile clean

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jens
2022-06-30 23:16:01 +02:00
parent 3202f415fb
commit 288ed8d40c
1 changed files with 4 additions and 4 deletions
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projects/mips_sys/ghdl/tb_mips_sys.make
+4 -4
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@@ -14,7 +14,7 @@ SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
SRCS += ../src/sdram_config_sim.vhd
# Clock Generator
SRCS += ../src/clockgen.vhd
SRCS += $(LIB_PATH)/clock/xilinx/src/clockgen.vhd
# MIPS
SRCS += $(MIPS_CORE_SRCS)
@@ -62,8 +62,8 @@ SRCS += $(LIB_PATH)/SSRAM/src/ssram_port_wb.vhd
# SDRAM
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/clock/xilinx/ddr_clk_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/ddr_phy_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
@@ -89,7 +89,7 @@ TARGET := tb_mips_sys
ENTITY = tb_mips_sys
RUN_TIME := 10ms
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk