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- fixed gtkw files

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jens
2022-06-30 19:32:53 +02:00
parent 240c12126a
commit 33c3c31353
4 changed files with 71 additions and 45 deletions
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lib/FIFO/ghdl/tb_fifo_async.gtkw
+17 -17
View File
@@ -1,35 +1,35 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Tue Mar 23 08:22:19 2021
[*] Thu Jun 30 17:26:51 2022
[*]
[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.vcd"
[dumpfile_mtime] "Tue Mar 23 08:21:16 2021"
[dumpfile_size] 79616
[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.gtkw"
[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_fifo_async/tb_fifo_async.fst"
[dumpfile_mtime] "Thu Jun 30 17:25:34 2022"
[dumpfile_size] 2432
[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_fifo_async.gtkw"
[timestart] 0
[size] 1000 600
[pos] 413 163
[pos] 2275 292
*-30.757229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 233
[signals_width] 166
[sst_expanded] 1
[sst_vpaned_height] 144
@29
tb_fifo_async.rst
rst
@28
tb_fifo_async.clk_w
tb_fifo_async.fifo_almost_full
tb_fifo_async.fifo_full
clk_w
fifo_almost_full
fifo_full
@22
tb_fifo_async.din[7:0]
din[7:0]
@28
tb_fifo_async.we
tb_fifo_async.clk_r
tb_fifo_async.fifo_almost_empty
tb_fifo_async.fifo_empty
we
clk_r
fifo_almost_empty
fifo_empty
@22
tb_fifo_async.dout[7:0]
dout[7:0]
@28
tb_fifo_async.re
re
[pattern_trace] 1
[pattern_trace] 0
lib/FIFO/ghdl/tb_fifo_sync.gtkw
+16 -16
View File
@@ -1,34 +1,34 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Tue Mar 23 08:21:05 2021
[*] Thu Jun 30 17:29:48 2022
[*]
[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.vcd"
[dumpfile_mtime] "Tue Mar 23 08:20:21 2021"
[dumpfile_size] 38508
[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.gtkw"
[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_fifo_sync/tb_fifo_sync.fst"
[dumpfile_mtime] "Thu Jun 30 17:29:20 2022"
[dumpfile_size] 1617
[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_fifo_sync.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
[pos] 395 8
*-30.891594 2114000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 233
[signals_width] 215
[sst_expanded] 1
[sst_vpaned_height] 144
@28
tb_fifo_sync.clk
tb_fifo_sync.rst
clk
rst
@29
tb_fifo_sync.we
we
@22
tb_fifo_sync.din[7:0]
din[7:0]
@28
tb_fifo_sync.re
re
@22
tb_fifo_sync.dout[7:0]
dout[7:0]
@28
tb_fifo_sync.fifo_almost_empty
tb_fifo_sync.fifo_almost_full
tb_fifo_sync.fifo_empty
tb_fifo_sync.fifo_full
fifo_almost_empty
fifo_almost_full
fifo_empty
fifo_full
[pattern_trace] 1
[pattern_trace] 0
lib/FIFO/ghdl/tb_gray_counter.gtkw
+12 -12
View File
@@ -1,11 +1,11 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Tue Mar 23 08:23:15 2021
[*] Thu Jun 30 17:30:57 2022
[*]
[dumpfile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.vcd"
[dumpfile_mtime] "Tue Mar 23 08:22:40 2021"
[dumpfile_size] 12229
[savefile] "/home/jens/work/vhdl/trunk/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.gtkw"
[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_gray_counter/tb_gray_counter.fst"
[dumpfile_mtime] "Thu Jun 30 17:30:50 2022"
[dumpfile_size] 565
[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_gray_counter.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
@@ -15,13 +15,13 @@
[sst_expanded] 1
[sst_vpaned_height] 144
@28
tb_gray_counter.rst
tb_gray_counter.clk
tb_gray_counter.ce
tb_gray_counter.bcnt[2:0]
tb_gray_counter.bnxt[2:0]
tb_gray_counter.gcnt[2:0]
rst
clk
ce
bcnt[2:0]
bnxt[2:0]
gcnt[2:0]
@29
tb_gray_counter.gnxt[2:0]
gnxt[2:0]
[pattern_trace] 1
[pattern_trace] 0
lib/FIFO/ghdl/tb_reg_stage.gtkw
+26
View File
@@ -0,0 +1,26 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Jun 30 17:32:24 2022
[*]
[dumpfile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/build/tb_reg_stage/tb_reg_stage.fst"
[dumpfile_mtime] "Thu Jun 30 17:31:56 2022"
[dumpfile_size] 672
[savefile] "/home/jens/work/projects/vhdl/lib/FIFO/ghdl/tb_reg_stage.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
*-28.283821 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 233
[signals_width] 102
[sst_expanded] 1
[sst_vpaned_height] 144
@28
clk
rst
@22
din[7:0]
dout[7:0]
@29
vld_dout
[pattern_trace] 1
[pattern_trace] 0