jens 288ed8d40c tb_mips_sys_sim compile clean

2022-06-30 23:16:01 +02:00

Common

Added .gitignore.templ

2022-06-30 22:54:11 +02:00

lib

Added .gitignore.templ

2022-06-30 23:01:20 +02:00

make

- don't touch gtkw file

2022-06-30 20:24:51 +02:00

projects

tb_mips_sys_sim compile clean

2022-06-30 23:16:01 +02:00

tools

- mips tools: rempoved binary, added sources

2022-06-30 17:01:40 +02:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%