jens cf6a2905a2 - fixed Make path

2022-09-09 19:52:47 +02:00

Common

- fixed Make path

2022-09-09 19:52:47 +02:00

lib

Short test

2022-09-09 15:34:34 +02:00

projects

- fixed Make path

2022-09-09 19:52:47 +02:00

defs.mk

Reafctored defs.mk

2022-09-08 09:10:32 +02:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.2%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.9%

IGOR Pro 0.5%

Other 1.3%