jens ae6738c0bd Unified RAM memory content signals

2022-09-08 11:27:10 +02:00

Common

Added genwopt target

2022-09-08 10:47:09 +02:00

lib

Unified RAM memory content signals

2022-09-08 11:27:10 +02:00

projects

- compile clean with Intel Quartus Prime Lite 21

2022-08-07 14:26:12 +02:00

defs.mk

Reafctored defs.mk

2022-09-08 09:10:32 +02:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

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23 MiB

Languages

VHDL 90.2%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.9%

IGOR Pro 0.5%

Other 1.3%