jens fb4ca98ad3 - fixed path to altera dp ram

2022-08-07 12:31:32 +02:00

Common

Added .gitignore.templ

2022-06-30 22:54:11 +02:00

lib

Updated GTKW files

2022-07-02 13:02:52 +02:00

make

- fixed ngdbuild

2022-07-01 18:17:38 +02:00

projects

- fixed path to altera dp ram

2022-08-07 12:31:32 +02:00

tools

- mips tools: rempoved binary, added sources

2022-06-30 17:01:40 +02:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%