40 lines
1.0 KiB
Makefile
40 lines
1.0 KiB
Makefile
# -----------------------------------------------------------
|
|
include $(VHDL_HOME)/defs.mk
|
|
# -----------------------------------------------------------
|
|
include mips_core.inc
|
|
|
|
# -----------------------------------------------------------
|
|
# UART
|
|
SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
|
|
SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
|
|
SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd
|
|
|
|
# GPIO
|
|
SRCS += $(LIB_PATH)/JBUS/gpio/src/gpio_wb.vhd
|
|
|
|
# Async port
|
|
SRCS += $(LIB_PATH)/JBUS/async_port/src/async_types.vhd
|
|
SRCS += $(LIB_PATH)/JBUS/async_port/src/async_port_wb.vhd
|
|
SRCS += ../src/async_defs.vhd
|
|
|
|
# ROM
|
|
#SRCS += Z:/work/repos/mips/src/bootloader/build/ml402/eb/bootloader.elf.ROM.vhd
|
|
#SRCS += Z:/work/repos/mips/src/bootloader/build/denano/eb/bootloader.elf.ROM.vhd
|
|
SRCS += ../src/bootloader_flash.ROM.vhd
|
|
SRCS += $(LIB_PATH)/JBUS/memory/src/rom_wb.vhd
|
|
|
|
# MIPS
|
|
SRCS += $(MIPS_CORE_SRCS)
|
|
|
|
# TB
|
|
SRCS += ../src/tb_mips_top.vhd
|
|
|
|
# Compile
|
|
TARGET := tb_mips_top
|
|
ENTITY := tb_mips_top
|
|
RUN_TIME ?= 250us
|
|
WAVE_FORMAT ?= ghw
|
|
|
|
include $(VHDL_MAKE_HOME)/ghdl.mk
|
|
|