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Unified RAM memory content signals

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This commit is contained in:
jens
2022-09-08 11:27:10 +02:00
parent 1966db95f1
commit ae6738c0bd
13 changed files with 62 additions and 62 deletions
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lib/rams/altera/src/dpram_1w1r1c_ra.vhd
+4 -4
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@@ -49,18 +49,18 @@ end dpram_1w1r1c_ra;
architecture Behavioral of dpram_1w1r1c_ra is
TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL ram_block: MEM;
TYPE memory_type IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL memory_content: memory_type;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (we_a = '1') THEN
ram_block(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
END IF;
IF (re_b = '1') THEN
dout_b <= ram_block(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
END IF;
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
lib/rams/altera/src/dpram_1w1r2c_ra.vhd
+4 -4
View File
@@ -50,10 +50,10 @@ architecture Behavioral of dpram_1w1r2c_ra is
-- Build a 2-D array type for the RAM
subtype word_t is unsigned((data_width-1) downto 0);
type memory_t is array(2**addr_width-1 downto 0) of word_t;
type memory_type is array(2**addr_width-1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
signal memory_content : memory_type;
begin
@@ -61,7 +61,7 @@ begin
begin
if(rising_edge(clk_a)) then
if(we_a = '1') then
ram(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
@@ -70,7 +70,7 @@ begin
begin
if(rising_edge(clk_b)) then
if(re_b = '1') then
dout_b <= ram(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/altera/src/dpram_1w1r2c_ro.vhd
+4 -4
View File
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
architecture Behavioral of dpram_1w1r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
begin
@@ -59,7 +59,7 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
@@ -68,7 +68,7 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/altera/src/dpram_2w2r2c_ra.vhd
+6 -6
View File
@@ -55,8 +55,8 @@ architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width;
subtype word_t is unsigned (data_width-1 downto 0);
type RAMtype is array (0 to depth-1) of word_t;
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of word_t;
shared variable memory_content : memory_type;
begin
@@ -64,10 +64,10 @@ process (clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
dout_a <= memory_content(to_integer(addr_a));
end if;
end if;
end process;
@@ -77,10 +77,10 @@ process (clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/sim/src/dpram_1w1r1c_ra.vhd
+4 -4
View File
@@ -49,18 +49,18 @@ end dpram_1w1r1c_ra;
architecture Behavioral of dpram_1w1r1c_ra is
TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL ram_block: MEM;
TYPE memory_type IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL memory_content: memory_type;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (we_a = '1') THEN
ram_block(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
END IF;
IF (re_b = '1') THEN
dout_b <= ram_block(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
END IF;
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
lib/rams/sim/src/dpram_1w1r2c_ra.vhd
+4 -4
View File
@@ -48,19 +48,19 @@ end dpram_1w1r2c_ra;
architecture Behavioral of dpram_1w1r2c_ra is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
dout_b <= memory_content(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
lib/rams/sim/src/dpram_1w1r2c_ro.vhd
+4 -4
View File
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
architecture Behavioral of dpram_1w1r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
begin
@@ -59,7 +59,7 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
@@ -68,7 +68,7 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/sim/src/dpram_2w2r2c_ra.vhd
+6 -6
View File
@@ -56,20 +56,20 @@ architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
dout_a <= memory_content(to_integer(addr_a_r));
dout_b <= memory_content(to_integer(addr_b_r));
process (clk_a, clk_b)
begin
if clk_a'event and clk_a = '1' and we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
elsif clk_b'event and clk_b = '1' and we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
memory_content(to_integer(addr_b)) <= din_b;
end if;
end process;
lib/rams/sim/src/dpram_2w2r2c_ro.vhd
+6 -6
View File
@@ -54,8 +54,8 @@ end dpram_2w2r2c_ro;
architecture Behavioral of dpram_2w2r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable memory_content : memory_type;
begin
@@ -63,10 +63,10 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
dout_a <= memory_content(to_integer(addr_a));
end if;
end if;
end process;
@@ -75,10 +75,10 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd
+4 -4
View File
@@ -48,19 +48,19 @@ end dpram_1w1r2c_ra;
architecture Behavioral of dpram_1w1r2c_ra is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
dout_b <= memory_content(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
lib/rams/xilinx/src/dpram_1w1r2c_ro.vhd
+4 -4
View File
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
architecture Behavioral of dpram_1w1r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal memory_content : memory_type;
begin
@@ -59,7 +59,7 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
memory_content(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
@@ -68,7 +68,7 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;
lib/rams/xilinx/src/dpram_2w2r2c_ra.vhd
+6 -6
View File
@@ -56,19 +56,19 @@ architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable memory_content : memory_type;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
dout_a <= memory_content(to_integer(addr_a_r));
dout_b <= memory_content(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
-- if re_a = '1' then
addr_a_r <= addr_a;
@@ -81,7 +81,7 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
-- if re_b = '1' then
addr_b_r <= addr_b;
lib/rams/xilinx/src/dpram_2w2r2c_ro.vhd
+6 -6
View File
@@ -54,8 +54,8 @@ end dpram_2w2r2c_ro;
architecture Behavioral of dpram_2w2r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable memory_content : memory_type;
begin
@@ -63,10 +63,10 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
dout_a <= memory_content(to_integer(addr_a));
end if;
end if;
end process;
@@ -75,10 +75,10 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;