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BRANCH_MIPS_R14

BRANCH_MIPS_TLB

BRANCH_TEST

BRANCH_TEST_2

EMAC_BRANCH_DMA

master

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EMAC_R0

EMAC_R01

EMAC_R1

EMAC_R2

EMAC_R3

EMAC_R4

JCPU_R4

MIPS_PRE_R14

MIPS_R10

MIPS_R10a

MIPS_R10b

MIPS_R11

MIPS_R12

MIPS_R13

MIPS_R9

R1

R2

R3

R4

R5

R6

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R8

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• 1ed8ad5fdc - added jens 2021-04-03 13:05:20 +00:00
• 165500c739 - use single rst signal jens 2021-04-03 09:03:19 +00:00
• b037c0f6fc -opt_level 2 jens 2021-04-02 15:13:31 +00:00
• c8384eb9f6 -opt_level 2 jens 2021-04-02 15:05:27 +00:00
• 484940f8de - removed latch pc_branch_take with latching signal 'branch_ce' jens 2021-04-02 13:28:11 +00:00
• 8e7477b83b - try to add clock buffer constraint jens 2021-04-02 12:42:01 +00:00
• 51f295d37f - JASM : fixed string literals jens 2021-04-01 06:53:44 +00:00
• 2721d59449 - fixed synth project after fifo refactoring - used _ld roms jens 2021-03-31 19:54:32 +00:00
• 1864b98e55 - removed half-cycle register for pc.branch_take - refactored jens 2021-03-31 14:04:22 +00:00
• 8af5e1a8a5 - added extra register for bus master fifos jens 2021-03-31 12:07:35 +00:00
• 9360547eab - FIFO: control extra read register using generic "add_extra_read_register". Default = false jens 2021-03-31 10:18:26 +00:00
• 556dc410f5 - fixed synth project after fifo refactoring jens 2021-03-31 09:55:49 +00:00
• fc50f1f9d3 - added read register stage to fifo jens 2021-03-31 09:37:17 +00:00
• c52c69e8fb - rfacored jens 2021-03-31 09:30:21 +00:00
• 83373bbae5 - fixed full write jens 2021-03-31 09:25:35 +00:00
• c922fbe961 - refacored jens 2021-03-31 08:15:41 +00:00
• 1970a91580 - FIFO: added reg_stage jens 2021-03-31 08:01:43 +00:00
• 4bce0d8107 - remove unrelated path - default effort = high jens 2021-03-30 15:42:52 +00:00
• 7b0201b69c - added MPA_EFFORT, PAR_EFFORT. Default = med jens 2021-03-30 15:26:40 +00:00
• 11567d0f3d - reverted buggy xst settings jens 2021-03-30 15:22:20 +00:00
• d8f6070643 - reverted buggy blanking modification jens 2021-03-30 15:21:08 +00:00
• 0c46a7fe81 - reverted jens 2021-03-30 14:34:27 +00:00
• 3eeaa0a5f5 - fixed overwriting of gtkw files jens 2021-03-30 12:40:10 +00:00
• d7b4ade86c - also specify run time on command line jens 2021-03-30 12:24:38 +00:00
• 84ee9394fe - unrelate bus and cpu clock jens 2021-03-30 09:50:28 +00:00
• 92781859e1 - added more constraints jens 2021-03-30 09:17:34 +00:00
• 19eadde8da - use make/ise.mk jens 2021-03-30 09:17:21 +00:00
• 95a989a001 VGA: refactored clocks and resets jens 2021-03-30 08:57:09 +00:00
• 82f64d5e06 - fixed NETLIST_DIR jens 2021-03-30 07:32:51 +00:00
• 83315b4c17 - VGA backend: use synchronous resets - VGA backend: proc_vga_color_out: keep color signals stable - reduce noise jens 2021-03-30 07:20:00 +00:00
• 24e5cb75cb VGA: refactored clocks and resets jens 2021-03-30 07:11:37 +00:00
• 756dc0ec5a VGA: refactored clocks and resets jens 2021-03-30 06:50:08 +00:00
• 5ffd02c06e - use correct char rom - background is black per default jens 2021-03-29 20:53:09 +00:00
• d34a85dbd0 - added new VGA time specs - fixed ts_vga_800_600_60 jens 2021-03-29 20:06:43 +00:00
• 1aa4dcee1f - use correct rams for synthesis jens 2021-03-29 19:43:27 +00:00
• 99a3711411 - fixed timing issues jens 2021-03-29 19:11:21 +00:00
• 47c9f86bae added jens 2021-03-29 17:55:39 +00:00
• d32d1d090b - refactored jens 2021-03-29 17:52:26 +00:00
• a4b3c6cbb5 - use vga_ctrl_sys jens 2021-03-29 17:47:13 +00:00
• d1e884eb47 - fixed paths after refactoring jens 2021-03-29 16:55:01 +00:00
• e58772981a - fixed paths after refactoring jens 2021-03-29 16:41:44 +00:00
• 1f4de98cea - refactored jens 2021-03-29 16:38:07 +00:00
• 2808f7e893 - refactored clockgens jens 2021-03-29 16:33:48 +00:00
• e8863e01ba - refactored jens 2021-03-29 16:29:02 +00:00
• 1ddbed0820 - fixed ise.mk - cleaned up project/vga_ctrl jens 2021-03-29 16:08:49 +00:00
• d9db6eed75 - update jens 2021-03-29 14:19:41 +00:00
• f538cb1577 - removed sys_vga_clk_out jens 2021-03-29 14:18:11 +00:00
• bd5ea68dda - improved tools install jens 2021-03-29 14:17:51 +00:00
• c1e96aecba - fixed rst - use main_sim for test bench jens 2021-03-29 14:14:22 +00:00
• c34cdf77ac - added main_sim - added docs jens 2021-03-29 14:11:00 +00:00
• 905ec4a05e - fixed path jens 2021-03-29 14:06:17 +00:00
• 15da56174f - fixed opc.list not found jens 2021-03-29 13:37:02 +00:00
• 7467d81909 - improved jens 2021-03-29 13:28:52 +00:00
• e803bf494d - added Makefile jens 2021-03-29 13:19:13 +00:00
• cfe212249a - added jens 2021-03-29 13:14:50 +00:00
• f9051bc51c - refactored ISE makefiles jens 2021-03-29 12:49:42 +00:00
• 14ff542f7a - fixed contention cg_draw jens 2021-03-29 10:48:07 +00:00
• 7efce56819 - fixed cpu_rst jens 2021-03-29 09:10:34 +00:00
• 51899a014d - fixed jens 2021-03-29 08:39:50 +00:00
• 736cf3464d - fixed jens 2021-03-29 08:39:24 +00:00
• 5dad6f21b4 - fixed lowercase bug jens 2021-03-29 08:33:41 +00:00
• b99fc27ccc - fixed paths jens 2021-03-28 18:28:34 +00:00
• dda7811902 - fixed mips_sys after refactoring jens 2021-03-28 18:02:48 +00:00
• 3803aa154c - refactored jens 2021-03-28 17:53:06 +00:00
• d3b0f59c8b - use lower case for WAVE_FORMAT jens 2021-03-28 17:45:33 +00:00
• 0f7a8fb950 - removed old wave select jens 2021-03-28 17:38:25 +00:00
• d0677069e1 - update gtkw jens 2021-03-28 17:26:05 +00:00
• a9da9b8d3d - changed wave format selection jens 2021-03-28 17:25:49 +00:00
• 3c29cd8d3f - updated gtkw jens 2021-03-28 15:38:32 +00:00
• 3b9576c520 - refactored jens 2021-03-28 14:56:00 +00:00
• a8e4af4484 - refactored jens 2021-03-28 14:36:32 +00:00
• f323c6fd7a - added jens 2021-03-28 14:19:46 +00:00
• 619807f898 - added vga_backend.inc (Zwischenstand) jens 2021-03-28 14:18:52 +00:00
• 6fd2570659 - refactored jens 2021-03-28 14:18:09 +00:00
• b9f08b774d - renamed jens 2021-03-28 13:28:02 +00:00
• 6984f03f6f - removed ROOT_PATH - added templates for tb and package jens 2021-03-28 13:27:25 +00:00
• b4f968c7c4 - no disp-time jens 2021-03-28 12:38:28 +00:00
• 2e87c7c8e2 - added new targets jens 2021-03-28 12:32:49 +00:00
• 4b69580c5d - use FST jens 2021-03-28 12:02:56 +00:00
• 1d3ac60495 - fixed aysnc_def jens 2021-03-28 11:22:24 +00:00
• 795ca6b382 - added jens 2021-03-28 11:07:17 +00:00
• 881893fda3 - MIPS core pulls Fifos jens 2021-03-28 10:42:44 +00:00
• ef273a188a - fixed assigning SRC jens 2021-03-28 10:35:35 +00:00
• 06feba8f63 - refactored jens 2021-03-28 10:27:33 +00:00
• d0433ac19d - fixed and use emac_jbus jens 2021-03-27 18:51:23 +00:00
• 3a7cd38951 - added jens 2021-03-27 18:47:07 +00:00
• 8c656907f3 - refactored jens 2021-03-26 16:40:32 +00:00
• 7b2080f729 - fixed xst file jens 2021-03-26 09:55:31 +00:00
• 5f6b6097aa - deleted jens 2021-03-25 13:19:10 +00:00
• d7d8e55e83 - fixed paths after refactoring jens 2021-03-25 12:54:39 +00:00
• 93a4d8905d - added list target - fixed path in ise project for MIPS netlist jens 2021-03-25 12:42:10 +00:00
• 1a346c73d9 - fixed paths after refactoring jens 2021-03-24 20:18:09 +00:00
• 4943c43e32 - fixed paths after refactoring jens 2021-03-24 18:57:18 +00:00
• 599726a7b2 - refactored jens 2021-03-24 18:39:05 +00:00
• ff4700093d - added jens 2021-03-24 18:29:39 +00:00
• 480214099c - added jens 2021-03-24 18:24:22 +00:00
• b3e02ac085 - refactored jens 2021-03-24 18:19:19 +00:00
• f72d1deb10 - added jens 2021-03-24 18:19:03 +00:00
• 0f36365c8f - refactored jens 2021-03-24 17:00:28 +00:00
• 47ec6a20ee - refactored jens 2021-03-24 16:57:19 +00:00