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VGA: refactored clocks and resets

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1593 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-30 06:50:08 +00:00
parent 5ffd02c06e
commit 756dc0ec5a
5 changed files with 39 additions and 46 deletions
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lib/VGA_ctrl/src/tb_vga_frontend_jb32.vhd
+5 -4
View File
@@ -65,6 +65,7 @@ ARCHITECTURE behavior OF tb_vga_frontend_jb32 IS
-- VGA signals
signal vga_clk : std_logic := '1';
signal vga_rst : std_logic;
signal vga_red : unsigned(7 downto 0);
signal vga_green : unsigned(7 downto 0);
signal vga_blue : unsigned(7 downto 0);
@@ -72,7 +73,7 @@ ARCHITECTURE behavior OF tb_vga_frontend_jb32 IS
signal vga_sync_n : std_logic;
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
signal vga_en : std_logic;
BEGIN
@@ -116,8 +117,8 @@ inst_vga_frontend_jb32 : entity work.vga_frontend_jb32
SDAT_O => SDAT_I,
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_en,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -127,7 +128,7 @@ inst_vga_frontend_jb32 : entity work.vga_frontend_jb32
vga_vsync => vga_vsync
);
vga_en <= not RST_O;
vga_rst <= RST_O;
CLK_GEN: process
begin
lib/VGA_ctrl/src/tb_vga_frontend_jb64.vhd
+4 -4
View File
@@ -77,7 +77,7 @@ ARCHITECTURE behavior OF tb_vga_frontend_jb64 IS
signal vga_sync_n : std_logic;
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
signal vga_en : std_logic;
signal vga_rst : std_logic;
type blit_size_array_t is array (0 to 9) of natural;
@@ -412,8 +412,8 @@ inst_vga_frontend_jb64 : entity work.vga_frontend_jb64
SDAT_O => SDAT_I,
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_en,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -423,7 +423,7 @@ inst_vga_frontend_jb64 : entity work.vga_frontend_jb64
vga_vsync => vga_vsync
);
vga_en <= not RST_O;
vga_rst <= RST_O;
rdy_GEN: process
begin
lib/VGA_ctrl/src/vga_backend.vhd
+14 -16
View File
@@ -43,7 +43,6 @@ entity vga_backend is
ctrl_scan_en : in std_logic;
-- Status signals
stat_vga_rdy : out std_logic;
stat_scan : out std_logic;
stat_hsync : out std_logic;
stat_vsync : out std_logic;
@@ -55,8 +54,8 @@ entity vga_backend is
stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- VGA domain signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_clk : in std_logic;
vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -77,7 +76,7 @@ architecture Behavioral of vga_backend is
signal vsync : std_logic;
signal hready : std_logic;
signal vready : std_logic;
signal rst : std_logic;
signal vga_ce : std_logic;
begin
@@ -89,8 +88,8 @@ inst_vga_timing: entity work.vga_timing
PORT MAP
(
sys_rst => sys_rst,
vga_clk => vga_clk_in,
vga_ce => vga_clk_ce,
vga_clk => vga_clk,
vga_ce => vga_ce,
sync_h => hsync,
sync_v => vsync,
scan_pos_h => stat_hpos,
@@ -102,8 +101,7 @@ inst_vga_timing: entity work.vga_timing
);
---------------------------------------------------------------------------------------------
rst <= not vga_clk_ce;
stat_vga_rdy <= vga_clk_ce;
vga_ce <= not vga_rst;
stat_hsync <= hsync;
stat_vsync <= vsync;
stat_hscan <= is_hscan;
@@ -118,11 +116,11 @@ inst_vga_timing: entity work.vga_timing
---------------------------------------------------------------------------------------------
proc_vga_start:
process (rst, vga_clk_in)
process (vga_rst, vga_clk)
begin
if rst = '1' then
if vga_rst = '1' then
scan_enable <= '0';
elsif rising_edge(vga_clk_in) then
elsif rising_edge(vga_clk) then
if vsync = '1' then
if ctrl_scan_en = '1' then
scan_enable <= '1';
@@ -134,11 +132,11 @@ inst_vga_timing: entity work.vga_timing
end process;
proc_vga_color_out:
process (vga_clk_in)
process (vga_clk)
variable do_scan : std_logic;
variable color : color_t;
begin
if rising_edge(vga_clk_in) then
if rising_edge(vga_clk) then
vga_red <= X"00";
vga_green <= X"00";
vga_blue <= X"00";
@@ -157,16 +155,16 @@ inst_vga_timing: entity work.vga_timing
---------------------------------------------------------------------------------------------
proc_vga_sync_out:
process (rst, vga_clk_in)
process (vga_rst, vga_clk)
variable hsync_r : std_logic;
variable vsync_r : std_logic;
begin
if rst = '1' then
if vga_rst = '1' then
vga_hsync <= tsvga.ts_h.sync_polarity;
vga_vsync <= tsvga.ts_v.sync_polarity;
hsync_r := tsvga.ts_h.sync_polarity;
vsync_r := tsvga.ts_v.sync_polarity;
elsif rising_edge(vga_clk_in) then
elsif rising_edge(vga_clk) then
vga_hsync <= hsync_r;
vga_vsync <= vsync_r;
hsync_r := hsync xor (not tsvga.ts_h.sync_polarity);
lib/VGA_ctrl/src/vga_frontend_jb32.vhd
+8 -12
View File
@@ -63,8 +63,8 @@ entity vga_frontend_jb32 is
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_clk : in std_logic;
vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -77,8 +77,6 @@ end vga_frontend_jb32;
architecture Behavioral of vga_frontend_jb32 is
signal vga_clk : std_logic;
-- Color FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
@@ -96,7 +94,6 @@ architecture Behavioral of vga_frontend_jb32 is
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
@@ -160,7 +157,6 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
@@ -172,8 +168,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_in => vga_clk_in,
vga_clk_ce => vga_clk_ce,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -203,7 +199,7 @@ inst_linefifo: entity work.fifo_async
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk_in,
clk_r => vga_clk,
we => fifo_color_we,
re => fifo_color_re,
data_w => fifo_color_in,
@@ -235,7 +231,7 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
process(s, vga_rst, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
begin
CYC_O <= '0';
@@ -248,7 +244,7 @@ vga_master:
case s is
when init =>
if stat_vga_rdy = '1' then
if vga_rst = '0' then
sn <= idle;
end if;
@@ -359,7 +355,7 @@ inst_char_gen : entity work.char_gen
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk_in,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
lib/VGA_ctrl/src/vga_frontend_jb64.vhd
+8 -10
View File
@@ -66,8 +66,8 @@ entity vga_frontend_jb64 is
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_clk : in std_logic;
vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -97,7 +97,6 @@ architecture Behavioral of vga_frontend_jb64 is
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
@@ -413,7 +412,6 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
@@ -425,8 +423,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_in => vga_clk_in,
vga_clk_ce => vga_clk_ce,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -466,7 +464,7 @@ inst_linefifo: entity work.fifo_async
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk_in,
clk_r => vga_clk,
we => fifo_color_we,
re => fifo_color_re,
data_w => fifo_color_in,
@@ -600,7 +598,7 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
process(s, vga_rst, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
begin
CYC_O_scan <= '0';
@@ -616,7 +614,7 @@ vga_master:
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
if vga_rst = '0' then
sn <= rdy;
end if;
@@ -1057,7 +1055,7 @@ inst_char_gen : entity work.char_gen
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk_in,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,