- use vga_ctrl_sys

git-svn-id: http://moon:8086/svn/vhdl/trunk@1586 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-29 17:47:13 +00:00
parent d1e884eb47
commit a4b3c6cbb5
3 changed files with 8 additions and 7 deletions
@@ -21,8 +21,9 @@ vhdl work "../../../../lib/CPUs/JCpu/src/core/int_ctrl.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/pc.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/reg_dual.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/stack_ctrl.vhd"
+vhdl work "../../../../lib/clock/xilinx/src/clockgen.vhd"
 vhdl work "../../src/main_xrom.vhdl"
 vhdl work "../../src/main_irom.vhdl"
 vhdl work "../../src/cpu_embedded.vhd"
 vhdl work "../../src/vga_ctrl_top.vhd"
-
+vhdl work "../../src/vga_ctrl_sys.vhd"
@@ -23,16 +23,16 @@ CONFIG STEPPING = "ES";
 NET sys_clk_in TNM_NET = "sys_clk_in";
 TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;

-NET "inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+NET sys_vga_clk TNM_NET = "vga_clk";
 #TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
 TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG;

 NET sys_clk_in LOC = AE14;
 NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET sys_rstn_in LOC = D6;
-NET sys_rstn_in PULLUP;
-NET sys_rstn_in TIG;
-NET sys_rstn_in IOSTANDARD = LVCMOS33;
+NET sys_rst_n_in LOC = D6;
+NET sys_rst_n_in PULLUP;
+NET sys_rst_n_in TIG;
+NET sys_rst_n_in IOSTANDARD = LVCMOS33;


 ////////////////////////////////////////////////////////////////////////////
@@ -6,7 +6,7 @@ run
 -ofn vga_ctrl_top
 -ofmt NGC
 -p xc4vsx35-10-ff668
-top vga_ctrl_top
+-top vga_ctrl_sys
 -opt_mode Speed
 -opt_level 1
 -power NO