added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1588 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-29 17:55:39 +00:00
parent d32d1d090b
commit 47c9f86bae
1 changed files with 120 additions and 0 deletions
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+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_ctrl_sys is
+	Generic
+	(
+		sys_freq_MHz	: real				:= 100.0;
+		tsvga			: vga_timespec_t := ts_vga_1280_1024_72
+	);
+	Port
+	(
+		sys_rst_n_in	: in std_logic;
+		sys_clk_in		: in std_logic;
+		
+		-- VGA signals
+		sys_vga_clk		: out std_logic;
+		sys_vga_red		: out unsigned(7 downto 0);
+		sys_vga_green	: out unsigned(7 downto 0);
+		sys_vga_blue	: out unsigned(7 downto 0);
+		sys_vga_blank_n	: out std_logic;
+		sys_vga_sync_n	: out std_logic;
+		sys_vga_hsync	: out std_logic;
+		sys_vga_vsync	: out std_logic;
+		
+		-- Buttons and LEDs
+		sys_btn			: in unsigned(4 downto 0);
+		sys_dip			: in unsigned(7 downto 0);
+		sys_led			: out unsigned(8 downto 0)
+	);
+end vga_ctrl_sys;
+
+ARCHITECTURE behavior OF vga_ctrl_sys IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT vga_ctrl_top
+    GENERIC
+    (
+		tsvga			: vga_timespec_t
+	);
+	PORT
+	(
+		rst_in : IN std_logic;
+		clk_in : IN std_logic;    
+		      
+		-- VGA signals
+		vga_clk_in : IN std_logic;
+		vga_clk_ce : IN std_logic;
+		vga_red : OUT unsigned(7 downto 0);
+		vga_green : OUT unsigned(7 downto 0);
+		vga_blue : OUT unsigned(7 downto 0);
+		vga_blank_n : OUT std_logic;
+		vga_sync_n : OUT std_logic;
+		vga_hsync : OUT std_logic;
+		vga_vsync : OUT std_logic;
+		
+		-- Buttons and LEDs
+		dip : in unsigned(7 downto 0);
+		btn : in unsigned(4 downto 0);
+		led : out unsigned(8 downto 0)
+	);
+	END COMPONENT;
+
+	--Constants
+	SIGNAL sys_rst 			:  std_logic;	
+	SIGNAL vga_clk 			:  std_logic;
+	SIGNAL vga_rst			:  std_logic;
+	SIGNAL vga_ce			:  std_logic;
+	constant vga_freq_MHz	: real := real(tsvga.f_pxl_clk)/1.0E6;
+
+BEGIN
+
+	sys_rst <= not sys_rst_n_in;
+	vga_ce	<= not vga_rst;
+	sys_vga_clk <= vga_clk;
+	
+	inst_vga_ctrl_top: vga_ctrl_top 
+	GENERIC MAP 
+	(
+		tsvga		=> tsvga
+	)
+	PORT MAP
+	(
+		rst_in => sys_rst,
+		clk_in => sys_clk_in,
+
+		vga_clk_in => vga_clk,
+		vga_clk_ce => vga_ce,
+		vga_red => sys_vga_red,
+		vga_green => sys_vga_green,
+		vga_blue => sys_vga_blue,
+		vga_blank_n => sys_vga_blank_n,
+		vga_sync_n => sys_vga_sync_n,
+		vga_hsync => sys_vga_hsync,
+		vga_vsync => sys_vga_vsync,
+		
+		dip => sys_dip,
+		btn => sys_btn,
+		led => sys_led
+	);
+
+inst_clockgen_vga : entity work.clockgen
+	GENERIC MAP
+	(
+		clk_in_freq			=> sys_freq_MHz,
+		clk_out_freq		=> vga_freq_MHz
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst_in				=> sys_rst,
+		clk_in				=> sys_clk_in,
+		rst_out				=> vga_rst,
+		clk_out				=> vga_clk
+	);
+
+END;