- unrelate bus and cpu clock

git-svn-id: http://moon:8086/svn/vhdl/trunk@1600 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-30 09:50:28 +00:00
parent 92781859e1
commit 84ee9394fe
1 changed files with 7 additions and 4 deletions
@@ -1,10 +1,13 @@
-# Bus clock nets
-NET "CLK_I" TNM_NET = "sys_clk";
-TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
-
+# CPU clock nets
 NET "cpu_clk" TNM_NET = "cpu_clk";
 TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;

+# Bus clock nets
+NET "CLK_I" TNM_NET = "bus_clk";
+TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 9.9 ns HIGH 50 %;
+TIMESPEC "TS_unrelate_bus_clk" = FROM cpu_clk TO bus_clk TIG;
+
+
 BEGIN MODEL biu
 	INST inst_bin_fifo ram_style = distributed;
 	INST inst_bout_fifo ram_style = distributed;