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- use correct rams for synthesis

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1590 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-29 19:43:27 +00:00
parent 99a3711411
commit 1aa4dcee1f
1 changed files with 2 additions and 2 deletions
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projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj
+2 -2
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@@ -1,4 +1,4 @@
vhdl work "../../../../lib/rams/sim/src/dpram_1w1r2c_ro.vhd"
vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ro.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
@@ -6,7 +6,7 @@ vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../../lib/rams/sim/src/dpram_1w1r2c_ra.vhd"
vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"