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- added list target

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- fixed path in ise project for MIPS netlist

git-svn-id: http://moon:8086/svn/vhdl/trunk@1534 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-25 12:42:10 +00:00
parent 1a346c73d9
commit 93a4d8905d
2 changed files with 25 additions and 17 deletions
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Common/make/ghdl.mk
+7
View File
@@ -52,6 +52,8 @@ GTK_OPTS-$(WITH_GHW) := --wave=$(SIM_FILE-y)
# -------------------------------------------------
# Targets
# -------------------------------------------------
all: analyze
$(WORK_DIR):
@@ -92,6 +94,11 @@ wave: run_wave
result:
exec gtkwave -f $(SIM_FILE-y) -a $(BUILD_DIR)/$(TARGET).gtkw &
.PHONY: list
INSTR = $(foreach number,$(SRCS),echo $(number);)
list:
@$(INSTR)
clean:
rm -rf $(WORK_DIR)
rm -f $(BUILD_DIR)/$(TARGET)*.vcd
lib/CPUs/MIPS/syn/ise101/project/mips_top.prj
+18 -17
View File
@@ -1,21 +1,22 @@
vhdl work "../../../../rams/xilinx/src/dpram_1w1r2c_ra.vhd"
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../FIFO/src/gray_counter.vhd"
vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../src/core/mips_types.vhd"
vhdl work "../../../../FIFO/src/fifo_sync.vhd"
vhdl work "../../../../FIFO/src/gray_counter.vhd"
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_async.vhd"
vhdl work "../../src/core/mips_shifter.vhd"
vhdl work "../../src/core/mips_reg.vhd"
vhdl work "../../src/core/mips_muldiv.vhd"
vhdl work "../../src/core/mips_instr.vhd"
vhdl work "../../src/core/mips_icache.vhd"
vhdl work "../../src/core/mips_dcache.vhd"
vhdl work "../../src/core/mips_bcu.vhd"
vhdl work "../../src/core/mips_alu.vhd"
vhdl work "../../src/core/mips_pipeline.vhd"
vhdl work "../../src/core/mips_cop.vhd"
vhdl work "../../src/core/mips_biu.vhd"
vhdl work "../../src/core/mips_top.vhd"
vhdl work "../../../../rams/xilinx/src/dpram_2w2r2c_ra.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_instr.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_alu.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_bcu.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_biu.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_cop.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_dcache.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_icache.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_muldiv.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_pipeline.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_reg.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_shifter.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_top.vhd"