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- fixed synth project after fifo refactoring

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1613 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-31 09:55:49 +00:00
parent fc50f1f9d3
commit 556dc410f5
2 changed files with 6 additions and 0 deletions
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lib/CPUs/MIPS/syn/ise101/project/mips_top.prj
+3
View File
@@ -1,9 +1,12 @@
vhdl work "../../../../rams/xilinx/src/dpram_1w1r2c_ra.vhd"
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../FIFO/src/reg_stage.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_stage.vhd"
vhdl work "../../../../FIFO/src/fifo_sync.vhd"
vhdl work "../../../../FIFO/src/gray_counter.vhd"
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_async_stage.vhd"
vhdl work "../../../../FIFO/src/fifo_async.vhd"
vhdl work "../../../../rams/xilinx/src/dpram_2w2r2c_ra.vhd"
vhdl work "../../../../CPUs/MIPS/src/core/mips_types.vhd"
projects/mips_sys/ise101/mips_sys/project/mips_sys.prj
+3
View File
@@ -13,7 +13,10 @@ vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/reg_stage.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_stage.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_stage.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd"
vhdl work "../../src/sdram_config.vhd"