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BRANCH_MIPS_R14

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• 84255df928 - Cleaned up jens 2008-10-25 18:09:39 +00:00
• 7b10fe898d This commit was manufactured by cvs2svn to create tag 'R7'. R7 jens 2008-10-25 17:40:43 +00:00
• 9954268b22 - Minor changes jens 2008-10-25 17:40:42 +00:00
• 6597bccd01 - using now dpram_1w1r jens 2008-10-25 17:26:07 +00:00
• a6c7859e22 - Cleaned up jens 2008-10-25 17:23:04 +00:00
• 1c7fd9022e - Intital revision jens 2008-10-25 17:20:15 +00:00
• 5120448104 - using bui-generics for cache sizes jens 2008-10-25 17:16:21 +00:00
• 8e41790680 - added generics for cache sizes jens 2008-10-25 17:16:05 +00:00
• 08317c7744 - Removed DEADBEEF-garbage jens 2008-10-25 17:09:13 +00:00
• 9918af8a12 - Removed dirty-bit which is not needed by Direct-Mapped Cache jens 2008-10-25 17:08:37 +00:00
• 8102a16c3c - Removed linefifo - Uses now lib/FIFO/fifo_async.vhd jens 2008-10-25 12:27:38 +00:00
• 726afd3362 This commit was manufactured by cvs2svn to create tag 'R6'. R6 jens 2008-10-25 11:48:05 +00:00
• ed47f478f8 - Switched to 64-Bit SDRAM- and VGA-controller jens 2008-10-25 11:48:04 +00:00
• 7cdfa6929d - Intital revision jens 2008-10-25 11:26:06 +00:00
• 16b4f2b138 - Bugfix: changed 'ptr_r' from 'bcnt_r' to 'bnxt_r' to prevent read delay when FIFO is read (re = 1) jens 2008-10-25 11:21:47 +00:00
• 7ccefbab86 - Removed linefifo - Uses now lib/FIFO/fifo_async.vhd jens 2008-10-25 11:15:26 +00:00
• 5abe0f9234 -Removed linefifo.vhd and dpram.vhd - Uses now lib/FIFO/fifo_async.vhd jens 2008-10-25 11:14:50 +00:00
• 29eb6a05c3 - Cleaned up jens 2008-10-25 11:11:52 +00:00
• 2c95fae0ab - Minor changes jens 2008-10-25 00:23:56 +00:00
• 545379c99d - added conversion functions unsigned <=> color_t jens 2008-10-25 00:15:29 +00:00
• 533a0bd328 - Intital revision jens 2008-10-24 20:56:28 +00:00
• b81ce94c39 - Cleaned up jens 2008-10-24 20:56:13 +00:00
• 48c7618752 - Minor changes jens 2008-10-23 22:06:41 +00:00
• 5c63d629a7 - Cleaned up jens 2008-10-23 22:06:34 +00:00
• 36e8cd1e00 - Using MODELSIM_HOME environment variable jens 2008-10-23 21:21:24 +00:00
• c90b63d476 - Intital revision jens 2008-10-23 21:20:28 +00:00
• 41593cbc54 - Intital revision jens 2008-10-23 09:49:42 +00:00
• 0bba7d2e10 - added area constraint for "inst_mips_top" jens 2008-10-22 09:47:34 +00:00
• a5f0a35f80 - Minor changes jens 2008-10-21 19:32:11 +00:00
• 5bd0c6ea4a - Update jens 2008-10-21 19:29:57 +00:00
• 1929d9374e - Removed User ROM stuff jens 2008-10-21 18:52:14 +00:00
• c9900e509a - Loading app from Flash instead User ROM - Removed User ROM jens 2008-10-21 18:24:56 +00:00
• 029bf8eb22 - changed some directories jens 2008-10-21 18:24:03 +00:00
• 8060efb864 - Minor changes jens 2008-10-21 18:23:29 +00:00
• 3f62f79d12 - Intital revision jens 2008-10-21 17:23:58 +00:00
• fdc3664187 Minor changes jens 2008-10-20 19:26:51 +00:00
• 69697d7222 - Intital revision jens 2008-10-20 19:26:01 +00:00
• 419ccc4edf Minor changes jens 2008-10-20 19:11:30 +00:00
• b67911c65d - added TM_NET for DDR-clock jens 2008-10-20 09:55:32 +00:00
• e9e132b3e6 - Cleaned up jens 2008-10-19 21:53:51 +00:00
• 32cbb4fc13 - Cleaned up jens 2008-10-19 21:29:45 +00:00
• 9e404bfb06 - Intital revision jens 2008-10-19 21:12:34 +00:00
• 0ea7ced5e3 - Removed linefifo and clockgen (=> frontend and top) jens 2008-10-19 21:11:46 +00:00
• de0a8c6e17 Minor changes jens 2008-10-19 21:10:51 +00:00
• f59e4dd7d1 - Added Sync. SRAM jens 2008-10-19 20:23:27 +00:00
• 85bf744892 - Intital revision jens 2008-10-19 20:13:28 +00:00
• 891e764a23 - Added VGA jens 2008-10-19 20:03:28 +00:00
• 20b3bfb41b - Added Sync. SRAM jens 2008-10-19 20:02:45 +00:00
• 8a8adce98e - using now 64-bit SDR interface (2 SDRAMS) jens 2008-10-18 13:31:15 +00:00
• 051b4182f1 - Cleaned up jens 2008-10-18 12:49:30 +00:00
• 3685973be8 - using now 64-bit SDR interface (2 SDRAMS) jens 2008-10-18 11:37:01 +00:00
• b656e2890b Minor changes jens 2008-10-18 11:36:33 +00:00
• f50a47246a - introduced per-bank activation (avoids multiple activations on same bank) - some other improvements jens 2008-10-18 11:36:07 +00:00
• eaeb68ad28 This commit was manufactured by cvs2svn to create tag 'R5'. R5 jens 2008-10-17 17:41:45 +00:00
• c104c6e67d - Intital revision jens 2008-10-17 17:41:44 +00:00
• c96015bbad - Removed distributed DPRAM reference jens 2008-10-17 17:41:15 +00:00
• fe372f0efa - Removed registered CYC_O (didn't work) jens 2008-10-17 17:35:07 +00:00
• 61b2095bf8 - Shortened read cycles - Minor improvements jens 2008-10-17 14:26:02 +00:00
• 329c639c1a - Shortened BUS-cycle by one clock jens 2008-10-17 14:25:30 +00:00
• f8962066f0 - Registered CYC_O jens 2008-10-17 13:39:07 +00:00
• 1c499c6b34 - Added VGA master/slave jens 2008-10-16 23:12:14 +00:00
• 225e0d5eeb - Added VGA component jens 2008-10-15 21:55:34 +00:00
• f960a13953 Simplified jens 2008-10-15 11:16:47 +00:00
• c8da959dbb - Moved to lib/FIFO jens 2008-10-14 17:12:22 +00:00
• 78db345b82 - Intital revision - Moved from SDRAM v1.5 to here jens 2008-10-14 17:11:50 +00:00
• fda12e53c3 - Uses now full capacity of SDRAM (64-Bit interface on ML-402) - Removed read data mask jens 2008-10-14 17:09:30 +00:00
• 40d96126e7 - Removed read data mask jens 2008-10-14 17:07:48 +00:00
• 959217a81c Minor changes jens 2008-10-14 14:55:15 +00:00
• 91347dd60e - Output pre_empty and pre_full for safer DPRAM control jens 2008-10-12 18:04:36 +00:00
• 3be3800dc7 Registered rdy (better timing) jens 2008-10-12 14:12:14 +00:00
• 9e28b9588c This commit was manufactured by cvs2svn to create tag 'R4'. R4 jens 2008-10-12 12:50:02 +00:00
• 0bc9ef0b00 - Simplfied (better timing) jens 2008-10-12 12:50:01 +00:00
• 5694dddd9f - Changed we to be - Changed r_wn to we jens 2008-10-12 11:02:41 +00:00
• b47d55d61f Cleaned up jens 2008-10-12 11:01:40 +00:00
• 14489d80e9 Bug fix: Uncached read and buffer write in different state jens 2008-10-11 20:14:54 +00:00
• de6bd8f29c Bug fix: Address and data latch only if ready jens 2008-10-11 20:13:52 +00:00
• b6309838f1 Minor changes jens 2008-10-10 21:33:10 +00:00
• 25a276d19b Intital revision jens 2008-10-10 21:31:24 +00:00
• f1e2601c27 Added bus fifo and write fifo jens 2008-10-10 21:30:42 +00:00
• c17d99dc2b Added instant RAW avoidance jens 2008-10-10 21:28:58 +00:00
• b3684f6403 deleted jens 2008-10-10 21:27:32 +00:00
• 1afb05d18a Intital revision jens 2008-10-10 21:25:58 +00:00
• 72cc8491e7 This commit was manufactured by cvs2svn to create tag 'R3'. R3 jens 2008-10-10 21:25:18 +00:00
• db98ad86d2 Removed ACK for J-Bus writes jens 2008-10-10 21:25:17 +00:00
• 1493e3e779 - Inhibit RAM write if FIFO is full - Inhibit update of output if last word is read jens 2008-10-10 21:23:27 +00:00
• 3015a0c6de Minor changes jens 2008-10-09 18:23:28 +00:00
• bea026d12b This commit was manufactured by cvs2svn to create tag 'R2'. R2 jens 2008-10-09 12:26:33 +00:00
• beca7f7ec8 Cleaned up jens 2008-10-09 12:26:32 +00:00
• 7e82a94595 - STB_O now deasserts only if SRDY active (fixes bus freezes during heavy traffic) jens 2008-10-09 11:53:48 +00:00
• 86866b26a7 - Added bus error signals jens 2008-10-09 11:51:55 +00:00
• 098b5982b2 - Added bus error signals for IBE/DBE generation jens 2008-10-09 11:51:17 +00:00
• 2a0d20f4b2 - Added Bus timeout detection - STB_O, ADDR_O registered to output when SRDY jens 2008-10-09 11:50:07 +00:00
• b117df0bc9 Ints are registered jens 2008-10-08 19:34:37 +00:00
• 316b998f86 Added data mask support jens 2008-10-08 19:33:27 +00:00
• e873c4ef07 Masked IPs are not shown in CR jens 2008-10-08 19:33:08 +00:00
• dd38d30198 Introduced J-Bus jens 2008-10-07 17:26:27 +00:00
• 3ecd76f185 Minor changes jens 2008-10-07 17:20:44 +00:00
• f2ebee9703 - Registered ACK - 32bit Host I/F jens 2008-10-07 17:19:52 +00:00
• 6eb25882ba Intital revision jens 2008-10-02 13:37:55 +00:00
• de0e513eb0 Added data mask (read) support jens 2008-10-02 13:27:32 +00:00