Initial revision

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/branches/EMAC_BRANCH_DMA@1035 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/.directory_history

@@ -1,8 +0,0 @@
-VHDL/lib/FIFO/src/async_fifo_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
-
-VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
-
-VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -1,248 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-LIBRARY WORK;
-USE WORK.FIFO_CTRL_PKG.ALL;
-
-entity fifo_async_ctrl is
-	Generic 
-	(
-		addr_width : integer := 3;
-		almost_full_thresh : integer := 6;
-		almost_empty_thresh : integer := 2
-	);
-	Port
-	(
-		rst					: in  STD_LOGIC;
-		clk_w				: in  STD_LOGIC;
-		clk_r				: in  STD_LOGIC;
-		winc				: in  STD_LOGIC;
-		rinc				: in  STD_LOGIC;
-		ptr_w				: out unsigned (addr_width-1 downto 0);
-		ptr_r				: out unsigned (addr_width-1 downto 0);
-		fifo_pre_full		: out STD_LOGIC;
-		fifo_pre_empty		: out STD_LOGIC;
-		fifo_full			: out STD_LOGIC;
-		fifo_empty			: out STD_LOGIC;
-		fifo_afull			: out STD_LOGIC;
-		fifo_aempty			: out STD_LOGIC
-	);
-end fifo_async_ctrl;
-
-architecture Behavioral of fifo_async_ctrl is
-
-	signal gcnt_w		: unsigned (addr_width downto 0);
-	signal gcnt2_w		: unsigned (addr_width downto 0);
-	signal bcnt2_aw		: unsigned (addr_width downto 0);
-	signal bcnt_w		: unsigned (addr_width downto 0);
-	signal gnxt_w		: unsigned (addr_width downto 0);
-	signal bnxt_w		: unsigned (addr_width downto 0);
-	signal gcnt_r		: unsigned (addr_width downto 0);
-	signal gcnt2_r		: unsigned (addr_width downto 0);
-	signal bcnt2_ar		: unsigned (addr_width downto 0);
-	signal bcnt_r		: unsigned (addr_width downto 0);
-	signal gnxt_r		: unsigned (addr_width downto 0);
-	signal bnxt_r		: unsigned (addr_width downto 0);
-
-	signal pre_empty, pre_full : std_logic;
-	signal full, empty : std_logic;
-
-	-- synthesis translate_off
-	signal diffw		: signed (addr_width downto 0);
-	signal diffr		: signed (addr_width downto 0);
-	-- synthesis translate_on
-
-begin
-
-	ptr_w			<= bcnt_w(addr_width-1 downto 0);
-	ptr_r			<= bnxt_r(addr_width-1 downto 0);
-	fifo_full		<= full;
-	fifo_empty		<= empty;
-	fifo_pre_full	<= pre_full;
-	fifo_pre_empty	<= pre_empty;
-	
-proc_write_inhibit:
-	process(rst, clk_w)
-	begin
-		if rst = '1' then
-			full	<= '0';
-		elsif rising_edge(clk_w) then
-			full	<= pre_full;
-		end if;
-	end process;
-	
-proc_read_inhibit:
-	process(rst, clk_r)
-	begin
-		if rst = '1' then
-			empty	<= '1';
-		elsif rising_edge(clk_r) then
-			empty	<= pre_empty;
-		end if;
-	end process;
-
-proc_sync_grptr:
-	process(clk_w)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_w) then
-			gcnt2_r <= p2;
-			p2 := p1;
-			p1 := gcnt_r;
-		end if;
-	end process;
-
-proc_ptr_gwptr:
-	process(clk_r)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_r) then
-			gcnt2_w <= p2;
-			p2 := p1;
-			p1 := gcnt_w;
-		end if;
-	end process;
-	
-proc_status_full:
-	process(gnxt_w, gcnt2_r)
-	begin
-		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
-			pre_full <= '1';
-		else
-			pre_full <= '0';
-		end if;
-	end process;
-
-proc_status_empty:
-	process(gnxt_r, gcnt2_w)
-	begin
-		if (gnxt_r = gcnt2_w) then
-			pre_empty <= '1';
-		else
-			pre_empty <= '0';
-		end if;
-	end process;
-	
-proc_sync_arptr:
-	process(clk_w)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_w) then
-			bcnt2_ar <= p2;
-			p2 := p1;
-			p1 := bcnt_r;
-		end if;
-	end process;
-
-proc_ptr_awptr:
-	process(clk_r)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_r) then
-			bcnt2_aw <= p2;
-			p2 := p1;
-			p1 := bcnt_w;
-		end if;
-	end process;
-	
-proc_status_almost_full:
-	process(rst, clk_w)
-	variable diff : unsigned (addr_width downto 0);
-	begin
-	-- synthesis translate_off
-		diffw <= signed(diff);
-	-- synthesis translate_on
-		if rst = '1' then
-			fifo_afull <= '0';
-			diff := (others => '0');
-		elsif rising_edge(clk_w) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
-		end if;
-	end process;
-
-proc_status_almost_empty:
-	process(rst, clk_r)
-	variable diff : unsigned (addr_width downto 0);
-	begin
-	-- synthesis translate_off
-		diffr <= signed(diff);
-	-- synthesis translate_on
-		if rst = '1' then
-			fifo_aempty <= '1';
-			diff := (others => '0');
-		elsif rising_edge(clk_r) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
-		end if;
-	end process;
-
-inst_gray_counter_w : entity work.gray_counter
-	generic map
-	(
-		width => addr_width+1,
-		init_value => 0
-		)
-	port map
-	(
-		rst			=> rst,
-		clk			=> clk_w,
-		ce			=> winc, 
-		bcnt		=> bcnt_w,
-		bnxt		=> bnxt_w,
-		gcnt		=> gcnt_w,
-		gnxt		=> gnxt_w
-	);
-
-inst_gray_counter_r : entity work.gray_counter
-	generic map
-	(
-		width => addr_width+1,
-		init_value => 0
-		)
-	port map
-	(
-		rst			=> rst,
-		clk			=> clk_r,
-		ce			=> rinc, 
-		bcnt		=> bcnt_r,
-		bnxt		=> bnxt_r,
-		gcnt		=> gcnt_r,
-		gnxt		=> gnxt_r
-	);
-
-end Behavioral;
-

lib/FIFO/src/fifo_async.vhd

@@ -1,124 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_async is
-	Generic
-	(
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4;
-		allow_full_writes	: boolean := false;
-		allow_empty_reads	: boolean := false;
-		do_last_read_update	: boolean := true
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk_w		: in  STD_LOGIC;
-		clk_r		: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_async;
-
-architecture Behavioral of fifo_async is
-	
-	signal mem_wr_en	: STD_LOGIC;
-	signal mem_rd_en	: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: std_logic;
-	signal empty		: std_logic;
-	signal pre_full		: STD_LOGIC;
-	signal pre_empty	: STD_LOGIC;
-	signal rinc			: std_logic;
-	
-begin
-
-	fifo_full	<= full;
-	fifo_empty	<= empty;
-	
-	mem_wr_en	<= (we and not full) when allow_full_writes = false else we;
-	rinc		<= (re and not empty) when allow_empty_reads = false else re;
-	mem_rd_en	<= not pre_empty when do_last_read_update = false else '1';
-	
-	
-	inst_fifo_async_ctrl: entity work.fifo_async_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=>	rst,
-		clk_w			=>	clk_w,
-		clk_r			=>	clk_r,
-		winc			=>	mem_wr_en,
-		rinc			=>	rinc,
-		ptr_w			=>	ptr_w,
-		ptr_r			=>	ptr_r,
-		fifo_full		=>	full,
-		fifo_empty		=>	empty,
-		fifo_pre_full	=>	pre_full,
-		fifo_pre_empty	=>	pre_empty,
-		fifo_afull		=>	fifo_afull,
-		fifo_aempty		=>	fifo_aempty
-
-	);
-
-inst_dpram_1w1r: entity work.dpram_1w1r
-	GENERIC MAP
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clka		=> clk_w,
-		clkb		=> clk_r,
-		en_a		=> '1',
-		en_b		=> mem_rd_en,
-		we_a		=> mem_wr_en,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-
-end Behavioral;
-

lib/FIFO/src/fifo_ctrl_pkg.vhd

@@ -1,67 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package fifo_ctrl_pkg is
-
-	-- Constants
-	-- Types
-	
-	-- Functions
-	function bin2gray(xb : unsigned) return unsigned;
-	function gray2bin(xg : unsigned) return unsigned;
-
-end fifo_ctrl_pkg;
-
-package body fifo_ctrl_pkg is
-
-	function bin2gray(xb : unsigned) return unsigned is
-	variable xg : unsigned(xb'left downto xb'right);
-	begin
-	
-    	xg(xg'left) := xb(xb'left);
-		for i in 1 to xb'left loop
-			xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
-		end loop;
-	
-		return xg;
-	end bin2gray;
-	
-	function gray2bin(xg : unsigned) return unsigned is
-	variable xb : unsigned(xg'left downto xg'right);
-	begin
-
-     	xb(xb'left) := xg(xg'left);
-		for i in 1 to xg'left loop
-			xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
-		end loop;
-		
-		return xb;
-	end gray2bin;
-
-end fifo_ctrl_pkg;
-

lib/FIFO/src/fifo_sync.vhd

@@ -1,123 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_sync is
-	Generic 
-	(
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4;
-		allow_full_writes	: boolean := false;
-		allow_empty_reads	: boolean := false;
-		do_last_read_update	: boolean := true
-		
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_sync;
-
-architecture Behavioral of fifo_sync is
-	
-	signal mem_wr_en	: STD_LOGIC;
-	signal mem_rd_en	: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: STD_LOGIC;
-	signal empty		: std_logic;
-	signal pre_full		: STD_LOGIC;
-	signal pre_empty	: STD_LOGIC;
-	signal rinc			: std_logic;
-	
-begin
-
-	fifo_full	<= full;
-	fifo_empty	<= empty;
-
-	mem_wr_en	<= (we and not full) when allow_full_writes = false else we;
-	rinc		<= (re and not empty) when allow_empty_reads = false else re;
-	mem_rd_en	<= not pre_empty when do_last_read_update = false else '1';
-
-
-inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=>	rst,
-		clk				=>	clk,
-		winc			=>	mem_wr_en,
-		rinc			=>	rinc,
-		ptr_w			=>	ptr_w,
-		ptr_r			=>	ptr_r,
-		fifo_full		=>	full,
-		fifo_empty		=>	empty,
-		fifo_pre_full	=>	pre_full,
-		fifo_pre_empty	=>	pre_empty,
-		fifo_afull		=>	fifo_afull,
-		fifo_aempty		=>	fifo_aempty
-
-	);
-
-inst_dpram_1w1r: entity work.dpram_1w1r
-	GENERIC MAP
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
-		en_a		=> '1',
-		en_b		=> mem_rd_en,
-		we_a		=> mem_wr_en,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-	
-end Behavioral;
-

lib/FIFO/src/gray_counter.vhd

@@ -1,84 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-LIBRARY WORK;
-USE WORK.FIFO_CTRL_PKG.ALL;
-
-entity gray_counter is
-	Generic (
-		width : natural := 3;
-		init_value : natural := 0
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		bcnt		: out unsigned (width-1 downto 0);
-		bnxt		: out unsigned (width-1 downto 0);
-		gcnt		: out unsigned (width-1 downto 0);
-		gnxt		: out unsigned (width-1 downto 0)
-	);
-end gray_counter;
-
-architecture Behavioral of gray_counter is
-
-	signal cntg : unsigned (width-1 downto 0);
-	signal cntb : unsigned (width-1 downto 0);
-	signal nxtb : unsigned (width-1 downto 0);
-	signal nxtg : unsigned (width-1 downto 0);
-
-begin
-
-	bnxt	<= nxtb;
-	gnxt	<= nxtg;
-	bcnt	<= cntb;
-	gcnt	<= cntg;
-
-	process(rst, clk, ce, cntb, nxtb)
-	begin
-		if rst = '1' then
-			cntb	<= to_unsigned(init_value, width);
-			nxtb	<= to_unsigned(init_value, width);
-			nxtg	<= to_unsigned(init_value, width);
-			cntg	<= to_unsigned(init_value, width);
-		else
-			if rising_edge(clk) then
-				cntg	<= nxtg;
-				cntb	<= nxtb;
-			end if;	
-			nxtg <= bin2gray(nxtb);
-			nxtb <= cntb;
-			if ce = '1' then
-				nxtb <= cntb + 1;
-			end if;	
-		end if;	
-	end process;
-
-end Behavioral;
-

lib/FIFO/src/sync_fifo_ctrl.vhd

@@ -1,198 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity fifo_sync_ctrl is
-	Generic
-	(
-		addr_width : integer := 3;
-		almost_full_thresh : integer := 6;
-		almost_empty_thresh : integer := 2
-	);
-	Port
-	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		winc			: in  STD_LOGIC;
-		rinc			: in  STD_LOGIC;
-		ptr_w			: out unsigned (addr_width-1 downto 0);
-		ptr_r			: out unsigned (addr_width-1 downto 0);
-		fifo_pre_full	: out STD_LOGIC;
-		fifo_pre_empty	: out STD_LOGIC;
-		fifo_full		: out STD_LOGIC;
-		fifo_empty		: out STD_LOGIC;
-		fifo_afull		: out STD_LOGIC;
-		fifo_aempty		: out STD_LOGIC
-	);
-end fifo_sync_ctrl;
-
-architecture Behavioral of fifo_sync_ctrl is
-
-	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
-	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
-	signal empty, full : std_logic;
-	signal pre_empty, pre_full : std_logic;
-	signal was_write : std_logic;
-	signal diff : unsigned (addr_width downto 0);
-	
-begin
-
-	fifo_full		<= full;
-	fifo_empty		<= empty;
-	fifo_pre_full	<= pre_full;
-	fifo_pre_empty	<= pre_empty;
-
-
-proc_diff_gen:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			diff <= (others => '0');
-		elsif rising_edge(clk) then
-			if winc = '1' and rinc = '0' then
-				diff <= diff + 1;
-			elsif winc = '0' and rinc = '1' then
-				diff <= diff - 1;
-			end if;
-		end if;
-	end process;
-
-proc_status_almost_full:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			fifo_afull <= '0';
-		elsif rising_edge(clk) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
-		end if;
-	end process;
-
-proc_status_almost_empty:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			fifo_aempty <= '1';
-		elsif rising_edge(clk) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
-		end if;
-	end process;
-
-proc_full_reg:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			full <= '0';
-		elsif rising_edge(clk) then
-			full <= pre_full;
-		end if;
-	end process;
-	
-proc_empty_reg:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			empty <= '1';
-		elsif rising_edge(clk) then
-			empty <= pre_empty;
-		end if;
-	end process;
-	
-proc_status_w:
-	process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
-	begin
-		if (pW_next = pR) and (winc = '1' or was_write = '1') then
-			pre_full <= '1';
-		else
-			pre_full <= '0';
-		end if;
-		if (pR_next = pW) and (rinc = '1' or was_write = '0') then
-			pre_empty <= '1';
-		else
-			pre_empty <= '0';
-		end if;
-	end process;
-
-proc_flag_write:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			was_write <= '0';
-		elsif rising_edge(clk) then
-			if winc = '1' then
-				was_write <= '1';
-			elsif rinc = '1' then
-				was_write <= '0';
-			end if;
-		end if;
-	end process;
-	
-proc_ptr_w:
-	process(rst, clk, pW, winc)
-	begin
-		if rst = '1' then
-			pW <= to_unsigned(0, addr_width);
-			pW_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if winc = '1' then 
-				pW <= pW_next;
-			end if;
-		end if;
-		pW_next <= pW;
-		if winc = '1' then 
-			pW_next <= pW + 1;
-		end if;
-		ptr_w		<= pW;
-	end process;
-
-proc_ptr_r:
-	process(rst, clk, pR_next, pR, rinc)
-	begin
-		if rst = '1' then
-			pR <= to_unsigned(0, addr_width);
-			pR_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if rinc = '1' then
-				pR <= pR_next;
-			end if;	
-		end if;
-		pR_next	<= pR;
-		if rinc = '1' then
-			pR_next	<= pR + 1;
-		end if;
-		ptr_r		<= pR_next;
-	end process;
-
-end Behavioral;
-

lib/emac/.directory_history

@@ -0,0 +1,2 @@
+VHDL/lib/emac/emac_jb.vhd
+

lib/emac/sim/.directory_history

@@ -0,0 +1,8 @@
+VHDL/lib/emac/sim/tb_emac_jb.fdo
+VHDL/lib/emac/sim/tb_serdes.fdo
+VHDL/lib/emac/sim/tb_emac_jb.wdo
+VHDL/lib/emac/sim/tb_serdes.wdo
+VHDL/lib/emac/sim/tb_serdes.fdo
+
+VHDL/lib/emac/sim/tb_serdes.wdo
+

lib/emac/sim/tb_crc32.fdo

@@ -0,0 +1,14 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../src/crc32.vhd"
+vcom -explicit  -93 "../src/tb_crc32.vhd"
+vsim -t 1ps   -lib work tb_crc32
+view wave
+do {tb_crc32.wdo}
+view structure
+view signals
+
+run 1 us

lib/emac/sim/tb_crc32.wdo

@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_crc32/clk
+add wave -noupdate -format Logic /tb_crc32/rst
+add wave -noupdate -format Logic /tb_crc32/din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/crc32
+add wave -noupdate -format Logic /tb_crc32/crc32_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/test_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {667016 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {1050 ns}

lib/emac/sim/tb_emac_jb.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../src/piso.vhd"
+vcom -explicit  -93 "../src/sipo.vhd"
+vcom -explicit  -93 "../src/tb_serdes.vhd"
+vsim -t 1ps   -lib work tb_serdes
+view wave
+do {tb_serdes.wdo}
+view structure
+view signals
+
+run 20 us

lib/emac/sim/tb_emac_jb.wdo

@@ -0,0 +1,58 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_serdes/clk
+add wave -noupdate -format Logic /tb_serdes/rst
+add wave -noupdate -divider PiSo
+add wave -noupdate -format Logic /tb_serdes/clk
+add wave -noupdate -format Logic /tb_serdes/piso_din_vld
+add wave -noupdate -format Logic /tb_serdes/piso_din_rdy
+add wave -noupdate -format Literal /tb_serdes/piso_din_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din
+add wave -noupdate -format Logic /tb_serdes/piso_dout_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout
+add wave -noupdate -format Logic /tb_serdes/piso_dout_en
+add wave -noupdate -divider SiPo
+add wave -noupdate -format Logic /tb_serdes/clk
+add wave -noupdate -format Logic /tb_serdes/sipo_enable
+add wave -noupdate -format Logic /tb_serdes/sipo_rst
+add wave -noupdate -format Logic /tb_serdes/sipo_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din
+add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld
+add wave -noupdate -format Logic /tb_serdes/sipo_dout_en
+add wave -noupdate -format Literal /tb_serdes/sipo_dout_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout
+add wave -noupdate -divider PiSo
+add wave -noupdate -format Logic /tb_serdes/clk
+add wave -noupdate -format Logic /tb_serdes/piso2_din_vld
+add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy
+add wave -noupdate -format Literal /tb_serdes/piso2_din_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din
+add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout
+add wave -noupdate -format Logic /tb_serdes/piso2_dout_en
+add wave -noupdate -divider SiPo
+add wave -noupdate -format Logic /tb_serdes/clk
+add wave -noupdate -format Logic /tb_serdes/sipo2_enable
+add wave -noupdate -format Logic /tb_serdes/sipo2_rst
+add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din
+add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld
+add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en
+add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {21 us}

lib/emac/sim/tb_emac_top_jb.fdo

@@ -0,0 +1,34 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../../JBUS/src/busmaster_types.vhd"
+vcom -explicit  -93 "../../JBUS/src/busmaster_sync.vhd"
+vcom -explicit  -93 "../../JBUS/src/dmac.vhd"
+vcom -explicit  -93 "../src/piso.vhd"
+vcom -explicit  -93 "../src/sipo.vhd"
+vcom -explicit  -93 "../src/crc32.vhd"
+vcom -explicit  -93 "../src/emac_types.vhd"
+vcom -explicit  -93 "../src/emac_rx.vhd"
+vcom -explicit  -93 "../src/emac_tx.vhd"
+vcom -explicit  -93 "../src/emac_top_jb.vhd"
+vcom -explicit  -93 "../src/pkt_gen.vhd"
+vcom -explicit  -93 "../src/tb_emac_top_jb.vhd"
+vsim -t 1ps   -lib work tb_emac_top_jb
+view wave
+do {tb_emac_top_jb.wdo}
+view structure
+view signals
+
+run 16000 us

lib/emac/sim/tb_emac_top_jb.wdo

@@ -0,0 +1,236 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Ethernet MAC}
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/ram64
+add wave -noupdate -divider Slave
+add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/sel_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/we_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/ack_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/srdy_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
+add wave -noupdate -divider Master
+add wave -noupdate -format Logic /tb_emac_top_jb/cyc_o
+add wave -noupdate -format Logic /tb_emac_top_jb/stb_o
+add wave -noupdate -format Logic /tb_emac_top_jb/we_o
+add wave -noupdate -format Literal /tb_emac_top_jb/sel_o
+add wave -noupdate -format Logic /tb_emac_top_jb/ack_i
+add wave -noupdate -format Logic /tb_emac_top_jb/mrdy_o
+add wave -noupdate -format Logic /tb_emac_top_jb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/addr_o
+add wave -noupdate -format Literal /tb_emac_top_jb/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/mdat_o
+add wave -noupdate -divider MII
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_rx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_tx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
+add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
+add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
+add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
+add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
+add wave -noupdate -divider {Packet generator}
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
+add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
+add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
+add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
+add wave -noupdate -divider RX-DMA
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_req
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_gnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_start
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_active
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_end
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rw
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_start
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_num_xfers
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_auto_inc
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete_ack
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/s
+add wave -noupdate -divider RX
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
+add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_chk_ok
+add wave -noupdate -divider TX
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re_dly
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {15999470765 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461803096 ps} 0} {{Cursor 5} {10000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {379173 ps}

lib/emac/src/.directory_history

@@ -0,0 +1,8 @@
+VHDL/lib/emac/emac_jb.vhd
+VHDL/lib/emac/src/emac_jb.vhd
+VHDL/lib/emac/src/emac_jb.vhd
+
+VHDL/lib/emac/src/tb_emac_jb.vhd
+VHDL/lib/emac/src/tb_serdes.vhd
+VHDL/lib/emac/src/tb_serdes.vhd
+

lib/emac/src/emac_rx.vhd

@@ -16,7 +16,7 @@ ENTITY emac_rx IS
 	(
 		clk				: in  STD_LOGIC;
 		rst				: in  STD_LOGIC;
-		dout_vld		: out STD_LOGIC;
+		dout_re			: in  STD_LOGIC;
 		dout			: out unsigned(31 downto 0);
 		ctrl_in			: in  rx_ctrl_in_t;
 		ctrl_out		: out rx_ctrl_out_t;
@@ -47,6 +47,7 @@ ARCHITECTURE behavior OF emac_rx IS
 	signal reset_en			: std_logic;
 	
 	signal host_ptr			: word_ptr_t;
+	signal host_ptr_next	: word_ptr_t;
 	signal host_ram_limit	: word_ptr_t;
 	signal host_ram_base	: word_ptr_t;
 
@@ -143,7 +144,7 @@ begin
 	dout					<= ram_dout_b;
 
 	ram_en_b				<= '1';
-	ram_addr_b				<= host_ptr;
+	ram_addr_b				<= host_ptr_next;
 
 	ram_en_a				<= '1';
 	ram_din_a				<= sipo32_dout;
@@ -183,15 +184,16 @@ fill_pointer:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			dout_vld			<= ctrl_in.pkt_read_en;
 			if ctrl_in.pkt_req_en = '1' then
 				host_ptr		<= cmd_base_out;
-			elsif ctrl_in.pkt_read_en = '1' then
-				host_ptr		<= host_ptr + 1;
+			elsif dout_re = '1' then
+				host_ptr		<= host_ptr_next;
 			end if;
 		end if;
 	end process;	
 
+	host_ptr_next	<= host_ptr + 1 when dout_re = '1' else host_ptr;
+	
 ------------------------------------------------------------------
 -- Transfer stuff
 ------------------------------------------------------------------
@@ -444,7 +446,7 @@ inst_cmd_fifo: entity work.fifo_async
 		data_r		=>  cmd_fifo_dout
 	);
 
-inst_ram : entity work.dpram_1w1r
+inst_ram : entity work.dpram_1w1r2c_ro
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -452,8 +454,8 @@ inst_ram : entity work.dpram_1w1r
 	)
 	PORT MAP 
 	(
-		clka		=> mii_rx_clk,
-		clkb		=> clk,
+		clk_a		=> mii_rx_clk,
+		clk_b		=> clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,

lib/emac/src/emac_top_jb.vhd

@@ -5,6 +5,7 @@ use std.textio.all; --  Imports the standard textio package.
 
 use work.emac_types.all;
 use work.utils_pkg.all;
+use work.busmaster_types.all;
 
 ENTITY emac_top_jb IS
 	Generic
@@ -15,6 +16,7 @@ ENTITY emac_top_jb IS
 	);
 	Port
 	(
+		-- JBUS Slave
 		CLK_I		: in  STD_LOGIC;
 		RST_I		: in  STD_LOGIC;
 		INT_O		: out STD_LOGIC;
@@ -28,6 +30,20 @@ ENTITY emac_top_jb IS
 		ADDR_I		: in  unsigned(31 downto 0);
 		DAT_I		: in  unsigned(31 downto 0);
 		DAT_O		: out unsigned(31 downto 0);
+		
+		-- JBUS Master
+		ACK_I		: in std_logic;
+		SRDY_I		: in std_logic;
+		MDAT_I		: in unsigned(31 downto 0);
+		MDAT_O		: out unsigned(31 downto 0);
+		ADDR_O		: out unsigned(31 downto 0);
+		SEL_O		: out unsigned(3 downto 0);
+		WE_O		: out std_logic;
+		CYC_O		: out std_logic;
+		STB_O		: out std_logic;
+		MRDY_O		: out std_logic;
+		
+		-- MII
 		mii_rx_clk	: in  STD_LOGIC;
 		mii_rx_dv	: in  STD_LOGIC;
 		mii_rx_er	: in  STD_LOGIC;
@@ -45,6 +61,12 @@ END emac_top_jb;
 
 ARCHITECTURE behavior OF emac_top_jb IS
 
+	-- Constants
+	constant DMA_NUM_CHANNEL		: integer := 2;
+	constant DMA_CH_WRITE			: integer := 0;
+	constant DMA_CH_READ			: integer := 1;
+	constant DMA_RW_CONF			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
+
 	-- Signals for EMAC connections
 	signal tx_ctrl_in		: tx_ctrl_in_t;
 	signal tx_ctrl_out		: tx_ctrl_out_t;
@@ -55,7 +77,7 @@ ARCHITECTURE behavior OF emac_top_jb IS
 	signal rx_ctrl_out		: rx_ctrl_out_t;
 
 	signal rx_dout			: unsigned(31 downto 0);
-	signal rx_dout_vld		: std_logic;
+	signal rx_dout_re		: std_logic;
 	
 	signal rx_int_en		: std_logic;
 	signal tx_int_en		: std_logic;
@@ -66,13 +88,55 @@ ARCHITECTURE behavior OF emac_top_jb IS
 
 	signal read				: std_logic;
 	signal write			: std_logic;
-	signal data_read		: std_logic;
-	signal data_write		: std_logic;
+	signal rx_read_en_CPU	: std_logic;
+	signal rx_req_en_CPU	: std_logic;
+	signal rx_free_en_CPU	: std_logic;
+	signal tx_write_en_CPU	: std_logic;
 	signal reg_read			: std_logic;
 	signal reg_write		: std_logic;
 
 	signal reg_addr			: unsigned(3 downto 0);
 
+	-- DMA Controller
+	signal dma_master_req			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_master_gnt			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
+	signal dma_req_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_req_en				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
+	signal dma_req_addr_auto_inc	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
+	signal dma_req_addr				: array32_t;
+	signal dma_req_num_xfers		: array32_t;
+
+	signal dma_req_complete			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_req_complete_ack		: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
+
+	signal dma_start					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_active					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_end						: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_bus_cmd_cycle_finished	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_bus_cmd_cycle_en			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
+	signal dma_bus_cmd_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
+	signal dma_bus_cmd_we				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
+	type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t;
+	signal dma_bus_cmd					: array_bus_cmd_t;
+
+	-- Busmaster arbiter
+	signal	arb_idx					: natural range 0 to DMA_NUM_CHANNEL-1;
+
+	-- BUS Master controller
+	signal bus_din_re				: std_logic;
+	signal bus_cmd_cycle_finished	: std_logic;
+	signal bus_cmd_cycle_en			: std_logic := '0';
+	signal bus_cmd_rdy				: std_logic;
+	signal bus_cmd_we				: std_logic := '0';
+	signal bus_cmd					: bm_cmd_t;
+	signal bus_din_rdy				: std_logic;
+	signal bus_din_vld				: std_logic := '0';
+	signal bus_din					: unsigned(31 downto 0) := (others => '-');
+	signal bus_dout					: unsigned(31 downto 0);
+	signal bus_dout_vld				: std_logic;
+	signal bus_dout_re				: std_logic := '0';
+	
 begin
 
 	mii_gtx_clk				<= '0';
@@ -80,18 +144,29 @@ begin
 	SRDY_O					<= CYC_I and ready;
 	read					<= STB_I and CYC_I and not WE_I;
 	write					<= STB_I and CYC_I and WE_I;
-	data_read				<= read and ADDR_I(15);
-	data_write				<= write and ADDR_I(15);
+	rx_read_en_CPU			<= read and ADDR_I(15);
+	tx_write_en_CPU			<= write and ADDR_I(15);
 	reg_read				<= read and not ADDR_I(15);
 	reg_write				<= write and not ADDR_I(15);
 	reg_addr				<= ADDR_I(5 downto 2);
 
 	ready					<= not tx_ctrl_in.pkt_alloc_en;
 	
-	tx_din_vld				<= data_write;
+	tx_din_vld				<= tx_write_en_CPU;
 	tx_din					<= DAT_I;
 
-	rx_ctrl_in.pkt_read_en	<= data_read;
+	rx_ctrl_in.pkt_free_en	<= rx_free_en_CPU or dma_end(0);
+	rx_ctrl_in.pkt_req_en	<= rx_req_en_CPU or dma_start(0);
+
+	rx_dout_re				<= rx_read_en_CPU or (dma_active(DMA_CH_WRITE) and bus_din_rdy);
+	
+	bus_din					<= rx_dout;
+	bus_din_vld				<= dma_active(DMA_CH_WRITE);
+	dma_master_gnt(0)		<= SRDY_I;
+	dma_req_en(0)			<= rx_ctrl_out.pkt_avail;
+	dma_req_num_xfers(0)	<= X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) when rx_ctrl_out.rx_size(1 downto 0) = "00" else X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) + 1;
+	dma_req_addr(0)			<= X"00000800";
+	dma_req_addr_auto_inc	<= "11";
 	
 ------------------------------------------------------------------
 registers_write: 
@@ -101,8 +176,8 @@ registers_write:
 			tx_ctrl_in.pkt_alloc_en		<= '0';
 			tx_ctrl_in.pkt_commit_en	<= '0';
 			tx_ctrl_in.reset			<= '0';
-			rx_ctrl_in.pkt_free_en		<= '0';
-			rx_ctrl_in.pkt_req_en		<= '0';
+			rx_free_en_CPU				<= '0';
+			rx_req_en_CPU				<= '0';
 			rx_ctrl_in.reset			<= '0';
 			if RST_I = '1' then
 				rx_int_en				<= '0';
@@ -125,8 +200,8 @@ registers_write:
 					rx_ctrl_in.Gbps_en			<= DAT_I(30);
 					rx_ctrl_in.fcs_chk_en		<= DAT_I(29);
 					rx_ctrl_in.promiscious		<= DAT_I(23);
-					rx_ctrl_in.pkt_req_en		<= DAT_I(17);
-					rx_ctrl_in.pkt_free_en		<= DAT_I(16);
+					rx_req_en_CPU				<= DAT_I(17);
+					rx_free_en_CPU				<= DAT_I(16);
 					rx_int_en					<= DAT_I(4);
 
 				-- 0x0004
@@ -177,7 +252,7 @@ registers_read:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			ACK_O					<= rx_dout_vld;
+			ACK_O					<= rx_read_en_CPU;
 			DAT_O					<= rx_dout;
 			if reg_read = '1' then
 				
@@ -266,7 +341,7 @@ inst_emac_rx : entity work.emac_rx
 	(
 		clk			=> CLK_I,
 		rst			=> RST_I,
-		dout_vld	=> rx_dout_vld,
+		dout_re		=> rx_dout_re,
 		dout		=> rx_dout,
 		ctrl_in		=> rx_ctrl_in,
 		ctrl_out	=> rx_ctrl_out,
@@ -301,5 +376,128 @@ inst_emac_tx : entity work.emac_tx
 		
 	);
 
+gen_dmac:
+for i in 0 to DMA_NUM_CHANNEL-1 generate
+	
+	dma_bus_cmd_cycle_finished(i)	<= bus_cmd_cycle_finished;
+	dma_bus_cmd_rdy(i) 				<= bus_cmd_rdy;
+
+	inst_dmac : entity work.dmac
+	Generic map
+	(
+		DATA_WIDTH			=> 32,
+		XFER_CHUNK_SIZE		=> 32
+	)
+	Port map
+	(
+		clk					=> CLK_I,
+		rst					=> RST_I,
+
+		master_req			=> dma_master_req(i),
+		master_gnt			=> dma_master_gnt(i),
+
+		req_rdy				=> dma_req_rdy(i),
+		req_en				=> dma_req_en(i),
+		req_rw				=> DMA_RW_CONF(i),
+		req_addr_auto_inc	=> dma_req_addr_auto_inc(i),
+		req_addr_start		=> dma_req_addr(i),
+		req_num_xfers		=> dma_req_num_xfers(i),
+
+		req_complete		=> dma_req_complete(i),
+		req_complete_ack	=> dma_req_complete_ack(i),
+
+		dma_start			=> dma_start(i),
+		dma_active			=> dma_active(i),
+		dma_end				=> dma_end(i),
+
+		-- busmaster control
+		bus_cyc_complete	=> dma_bus_cmd_cycle_finished(i),
+		bus_cmd_rdy			=> dma_bus_cmd_rdy(i),
+		bus_cmd_we			=> dma_bus_cmd_we(i),
+		bus_cmd_cycle_en	=> dma_bus_cmd_cycle_en(i),
+
+		-- busmaster command
+		bus_cmd_out			=> dma_bus_cmd(i)
+	);
+
+end generate;
+
+inst_busmaster_sync : entity work.busmaster_sync
+	GENERIC MAP
+	(
+		DATA_WIDTH					=> 32,
+		FIFO_DEPTH					=> 4
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST_I,
+		clk					=> CLK_I,
+
+		cmd_cycle_finished	=> bus_cmd_cycle_finished,
+		cmd_cycle_en		=> bus_cmd_cycle_en,
+		
+		cmd_rdy				=> bus_cmd_rdy,
+		cmd_we				=> bus_cmd_we,
+		cmd_in				=> bus_cmd,
+		
+		din_rdy				=> bus_din_rdy,
+		din_we				=> bus_din_vld,
+		din					=> bus_din,
+
+		dout				=> bus_dout,
+		dout_vld			=> bus_dout_vld,
+		dout_re				=> bus_dout_re,
+
+		-- JBUS Master signals
+		CYC_O				=> CYC_O,
+		STB_O				=> STB_O,
+		WE_O				=> WE_O,
+		SEL_O				=> SEL_O,
+		ACK_I				=> ACK_I,
+		SRDY_I				=> SRDY_I,
+		MRDY_O				=> MRDY_O,
+		ADDR_O				=> ADDR_O,
+		MDAT_I				=> MDAT_I,
+		MDAT_O				=> MDAT_O
+	);
+
+arbiter_proc:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				dma_master_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif dma_master_req(arb_idx) = '0' then
+				if arb_idx /= DMA_NUM_CHANNEL-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				dma_master_gnt	<= (others => '0');
+				dma_master_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+
+arbiter_mux:
+	process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
+	variable v_bus_cmd_we : std_logic;
+	variable v_bus_cmd_cycle_en : std_logic;
+	begin
+		v_bus_cmd_we := '0';
+		v_bus_cmd_cycle_en := '0';
+		for i in 0 to DMA_NUM_CHANNEL-1 loop
+			v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
+			v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
+			if dma_master_gnt(i) = '1' then
+				bus_cmd <= dma_bus_cmd(i);
+			end if;
+		end loop;
+		bus_cmd_we <= v_bus_cmd_we;
+		bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
+end process;
 
 end behavior;

lib/emac/src/emac_tx.vhd

@@ -562,7 +562,7 @@ xfer_state:
 	end process;
 
 ------------------------------------------------------------------
-inst_ram : entity work.dpram_1w1r
+inst_ram : entity work.dpram_1w1r2c_ro
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -570,8 +570,8 @@ inst_ram : entity work.dpram_1w1r
 	)
 	PORT MAP 
 	(
-		clka		=> clk,
-		clkb		=> mii_tx_clk,
+		clk_a		=> clk,
+		clk_b		=> mii_tx_clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,

lib/emac/src/emac_types.vhd

@@ -36,7 +36,6 @@ package emac_types is
 		Gbps_en				: std_logic;
 		reset				: std_logic;
 		fcs_chk_en			: std_logic;
-		pkt_read_en			: std_logic;
 		pkt_req_en			: std_logic;
 		pkt_free_en			: std_logic;
 		mac_addr			: mac_addr_t;

lib/emac/src/shifter.vhd

@@ -0,0 +1,111 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY shifter IS
+	Generic
+	(
+		data_width		: natural := 32;
+		aggregate_size	: natural := 8;
+		do_pipelined	: boolean := true
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		sa			: in  integer;
+		din_vld		: in  STD_LOGIC;
+		din			: in  unsigned(data_width-1 downto 0);
+		dout_vld	: out STD_LOGIC;
+		dout		: out unsigned(data_width-1 downto 0)
+		
+	);
+END shifter;
+
+ARCHITECTURE behavior OF shifter IS
+
+	constant num_rounds	: natural := NextExpBaseTwo(data_width/aggregate_size);
+	subtype sa_rnd_t is signed(num_rounds-1 downto 0);
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to num_rounds) of word_t;
+
+	signal rot_data			: word_array_t;
+	signal sa_rnd			: sa_rnd_t;
+
+	type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
+	signal sa_rnd_pipe		: sa_rnd_array_t;
+	signal dout_vld_pipe	: unsigned(0 to num_rounds);
+	
+--------------------------------------------------------------------------
+function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
+	variable result : unsigned(x'range);
+	constant sa : natural := (2**stage_num) * size;
+	begin
+	if en = '1' then
+		result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
+	else
+		result := x;
+	end if;	
+	return result;
+end rol_stage;
+
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+gen_non_pipelined:
+if do_pipelined = false generate
+begin
+	
+	rot_data(0)		<= din;
+	
+gen_rotate_right:
+	for stage in 0 to num_rounds-1 generate
+	begin
+		rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
+	end generate;
+	
+	sa_rnd			<= to_signed(sa, num_rounds);
+	dout			<= rot_data(num_rounds);
+	dout_vld		<= din_vld;
+	
+end generate;
+	
+--------------------------------------------------------------------------
+gen_pipelined:
+if do_pipelined = true generate
+begin
+	
+	rot_data(0)			<= din;
+	sa_rnd_pipe(0)		<= to_signed(sa, num_rounds);
+	dout_vld_pipe(0)	<= din_vld;
+	
+gen_rotate_right:
+	for stage in 0 to num_rounds-1 generate
+	begin
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					dout_vld_pipe(stage+1)	<= '0';
+				else
+					dout_vld_pipe(stage+1)	<= dout_vld_pipe(stage);
+					if dout_vld_pipe(stage) = '1' then
+						sa_rnd_pipe(stage+1)	<= sa_rnd_pipe(stage);
+						rot_data(stage+1)		<= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
+					end if;
+				end if;
+			end if;
+		end process;
+	end generate;
+	
+	dout			<= rot_data(num_rounds);
+	dout_vld		<= dout_vld_pipe(num_rounds);
+	
+end generate;
+
+--------------------------------------------------------------------------
+end behavior;

lib/emac/src/tb_crc32.vhd

@@ -0,0 +1,106 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_crc32 IS
+END tb_crc32;
+
+ARCHITECTURE behavior OF tb_crc32 IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+
+	signal din_vld			: std_logic := '0';
+	signal din				: unsigned(7 downto 0) := (others => '-');
+	signal crc32			: unsigned(31 downto 0);
+	signal crc32_vld		: std_logic;
+
+
+	type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
+	
+	signal test_data : byte_array_t :=
+	(
+		X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
+		X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
+		X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
+		X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
+		X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
+		X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
+		X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
+		X"0E", X"0F", X"10", X"11", X"12", X"13"
+	);
+	
+BEGIN
+
+inst_crc32: entity work.crc32
+	PORT MAP
+	(
+		rst				=> RST,
+		clk				=> CLK,
+		din_vld			=> din_vld,
+		din				=> din,
+		crc32_vld		=> crc32_vld,
+		crc32_out		=> crc32
+		
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+
+-- Master
+STIMULUS: process
+
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST <= '0';
+		wait for 6*CLK_PERIOD;
+
+		wait until rising_edge(CLK);
+
+		for i in 0 to 61 loop
+			din_vld	<= '1';
+			din		<= test_data(i);
+			wait until rising_edge(CLK);
+		end loop;
+
+		din		<= (others => '-');
+		din_vld	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;

lib/emac/src/tb_emac_jb.vhd

@@ -0,0 +1,224 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_serdes IS
+END tb_serdes;
+
+ARCHITECTURE behavior OF tb_serdes IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+
+	signal piso_din_vld		: std_logic := '0';
+	signal piso_din_rdy		: std_logic;
+	signal piso_din_be		: unsigned(3 downto 0) := (others => '0');
+	signal piso_din			: unsigned(31 downto 0) := (others => '-');
+	signal piso_dout_vld	: std_logic;
+	signal piso_dout		: unsigned(7 downto 0);
+	signal piso_dout_en		: std_logic;
+
+	signal piso2_din_vld	: std_logic := '0';
+	signal piso2_din_rdy	: std_logic;
+	signal piso2_din_be		: unsigned(1 downto 0) := (others => '1');
+	signal piso2_din		: unsigned(7 downto 0) := (others => '-');
+	signal piso2_dout_vld	: std_logic;
+	signal piso2_dout		: unsigned(3 downto 0);
+	signal piso2_dout_en	: std_logic;
+
+	signal sipo_enable		: std_logic := '0';
+	signal sipo_rst			: std_logic := '0';
+	signal sipo_din_vld		: std_logic := '0';
+	signal sipo_din			: unsigned(7 downto 0) := (others => '-');
+	signal sipo_dout_vld	: std_logic;
+	signal sipo_dout_en		: std_logic;
+	signal sipo_dout_be		: unsigned(3 downto 0);
+	signal sipo_dout		: unsigned(31 downto 0);
+
+	signal sipo2_enable		: std_logic := '0';
+	signal sipo2_rst		: std_logic := '0';
+	signal sipo2_din_vld	: std_logic := '0';
+	signal sipo2_din		: unsigned(3 downto 0) := (others => '-');
+	signal sipo2_dout_vld	: std_logic;
+	signal sipo2_dout_en	: std_logic;
+	signal sipo2_dout_be	: unsigned(1 downto 0);
+	signal sipo2_dout		: unsigned(7 downto 0);
+
+	
+BEGIN
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		din_vld		=> piso_din_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> piso_din_be,
+		din			=> piso_din,
+		dout_vld	=> piso_dout_vld,
+		dout_en		=> piso_dout_en,
+		dout		=> piso_dout
+		
+	);
+
+	piso_dout_en	<= piso2_din_rdy;
+	
+inst_piso2 : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 4,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		din_vld		=> piso2_din_vld,
+		din_rdy		=> piso2_din_rdy,
+		din_be		=> piso2_din_be,
+		din			=> piso2_din,
+		dout_vld	=> piso2_dout_vld,
+		dout_en		=> piso2_dout_en,
+		dout		=> piso2_dout
+		
+	);
+
+	piso2_din_vld	<= piso_dout_vld;
+	piso2_dout_en	<= '1';
+	piso2_din		<= piso_dout;
+	
+inst_sipo : entity work.sipo
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 32,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		din_en		=> sipo_enable,
+		din_vld		=> sipo_din_vld,
+		din			=> sipo_din,
+		dout_be		=> sipo_dout_be,
+		dout_vld	=> sipo_dout_vld,
+		dout		=> sipo_dout,
+		dout_en		=> sipo_dout_en
+		
+	);
+	sipo_din		<= sipo2_dout;
+	sipo_din_vld	<= sipo2_dout_vld;
+	sipo_enable		<= sipo2_dout_en;
+	sipo_rst		<= RST or not piso2_dout_vld;
+
+inst_sipo2 : entity work.sipo
+	GENERIC MAP
+	(
+		data_width_in	=> 4,
+		data_width_out	=> 8,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		din_en		=> sipo2_enable,
+		din_vld		=> sipo2_din_vld,
+		din			=> sipo2_din,
+		dout_be		=> sipo2_dout_be,
+		dout_vld	=> sipo2_dout_vld,
+		dout		=> sipo2_dout,
+		dout_en		=> sipo2_dout_en
+		
+	);
+	sipo2_din		<= piso2_dout;
+	sipo2_din_vld	<= piso2_dout_vld;
+	sipo2_enable	<= sipo2_din_vld;
+	sipo_rst		<= RST or not piso2_dout_vld;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+
+-- Master
+STIMULUS: process
+
+
+	begin
+
+		wait for 600*CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+
+		for i in 1 to 10 loop
+
+			wait until rising_edge(CLK);
+			piso_din_vld	<= '1';
+			piso_din		<= X"12345678";
+			piso_din_be		<= "1111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "1111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "1111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "1100";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= (others => '-');
+			piso_din_vld	<= '0';
+
+
+			wait until rising_edge(CLK) and piso_dout_vld = '0';
+
+--			wait until rising_edge(CLK);
+--			wait until rising_edge(CLK) and sipo_dout_vld = '1';
+--
+			wait for 33*CLK_PERIOD;
+		
+		end loop;
+		
+		wait; 
+	
+	end process;
+	
+END;

lib/emac/src/tb_emac_top_jb.vhd

@@ -0,0 +1,761 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_emac_top_jb IS
+END tb_emac_top_jb;
+
+ARCHITECTURE behavior OF tb_emac_top_jb IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+	constant MII_CLK_PERIOD	: time := 37.7 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+
+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_O			: std_logic;
+	signal INT_O			: std_logic;
+	signal MRDY_I			: std_logic := '0';
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O_reg		: unsigned(31 downto 0) := (others => '-');
+	signal status_reg		: unsigned(31 downto 0) := (others => '0');
+	signal size_reg			: unsigned(31 downto 0) := (others => '0');
+
+	-- Master
+	signal CYC_O					: std_logic;
+	signal STB_O					: std_logic;
+	signal WE_O						: std_logic;
+	signal SEL_O					: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I					: std_logic := '0';
+	signal MRDY_O					: std_logic := '1';
+	signal SRDY_I					: std_logic := '1';
+	signal ADDR_O					: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I					: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_O					: unsigned(31 downto 0) := (others => '-');
+
+	-- MII signals
+	signal mii_rx_clk_board	: std_logic := '1';
+	signal mii_tx_clk_board	: std_logic := '1';
+	signal mii_rx_clk		: std_logic := '1';
+	signal mii_tx_clk		: std_logic := '1';
+	signal mii_rx			: unsigned(7 downto 0) := (others => '-');
+	signal mii_tx			: unsigned(7 downto 0);
+	signal mii_rx_dv		: std_logic := '0';
+	signal mii_rx_er		: std_logic := '0';
+	signal mii_tx_en		: std_logic;
+	signal mii_tx_er		: std_logic;
+	signal mii_crs			: std_logic := '0';
+	signal mii_col			: std_logic := '0';
+	signal mii_gtx_clk		: std_logic;
+
+	signal loop_back_en		: std_logic := '0';
+	
+	signal pktgen_tx		: unsigned(7 downto 0);
+	signal pktgen_tx_en		: std_logic;
+	signal pktgen_tx_er		: std_logic;
+	signal pktgen_en		: std_logic := '0';
+	signal pktgen_gigabit	: std_logic := '0';
+	signal pktgen_fcs_en	: std_logic := '0';
+	signal dat_o_cnt_en		: std_logic := '0';
+	signal dat_o_cnt_rst	: std_logic := '1';
+	signal dat_o_cnt		: natural;
+	signal pkt_count		: natural;
+	
+	type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
+	signal emac_action	: emac_action_t;
+	
+	constant RX_STATUS_REG_ADDR	: unsigned(31 downto 0) := X"0000_0000";
+	constant RX_SIZE_REG_ADDR	: unsigned(31 downto 0) := X"0000_0004";
+	constant TX_STATUS_REG_ADDR	: unsigned(31 downto 0) := X"0000_0008";
+	constant TX_SIZE_REG_ADDR	: unsigned(31 downto 0) := X"0000_000C";
+	constant DATA_REG_ADDR		: unsigned(31 downto 0) := X"0000_8000";
+
+
+	-- 64Bit RAM
+	signal MDAT_I_64				: unsigned(63 downto 0) := (others => '-');
+	signal MDAT_O_64				: unsigned(63 downto 0) := (others => '-');
+
+	type ram_t  is array (0 to 511) of unsigned(63 downto 0);
+
+	signal ram64		: ram_t;
+
+	
+BEGIN
+
+	MDAT_I	<= MDAT_I_64(31 downto 0);
+	MDAT_O_64	<= MDAT_O & MDAT_O;
+
+	process(CLK)
+	variable res: unsigned(63 downto 0);
+	variable ram_data : unsigned(63 downto 0);
+	variable data8: unsigned(7 downto 0);
+	begin
+		if rising_edge(CLK) then
+			if RST = '1' then
+					data8 := X"00";
+				for i in 0 to 255 loop
+					ram_data(7 downto 0)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(15 downto 8)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(23 downto 16)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(31 downto 24)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(39 downto 32)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(47 downto 40)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(55 downto 48)	:= data8;
+					data8				:= data8 + 1;
+					ram_data(63 downto 56)	:= data8;
+					data8				:= data8 + 1;
+					ram64(i) <= ram_data;
+				end loop;
+			else
+				ACK_I	<= '0';
+				if (CYC_O and STB_O) = '1' then
+					if WE_O = '0' then
+						ACK_I	<= '1';
+						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
+						if ADDR_O(2) = '0' then
+							res			:= ram_data;
+						else
+							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
+						end if;
+					else -- WE=1
+						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
+					--	ram_data := (others => '-');
+						if ADDR_O(2) = '0' then
+							if SEL_O = "11111111" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
+							elsif SEL_O = "00001111" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
+							elsif SEL_O = "11110000" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
+							end if;
+						else
+							if SEL_O = "11111111" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
+							elsif SEL_O = "00001111" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
+							elsif SEL_O = "11110000" then
+								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
+							end if;
+						end if;
+					end if;
+				end if;
+				MDAT_I_64	<= res;
+			end if;
+		end if;
+	end process;
+
+inst_emac_top_jb : entity work.emac_top_jb
+	GENERIC MAP
+	(
+		f_sysclk	=> 100.0,
+		RX_RAM_SIZE	=> 2048,
+		TX_RAM_SIZE	=> 2048
+	)
+	PORT MAP
+	(
+		-- JBUS Slave signals
+		CLK_I		=> CLK,
+		RST_I		=> RST,
+		INT_O		=> INT_O,
+		CYC_I		=> CYC_I,
+		STB_I		=> STB_I,
+		SEL_I		=> SEL_I,
+		WE_I		=> WE_I,
+		ACK_O		=> ACK_O,
+		SRDY_O		=> SRDY_O,
+		MRDY_I		=> MRDY_I,
+		ADDR_I		=> ADDR_I,
+		DAT_I		=> DAT_I,
+		DAT_O		=> DAT_O,
+		
+		-- JBUS Master signals
+		CYC_O		=> CYC_O,
+		STB_O		=> STB_O,
+		WE_O		=> WE_O,
+		SEL_O		=> SEL_O,
+		ACK_I		=> ACK_I,
+		SRDY_I		=> SRDY_I,
+		MRDY_O		=> MRDY_O,
+		ADDR_O		=> ADDR_O,
+		MDAT_I		=> MDAT_I,
+		MDAT_O		=> MDAT_O,
+		
+		mii_rx_clk	=> mii_rx_clk_board,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx,
+		mii_gtx_clk	=> mii_gtx_clk,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+inst_pkt_gen : entity work.pkt_gen
+	GENERIC MAP
+	(
+		f_sysclk		=> 100.0,
+		PKT_SIZE_MIN	=> 64,
+		PKT_SIZE_MAX	=> 1512
+		
+	)
+	PORT MAP
+	(
+		clk			=> CLK,
+		rst			=> RST,
+		en			=> pktgen_en,
+		gigabit_en	=> pktgen_gigabit,
+		fcs_gen_en	=> pktgen_fcs_en,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> pktgen_tx_en,
+		mii_tx_er	=> pktgen_tx_er,
+		mii_tx		=> pktgen_tx
+		
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+MII_CLK_GEN: process
+	begin
+		wait for MII_CLK_PERIOD/2;
+		mii_rx_clk <= not mii_rx_clk;
+		mii_tx_clk <= not mii_tx_clk;
+	end process;
+
+	mii_rx_clk_board <= mii_rx_clk;
+	mii_tx_clk_board <= mii_tx_clk;
+
+DAT_O_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if ACK_O = '1' then
+				DAT_O_reg	<= DAT_O;
+			end if;
+		end if;
+	end process;
+	
+DAT_O_count_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if dat_o_cnt_rst = '1' then
+				dat_o_cnt <= 0;
+			elsif ACK_O = '1' and dat_o_cnt_en = '1' then
+				dat_o_cnt	<= dat_o_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+	mii_rx		<= mii_tx when loop_back_en = '1' else pktgen_tx;
+	mii_rx_dv	<= mii_tx_en when loop_back_en = '1' else pktgen_tx_en;
+	mii_rx_er	<= mii_tx_er when loop_back_en = '1' else pktgen_tx_er;
+	mii_crs		<= '0';
+	mii_col		<= '0';
+	
+-- Master
+STIMULUS: process
+
+	procedure emac_tx_reset_100mbps  is
+	begin
+	
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"A000_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= TX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+	end procedure emac_tx_reset_100mbps;
+
+	procedure emac_rx_reset_100mbps  is
+	begin
+	
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"A000_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+	end procedure emac_rx_reset_100mbps;
+
+	procedure emac_tx_reset_1000mbps  is
+	begin
+	
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"E000_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= TX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+	end procedure emac_tx_reset_1000mbps;
+
+	procedure emac_rx_reset_1000mbps  is
+	begin
+	
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"E000_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+	end procedure emac_rx_reset_1000mbps;
+
+	procedure emac_alloc (size : natural) is
+	begin
+	
+		-- TX-ALLOCATION
+		-- set TX-size
+		emac_action	<= emac_alloc;
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= to_unsigned(size, 32);
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= TX_SIZE_REG_ADDR;
+
+	check_alloc_ok:
+		while(true) loop
+
+			-- set alloc request
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			WE_I	<= '0';
+			STB_I	<= '1';
+			ADDR_I	<= TX_STATUS_REG_ADDR;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '0';
+			wait until rising_edge(CLK) and ACK_O = '1';
+			status_reg	<= DAT_O;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			DAT_I	<= X"0002_0000" or (not X"0001_0000" and status_reg);
+			STB_I	<= '1';
+			WE_I	<= '1';
+			ADDR_I	<= TX_STATUS_REG_ADDR;
+
+		check_bsy:
+			while (true) loop
+				wait until rising_edge(CLK) and SRDY_O = '1';
+				WE_I	<= '0';
+				STB_I	<= '1';
+				ADDR_I	<= TX_STATUS_REG_ADDR;
+				wait until rising_edge(CLK) and SRDY_O = '1';
+				STB_I	<= '0';
+				wait until rising_edge(CLK) and ACK_O = '1';
+				status_reg	<= DAT_O;
+				wait until rising_edge(CLK);
+				if status_reg(17) = '0' then
+					exit check_bsy;
+				end if;
+			end loop;
+			if status_reg(16) = '1' then
+				exit check_alloc_ok;
+			end if;
+		end loop;
+		CYC_I	<= '0';
+		
+		emac_action	<= emac_idle;
+
+	end procedure emac_alloc;
+	
+	procedure emac_commit  is
+	begin
+	
+		-- RX- DEALLOCATION
+		emac_action	<= emac_commit;
+
+		-- set free request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		WE_I	<= '0';
+		STB_I	<= '1';
+		ADDR_I	<= TX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and ACK_O = '1';
+		status_reg	<= DAT_O;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0001_0000" or (not X"0002_0000" and status_reg);
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= TX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_commit;
+
+	procedure emac_write (size : natural) is
+	variable data : unsigned (7 downto 0);
+	variable num_words : natural;
+	begin
+
+		-- FILL TX data
+		emac_action	<= emac_write;
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		data	:= X"00";
+		ADDR_I	<= DATA_REG_ADDR;
+		WE_I	<= '1';
+		for i in 1 to num_words loop
+			STB_I	<= '1';
+			DAT_I(7 downto 0)	<= data;
+			data				:= data + 1;
+			DAT_I(15 downto 8)	<= data;
+			data				:= data + 1;
+			DAT_I(23 downto 16)	<= data;
+			data				:= data + 1;
+			DAT_I(31 downto 24)	<= data;
+			data				:= data + 1;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+
+ 		emac_commit;
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_write;
+
+	procedure emac_read (size_in : natural) is
+	variable data : unsigned (7 downto 0);
+	variable size, num_words : natural;
+	begin
+
+		return;
+		emac_action	<= emac_wait_data;
+
+		-- check if data available
+	check_data_avail:
+		while (true) loop
+			CYC_I	<= '1';
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			WE_I	<= '0';
+			STB_I	<= '1';
+			ADDR_I	<= RX_STATUS_REG_ADDR;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '0';
+			wait until rising_edge(CLK) and ACK_O = '1';
+			status_reg	<= DAT_O;
+			wait until rising_edge(CLK);
+			if status_reg(17) = '1' and status_reg(16) = '1' then
+				exit check_data_avail;
+			end if;
+		end loop;
+
+	read_size:
+		dat_o_cnt_rst <= '1';
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		WE_I	<= '0';
+		STB_I	<= '1';
+		ADDR_I	<= RX_SIZE_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and ACK_O = '1';
+		size_reg	<= DAT_O;
+		wait until rising_edge(CLK);
+
+		-- set packet request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		WE_I	<= '0';
+		STB_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and ACK_O = '1';
+		status_reg	<= DAT_O;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0002_0000" or (not X"0001_0000" and status_reg);
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_read;
+		-- Read RX data
+		size := size_in;
+		if (size_in = 0) then
+			size	:= to_integer(size_reg(15 downto 0));
+		end if;
+		
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		dat_o_cnt_rst <= '0';
+		dat_o_cnt_en <= '1';
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		ADDR_I	<= DATA_REG_ADDR;
+		WE_I	<= '0';
+		STB_I	<= '1';
+		for i in 1 to num_words loop
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and dat_o_cnt = num_words;
+		dat_o_cnt_en <= '0';
+		emac_action	<= emac_idle;
+
+	end procedure emac_read;
+
+	procedure emac_free  is
+	begin
+	
+		return;
+		-- RX- DEALLOCATION
+		emac_action	<= emac_free;
+
+		-- set free request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		WE_I	<= '0';
+		STB_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and ACK_O = '1';
+		status_reg	<= DAT_O;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0001_0000" or (not X"0002_0000" and status_reg);
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= RX_STATUS_REG_ADDR;
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_free;
+
+	begin
+
+		wait for 6*MII_CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+		emac_rx_reset_100mbps;
+		emac_tx_reset_100mbps;
+		pktgen_gigabit	<= '0';
+		pktgen_fcs_en	<= '1';
+		wait for 60*CLK_PERIOD;
+		
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+
+		for i in 1 to 10 loop
+			for j in 1 to 100 loop
+		 		emac_alloc (72);
+		 		emac_write (72);
+			end loop;
+			wait for 1 ms;
+		end loop;
+		
+		wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
+		wait for 6000*CLK_PERIOD;
+		
+		loop_back_en	<= '1';
+		
+ 		emac_alloc (74);
+ 		emac_write (74);
+ 
+ 		emac_alloc (105);
+ 		emac_write (105);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (103);
+ 		emac_write (103);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (71);
+ 		emac_write (71);
+ 
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (82);
+ 		emac_write (82);
+
+ 		emac_alloc (86);
+ 		emac_write (86);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (77);
+ 		emac_write (77);
+
+ 		emac_alloc (99);
+ 		emac_write (99);
+
+ 		emac_alloc (65);
+ 		emac_write (65);
+
+ 		emac_alloc (321);
+ 		emac_write (321);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (1111);
+ 		emac_write (1111);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (73);
+ 		emac_write (73);
+
+ 		emac_alloc (107);
+ 		emac_write (107);
+
+ 		emac_alloc (83);
+ 		emac_write (83);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (72);
+ 		emac_write (72);
+
+ 		emac_alloc (1003);
+ 		emac_write (1003);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		wait for 6000*CLK_PERIOD;
+
+		loop_back_en	<= '0';
+		pktgen_en		<= '1';
+		pkt_count		<= 0;
+		for i in 1 to 500 loop
+			wait for 1 us;
+			emac_read (0);
+			emac_free;
+			pkt_count	<= pkt_count + 1;
+		end loop;
+		pktgen_en		<= '0';
+		emac_read (0);
+		emac_free;
+			
+
+		wait; 
+	
+	end process;
+	
+END;

lib/misc/dpram_1w1r.vhd

@@ -1,79 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r;
-
-architecture Behavioral of dpram_1w1r is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clka)
-begin
-if clka'event and clka = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clkb)
-begin
-if clkb'event and clkb = '1' then
-	if en_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-

lib/misc/dpram_2w2r.vhd

@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r;
-
-architecture Behavioral of dpram_2w2r is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-

lib/misc/utils_pkg.vhd

@@ -1,196 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package utils_pkg is
-	
-	-- Constants
-
-	-- Functions
-	function MIN (X, Y: INTEGER) return INTEGER;
-	function MAX (X, Y: INTEGER) return INTEGER;
-
-	function NextPowerOfTwo(x : real) return real;
-	function NextExpBaseTwo(x : real) return real;
-	function NextPowerOfTwo(x : natural) return natural;
-	function NextExpBaseTwo(x : natural) return natural;
-	function GCD(a, b : natural) return natural;
-	function LCM(a, b : natural) return natural;
-	function UTILS_PERIOD_NS(f_in_MHz : real) return real;
-	function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
-	function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
-	function f_correct(f : real) return natural;
-	
-end utils_pkg;
-
-
-package body utils_pkg is
-
-	-------------------------------------------------------------
-	function MIN (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y < X then
-		res := Y;
-	end if;
-
-	return res;
-
-	end MIN;
-
-	-------------------------------------------------------------
-	function MAX (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y > X then
-		res := Y;
-	end if;
-
-	return res;
-	
-	end MAX;
-
-	-------------------------------------------------------------
-	function NextExpBaseTwo(x : real) return real is
-	begin
-		return ceil(log2(x));
-	end NextExpBaseTwo;	
-	
-	-------------------------------------------------------------
-	function NextPowerOfTwo(x : real) return real is
-	begin
-
-		return 2.0**NextExpBaseTwo(x);
-	end NextPowerOfTwo;	
-
-	-------------------------------------------------------------
-	function NextExpBaseTwo(x : natural) return natural is
-	begin
-		return natural(NextExpBaseTwo(real(x)));
-	end NextExpBaseTwo;	
-	
-	-------------------------------------------------------------
-	function NextPowerOfTwo(x : natural) return natural is
-	begin
-
-		return 2**NextExpBaseTwo(x);
-	end NextPowerOfTwo;	
-	
-	-------------------------------------------------------------
-	function GCD(a, b : natural) return natural is
-	variable aa : natural;
-	variable bb : natural;
-	begin
-		aa := a;
-		bb := b;
-		while bb /= 0 loop
-			if aa > bb then
-				aa := aa - bb;
-			else
-				bb := bb - aa;
-			end if;
-		end loop;
-		
-		return aa;
-
-	end GCD;	
-
-	-------------------------------------------------------------
-	function LCM(a, b : natural) return natural is
-	begin
-
-		return (a * b)/GCD(a, b);
-
-	end LCM;	
-
-	-------------------------------------------------------------
-	function UTILS_PERIOD_NS(f_in_MHz : real) return real is
-	begin
-		
-		return 1.0E3/f_in_MHz;
-
-	end UTILS_PERIOD_NS;	
-	
-	-------------------------------------------------------------
-	function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
-	variable f_in  : natural;
-	variable f_out : natural;
-	variable C : natural;
-	variable M : natural;
-	variable D : natural;
-	begin
-		C := f_correct(f_out_MHz);
-		if C < 2 then
-			C := f_correct(f_in_MHz);
-		end if;
-
-		f_out := natural(ceil(real(C)*f_out_MHz));
-		f_in  := natural(ceil(real(C)*f_in_MHz));
-
-		M := LCM(f_in, f_out)/f_in;
-		D := f_in/GCD(f_in, f_out);
-
-		assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
-		if M = 1 then
-			M := 2;
-		end if;
-
-		return M;
-		
-	end UTILS_FREQ_M;	
-
-	-------------------------------------------------------------
-	function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
-	variable f_in  : natural;
-	variable f_out : natural;
-	variable C : natural;
-	variable M : natural;
-	variable D : natural;
-	begin
-		C := f_correct(f_out_MHz);
-		if C < 2 then
-			C := f_correct(f_in_MHz);
-		end if;
-
-		f_out := natural(ceil(real(C)*f_out_MHz));
-		f_in  := natural(ceil(real(C)*f_in_MHz));
-
-		M := LCM(f_in, f_out)/f_in;
-		D := f_in/GCD(f_in, f_out);
-
-		assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
-		if M = 1 then
-			D := 2*D;
-		end if;
-		
-		return D;
-
-	end UTILS_FREQ_D;	
-
-	-------------------------------------------------------------
-	function f_correct(f : real) return natural is
-	constant MAX_ITER	: positive	:= 100;
-	constant MAX_ERR	: real		:= 0.01;
-	variable fpart		: real;
-	variable err		: real;
-	begin
-		for i in 1 to MAX_ITER loop
-			fpart := real(i)*f - ceil(real(i)*f);
-			err := abs(fpart);
-			if err < max_err then
-				return i;
-			end if;
-		end loop;
-	end f_correct;	
-
-	-------------------------------------------------------------
-end utils_pkg;
-
-