Compare commits
2
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
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6277b516d0 | ||
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jens
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b6a0780463 |
@@ -1,4 +0,0 @@
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PACKAGE ALT_CUSP_PACKAGE IS
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END ALT_CUSP_PACKAGE;
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File diff suppressed because it is too large
Load Diff
@@ -1,689 +0,0 @@
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus II License Agreement,
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||||
-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-----------------------------------------------------------------------------
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-- --
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-- Description: Declares utility package for Altera IP support --
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-- --
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-- --
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-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
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-- --
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------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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--
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-- These routines are used to help SOPC Builder generate VHDL code.
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--
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-- ----------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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package altera_europa_support_lib is
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attribute IS_SIGNED : BOOLEAN ;
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attribute SYNTHESIS_RETURN : STRING ;
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FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of and'ing all of the bits of the vector.
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FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of nand'ing all of the bits of the vector.
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FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of or'ing all of the bits of the vector.
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FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of nor'ing all of the bits of the vector.
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FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of xor'ing all of the bits of the vector.
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FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
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-- Result subtype: STD_LOGIC.
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-- Result: Result of xnor'ing all of the bits of the vector.
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FUNCTION A_SRL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
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FUNCTION A_SLL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
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FUNCTION A_SRL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
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FUNCTION A_SLL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
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FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector;
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FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector;
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FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC;
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FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC;
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FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
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FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
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FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR) return Std_Logic;
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function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC;
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-- Result subtype: STD_LOGIC
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-- Result: Converts a BOOLEAN to a STD_LOGIC..
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FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
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FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
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function a_min(L, R: INTEGER) return INTEGER ;
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function a_max(L, R: INTEGER) return INTEGER ;
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FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR ;
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||||
-------------------------------------------------------
|
||||
-- Conversions for Verilog $display/$write emulation --
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-------------------------------------------------------
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||||
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-- All required padding is to the left of the value (right justified) to
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-- a string that can hold the maximum value of the vector in that radix.
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-- When displaying decimal values (e.g. %d), padding is spaces.
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-- When displaying other radices (e.g. %h), padding is zeros.
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-- There is no padding when a zero is placed after the % (e.g. %0d or %0h).
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type pad_type is (pad_none, pad_spaces, pad_zeros);
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function to_hex_string(val : std_logic_vector;
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pad : pad_type := pad_zeros) return string;
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function to_decimal_string(val : integer;
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pad : pad_type := pad_spaces) return string;
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function to_decimal_string(val : std_logic_vector;
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pad : pad_type := pad_spaces) return string;
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function to_octal_string(val : std_logic_vector;
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pad : pad_type := pad_zeros) return string;
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function to_binary_string(val : std_logic_vector;
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pad : pad_type := pad_zeros) return string;
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function to_hex_string(val : std_logic;
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pad : pad_type := pad_zeros) return string;
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function to_decimal_string(val : std_logic;
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pad : pad_type := pad_spaces) return string;
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function to_octal_string(val : std_logic;
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pad : pad_type := pad_zeros) return string;
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function to_binary_string(val : std_logic;
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pad : pad_type := pad_zeros) return string;
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end altera_europa_support_lib;
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package body altera_europa_support_lib is
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--
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-- Reducing logical functions.
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--
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FUNCTION and_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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-- Exemplar synthesis directive attributes for this function
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ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
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BEGIN
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result := '1';
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FOR i IN arg'RANGE LOOP
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result := result AND arg(i);
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END LOOP;
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RETURN result;
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END;
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FUNCTION nand_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
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BEGIN
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result := NOT and_reduce(arg);
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RETURN result;
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END;
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FUNCTION or_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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-- Exemplar synthesis directive attributes for this function
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ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ;
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BEGIN
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result := '0';
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FOR i IN arg'RANGE LOOP
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result := result OR arg(i);
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END LOOP;
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RETURN result;
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END;
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FUNCTION nor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NOR" ;
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BEGIN
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result := NOT or_reduce(arg);
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RETURN result;
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END;
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FUNCTION xor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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-- Exemplar synthesis directive attributes for this function
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ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ;
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BEGIN
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result := '0';
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FOR i IN arg'RANGE LOOP
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result := result XOR arg(i);
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END LOOP;
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RETURN result;
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END;
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FUNCTION xnor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
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VARIABLE result: STD_LOGIC;
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ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_XNOR" ;
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BEGIN
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result := NOT xor_reduce(arg);
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RETURN result;
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END;
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function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC is
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begin
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if(arg = true) then
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return('1');
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else
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return('0');
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end if;
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end;
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FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN(A_SRL(arg,conv_integer(shift)));
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END;
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FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN(A_SLL(arg,conv_integer(shift)));
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END;
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FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
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VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
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BEGIN
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IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
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IF (shift = 0) THEN
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result := arg;
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ELSE
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result(arg'LEFT - shift DOWNTO 0) := arg(arg'LEFT DOWNTO shift);
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END IF;
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END IF;
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||||
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RETURN(result);
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||||
END;
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||||
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FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
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VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
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BEGIN
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IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
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IF (shift = 0) THEN
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result := arg;
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ELSE
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result(arg'LEFT DOWNTO shift) := arg(arg'LEFT - shift DOWNTO 0);
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END IF;
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END IF;
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RETURN(result);
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END;
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FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector IS
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BEGIN
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IF a = '1' THEN
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return "1";
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ELSE
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return "0";
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END IF;
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END;
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FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector IS
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BEGIN
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return a;
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END;
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FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC IS
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BEGIN
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IF (select_arg) THEN
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return (then_arg);
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ELSE
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return (else_arg);
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END IF;
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END;
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FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC IS
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BEGIN
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IF (select_arg) THEN
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return (then_arg);
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ELSE
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return (else_arg);
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END IF;
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END;
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FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
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BEGIN
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IF (select_arg) THEN
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return (then_arg);
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ELSE
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return (else_arg);
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END IF;
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END;
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FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
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BEGIN
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IF (select_arg) THEN
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return (then_arg);
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ELSE
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return (else_arg);
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END IF;
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END;
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FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR)
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return Std_Logic IS
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BEGIN
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return (vector(vector'right));
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END;
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FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
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VARIABLE result : STD_LOGIC_VECTOR(repeat-1 DOWNTO 0) := (others => '0');
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VARIABLE i : integer := 0;
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BEGIN
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FOR i IN 0 TO (repeat-1) LOOP
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result(i) := arg;
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end LOOP;
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RETURN(result);
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END;
|
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FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
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VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
|
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VARIABLE result : STD_LOGIC_VECTOR(((repeat * (arg_copy'LEFT+1))-1) DOWNTO 0) := (others => '0');
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VARIABLE i : integer := 0;
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BEGIN
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FOR i IN 0 TO (repeat-1) LOOP
|
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result((((arg_copy'left + 1) * i) + arg_copy'left) downto ((arg_copy'left + 1) * i)) := arg_copy(arg_copy'LEFT DOWNTO 0);
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end LOOP;
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RETURN(result);
|
||||
END;
|
||||
|
||||
-- a_min : return the minimum of two integers;
|
||||
function a_min(L, R: INTEGER) return INTEGER is
|
||||
begin
|
||||
if L < R then
|
||||
return L;
|
||||
else
|
||||
return R;
|
||||
end if;
|
||||
end;
|
||||
|
||||
-- a_max : return the minimum of two integers;
|
||||
function a_max(L, R: INTEGER) return INTEGER is
|
||||
begin
|
||||
if L > R then
|
||||
return L;
|
||||
else
|
||||
return R;
|
||||
end if;
|
||||
end;
|
||||
|
||||
-- a_ext is the Altera version of the EXT function. It is used to both
|
||||
-- zero-extend a signal to a new length, and to extract a signal of 'size'
|
||||
-- length from a larger signal.
|
||||
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
|
||||
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
|
||||
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0) := (others => '0');
|
||||
VARIABLE i : integer := 0;
|
||||
VARIABLE bits_to_copy : integer := 0;
|
||||
VARIABLE arg_length : integer := arg'length ;
|
||||
VARIABLE LSB_bit : integer := 0;
|
||||
BEGIN
|
||||
bits_to_copy := a_min(arg_length, size);
|
||||
FOR i IN 0 TO (bits_to_copy - 1) LOOP
|
||||
result(i) := arg_copy(i);
|
||||
end LOOP;
|
||||
|
||||
RETURN(result);
|
||||
END;
|
||||
|
||||
-------------------------------------------------------
|
||||
-- Conversions for Verilog $display/$write emulation --
|
||||
-------------------------------------------------------
|
||||
|
||||
subtype slv4 is std_logic_vector(1 to 4);
|
||||
subtype slv3 is std_logic_vector(1 to 3);
|
||||
|
||||
-- Remove leading zeros. Also changes strings of all 'x' or 'z' to one char.
|
||||
-- This handles the %0<radix> kind of Verilog syntax in the format string.
|
||||
-- Examples:
|
||||
-- input output
|
||||
-- ----- -----------
|
||||
-- 001f 1f
|
||||
-- 0000 0
|
||||
-- xxxx x
|
||||
-- zzzz z
|
||||
-- xxzz xxzz
|
||||
|
||||
function do_pad_none(
|
||||
str_in : string) return string is
|
||||
variable start : integer;
|
||||
variable all_x : boolean := true;
|
||||
variable all_z : boolean := true;
|
||||
begin
|
||||
-- Nothing to remove if string isn't at least two characters long.
|
||||
if (str_in'length < 2) then
|
||||
return str_in;
|
||||
end if;
|
||||
|
||||
for i in str_in'range loop
|
||||
case str_in(i) is
|
||||
when 'X' | 'x' => all_z := false;
|
||||
when 'Z' | 'z' => all_x := false;
|
||||
when others => all_x := false; all_z := false;
|
||||
end case;
|
||||
end loop;
|
||||
|
||||
if (all_x or all_z) then
|
||||
return str_in(str_in'left to str_in'left);
|
||||
end if;
|
||||
|
||||
-- Find index of first non-zero character.
|
||||
for i in str_in'range loop
|
||||
start := i;
|
||||
exit when (str_in(i) /= '0');
|
||||
end loop;
|
||||
|
||||
return str_in(start to str_in'right);
|
||||
end do_pad_none;
|
||||
|
||||
-- Replace leading zeros with spaces.
|
||||
-- This handles the %d kind of Verilog syntax in the format string.
|
||||
function replace_leading_zeros(
|
||||
str_in : string;
|
||||
c : character) return string is
|
||||
variable str_out : string(str_in'range) := str_in;
|
||||
begin
|
||||
-- Nothing to replace if string isn't at least two characters long.
|
||||
if (str_in'length < 2) then
|
||||
return str_in;
|
||||
end if;
|
||||
|
||||
for i in str_in'range loop
|
||||
if (str_in(i) = '0') then
|
||||
str_out(i) := c;
|
||||
else
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
return str_out;
|
||||
end replace_leading_zeros;
|
||||
|
||||
function do_pad(
|
||||
str : string;
|
||||
pad : pad_type) return string is
|
||||
begin
|
||||
case pad is
|
||||
when pad_none => return do_pad_none(str);
|
||||
when pad_spaces => return replace_leading_zeros(str, ' ');
|
||||
when pad_zeros => return str;
|
||||
end case;
|
||||
end do_pad;
|
||||
|
||||
function round_up_to_multiple(
|
||||
val : integer;
|
||||
size : integer) return integer is
|
||||
begin
|
||||
return ((val + size - 1) / size) * size;
|
||||
end round_up_to_multiple;
|
||||
|
||||
function to_hex_string(
|
||||
val : std_logic_vector;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
variable ext_len : integer := round_up_to_multiple(val'length,4);
|
||||
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
|
||||
variable ptr : integer range 1 to (ext_len/4)+1 := 1;
|
||||
variable str : string(1 to ext_len/4) := (others=>'0');
|
||||
variable found_x : boolean := false;
|
||||
variable found_z : boolean := false;
|
||||
begin
|
||||
val_ext(ext_len-val'length+1 to ext_len) := val;
|
||||
|
||||
-- Extend MSB to extended sulv unless it starts with one (unsigned).
|
||||
-- Done to extend 'x' and 'z'.
|
||||
if ext_len-val'length > 0 and val(val'left) /= '1' then
|
||||
val_ext(1 to ext_len-val'length) := (others => val(val'left));
|
||||
end if;
|
||||
|
||||
for i in val_ext'range loop
|
||||
next when i rem 4 /= 1;
|
||||
|
||||
case slv4(to_x01z(val_ext(i to i+3))) is
|
||||
when "0000" => str(ptr) := '0';
|
||||
when "0001" => str(ptr) := '1';
|
||||
when "0010" => str(ptr) := '2';
|
||||
when "0011" => str(ptr) := '3';
|
||||
when "0100" => str(ptr) := '4';
|
||||
when "0101" => str(ptr) := '5';
|
||||
when "0110" => str(ptr) := '6';
|
||||
when "0111" => str(ptr) := '7';
|
||||
when "1000" => str(ptr) := '8';
|
||||
when "1001" => str(ptr) := '9';
|
||||
when "1010" => str(ptr) := 'a';
|
||||
when "1011" => str(ptr) := 'b';
|
||||
when "1100" => str(ptr) := 'c';
|
||||
when "1101" => str(ptr) := 'd';
|
||||
when "1110" => str(ptr) := 'e';
|
||||
when "1111" => str(ptr) := 'f';
|
||||
when "XXXX" => str(ptr) := 'x';
|
||||
when "ZZZZ" => str(ptr) := 'z';
|
||||
when others =>
|
||||
for j in 0 to 3 loop
|
||||
case val_ext(i + j) is
|
||||
when 'X' => found_x := true;
|
||||
when 'Z' => found_z := true;
|
||||
when others => null;
|
||||
end case;
|
||||
end loop;
|
||||
|
||||
if found_x then
|
||||
str(ptr) := 'X';
|
||||
elsif found_z then
|
||||
str(ptr) := 'Z';
|
||||
else
|
||||
str(ptr) := 'X';
|
||||
end if;
|
||||
end case;
|
||||
ptr := ptr + 1;
|
||||
end loop;
|
||||
return do_pad(str, pad);
|
||||
end to_hex_string;
|
||||
|
||||
function to_decimal_string(
|
||||
val : integer;
|
||||
pad : pad_type := pad_spaces) return string is
|
||||
variable tmp : integer := val;
|
||||
variable ptr : integer range 1 to 32 := 32;
|
||||
variable str : string(1 to 32) := (others=>'0');
|
||||
begin
|
||||
if val=0 then
|
||||
return do_pad("0", pad);
|
||||
else
|
||||
while tmp > 0 loop
|
||||
case tmp rem 10 is
|
||||
when 0 => str(ptr) := '0';
|
||||
when 1 => str(ptr) := '1';
|
||||
when 2 => str(ptr) := '2';
|
||||
when 3 => str(ptr) := '3';
|
||||
when 4 => str(ptr) := '4';
|
||||
when 5 => str(ptr) := '5';
|
||||
when 6 => str(ptr) := '6';
|
||||
when 7 => str(ptr) := '7';
|
||||
when 8 => str(ptr) := '8';
|
||||
when 9 => str(ptr) := '9';
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
tmp := tmp / 10;
|
||||
ptr := ptr - 1;
|
||||
end loop;
|
||||
|
||||
return do_pad(str(ptr+1 to 32), pad);
|
||||
end if;
|
||||
end to_decimal_string;
|
||||
|
||||
function to_decimal_string(
|
||||
val : std_logic_vector;
|
||||
pad : pad_type := pad_spaces) return string is
|
||||
variable all_x : boolean := true;
|
||||
variable all_z : boolean := true;
|
||||
variable some_x : boolean := false;
|
||||
variable some_z : boolean := false;
|
||||
variable fixed_str : string(1 to 1);
|
||||
begin
|
||||
for i in val'range loop
|
||||
case to_x01z(val(i)) is
|
||||
when 'X' => some_x := true; all_z := false;
|
||||
when 'Z' => some_z := true; all_x := false;
|
||||
when others => all_x := false; all_z := false;
|
||||
end case;
|
||||
end loop;
|
||||
|
||||
if (all_x) then
|
||||
fixed_str(1) := 'x';
|
||||
return fixed_str;
|
||||
elsif (all_z) then
|
||||
fixed_str(1) := 'z';
|
||||
return fixed_str;
|
||||
elsif (some_x) then
|
||||
fixed_str(1) := 'X';
|
||||
return fixed_str;
|
||||
elsif (some_z) then
|
||||
fixed_str(1) := 'Z';
|
||||
return fixed_str;
|
||||
else
|
||||
return to_decimal_string(conv_integer(val), pad);
|
||||
end if;
|
||||
end to_decimal_string;
|
||||
|
||||
function to_octal_string(
|
||||
val : std_logic_vector;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
variable ext_len : integer := round_up_to_multiple(val'length,3);
|
||||
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
|
||||
variable ptr : integer range 1 to (ext_len/3)+1 := 1;
|
||||
variable str : string(1 to ext_len/3) := (others=>'0');
|
||||
variable found_x : boolean := false;
|
||||
variable found_z : boolean := false;
|
||||
begin
|
||||
val_ext(ext_len-val'length+1 to ext_len) := val;
|
||||
|
||||
-- Extend MSB to extended sulv unless it starts with one (unsigned).
|
||||
-- Done to extend 'x' and 'z'.
|
||||
if ext_len-val'length > 0 and val(val'left) /= '1' then
|
||||
val_ext(1 to ext_len-val'length) := (others => val(val'left));
|
||||
end if;
|
||||
|
||||
for i in val_ext'range loop
|
||||
next when i rem 3 /= 1;
|
||||
|
||||
case slv3(to_x01z(val_ext(i to i+2))) is
|
||||
when "000" => str(ptr) := '0';
|
||||
when "001" => str(ptr) := '1';
|
||||
when "010" => str(ptr) := '2';
|
||||
when "011" => str(ptr) := '3';
|
||||
when "100" => str(ptr) := '4';
|
||||
when "101" => str(ptr) := '5';
|
||||
when "110" => str(ptr) := '6';
|
||||
when "111" => str(ptr) := '7';
|
||||
when "XXX" => str(ptr) := 'x';
|
||||
when "ZZZ" => str(ptr) := 'z';
|
||||
when others =>
|
||||
for j in 0 to 2 loop
|
||||
case val_ext(i + j) is
|
||||
when 'X' => found_x := true;
|
||||
when 'Z' => found_z := true;
|
||||
when others => null;
|
||||
end case;
|
||||
end loop;
|
||||
|
||||
if found_x then
|
||||
str(ptr) := 'X';
|
||||
elsif found_z then
|
||||
str(ptr) := 'Z';
|
||||
else
|
||||
str(ptr) := 'X';
|
||||
end if;
|
||||
end case;
|
||||
ptr := ptr + 1;
|
||||
end loop;
|
||||
return do_pad(str, pad);
|
||||
end to_octal_string;
|
||||
|
||||
function to_hex_string(
|
||||
val : std_logic;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
begin
|
||||
return to_binary_string(val, pad);
|
||||
end to_hex_string;
|
||||
|
||||
function to_decimal_string(
|
||||
val : std_logic;
|
||||
pad : pad_type := pad_spaces) return string is
|
||||
begin
|
||||
return to_binary_string(val, pad);
|
||||
end to_decimal_string;
|
||||
|
||||
function to_octal_string(
|
||||
val : std_logic;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
begin
|
||||
return to_binary_string(val, pad);
|
||||
end to_octal_string;
|
||||
|
||||
function to_binary_string(
|
||||
val : std_logic;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
variable str : string(1 to 1);
|
||||
begin
|
||||
case to_x01z(val) is
|
||||
when '0' => str(1) := '0';
|
||||
when '1' => str(1) := '1';
|
||||
when 'X' => str(1) := 'x';
|
||||
when 'Z' => str(1) := 'z';
|
||||
when others => str(1) := 'x';
|
||||
end case;
|
||||
return do_pad(str, pad);
|
||||
end to_binary_string;
|
||||
|
||||
function to_binary_string(
|
||||
val : std_logic_vector;
|
||||
pad : pad_type := pad_zeros) return string is
|
||||
variable str : string(1 to val'length) := (others=>'0');
|
||||
variable ptr : integer := str'left;
|
||||
begin
|
||||
for i in val'range loop
|
||||
str(ptr to ptr) := to_binary_string(val(i));
|
||||
ptr := ptr + 1;
|
||||
end loop;
|
||||
return do_pad(str, pad);
|
||||
end to_binary_string;
|
||||
|
||||
end altera_europa_support_lib;
|
||||
@@ -1,40 +0,0 @@
|
||||
-----------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 2003 by Altera Corp. All rights reserved. --
|
||||
-- --
|
||||
-- --
|
||||
-- Description: Declares utility package for internal Altera synthesis --
|
||||
-- support. --
|
||||
-- --
|
||||
-- --
|
||||
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
|
||||
-- --
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
PACKAGE altera_internal_syn is
|
||||
|
||||
-- Specfies a built-in pragma function that should replace a user-defined
|
||||
-- subprogram during synthesis.
|
||||
ATTRIBUTE synthesis_return : STRING;
|
||||
|
||||
-- If a subprogram specifies a synthesis_return attribute, it may also
|
||||
-- use these additional attributes to fine-tune the behavior of a built-in
|
||||
-- function.
|
||||
|
||||
-- Specifies the method for calculating the size of a unary or binary
|
||||
-- built-in pragma function's result. The following values are supported:
|
||||
--
|
||||
-- LEFT: Use the size of the left operand
|
||||
-- RIGHT: Use the size of the right operand
|
||||
-- MAX_LEFT_RIGHT: Use the maximum of the left and right operands
|
||||
ATTRIBUTE synthesis_result_size : STRING;
|
||||
|
||||
-- Flag that indicates if a type or an argument/result of a built-in pragma
|
||||
-- function is signed (TRUE) or unsigned (FALSE).
|
||||
ATTRIBUTE is_signed : BOOLEAN;
|
||||
|
||||
-- Flag that indicates if truncation should preserve the sign bit
|
||||
attribute signed_truncation : BOOLEAN;
|
||||
|
||||
END altera_internal_syn;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,435 +0,0 @@
|
||||
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
-- the Altera MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Altera and sold by Altera or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- ALtera Primitives Component Declaration File
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.VITAL_Timing.all;
|
||||
use IEEE.VITAL_Primitives.all;
|
||||
|
||||
package dffeas_pack is
|
||||
|
||||
-- default generic values
|
||||
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
|
||||
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
|
||||
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
|
||||
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
|
||||
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
|
||||
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
|
||||
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
|
||||
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
|
||||
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
|
||||
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
|
||||
|
||||
end dffeas_pack;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use IEEE.VITAL_Timing.all;
|
||||
use work.dffeas_pack.all;
|
||||
|
||||
package altera_primitives_components is
|
||||
|
||||
component carry
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic );
|
||||
end component;
|
||||
|
||||
component cascade
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic );
|
||||
end component;
|
||||
|
||||
component global
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic);
|
||||
end component;
|
||||
|
||||
component tri
|
||||
port(
|
||||
a_in : in std_logic;
|
||||
oe : in std_logic;
|
||||
a_out : out std_logic);
|
||||
end component;
|
||||
|
||||
component carry_sum
|
||||
port (
|
||||
sin : in std_logic;
|
||||
cin : in std_logic;
|
||||
sout : out std_logic;
|
||||
cout : out std_logic );
|
||||
end component;
|
||||
|
||||
component exp
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic);
|
||||
end component;
|
||||
|
||||
component soft
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic );
|
||||
end component;
|
||||
|
||||
component opndrn
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic );
|
||||
end component;
|
||||
|
||||
component row_global
|
||||
port (
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic );
|
||||
end component;
|
||||
|
||||
component lut_input
|
||||
port(
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic);
|
||||
end component;
|
||||
|
||||
component lut_output
|
||||
port(
|
||||
a_in : in std_logic;
|
||||
a_out : out std_logic);
|
||||
end component;
|
||||
|
||||
component dlatch
|
||||
port(
|
||||
d : in std_logic;
|
||||
ena : in std_logic;
|
||||
clrn : in std_logic;
|
||||
prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component latch
|
||||
port(
|
||||
d : in std_logic;
|
||||
ena : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component dff
|
||||
port(
|
||||
d, clk, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component dffe
|
||||
port(
|
||||
d, clk, ena, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component dffea
|
||||
port(
|
||||
d, clk, ena, clrn, prn, aload, adata : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component dffeas
|
||||
generic (
|
||||
power_up : string := "DONT_CARE";
|
||||
is_wysiwyg : string := "false";
|
||||
dont_touch : string := "false";
|
||||
x_on_violation : string := "on";
|
||||
lpm_type : string := "DFFEAS";
|
||||
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_d : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_prn : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
TimingChecksOn: Boolean := True;
|
||||
MsgOn: Boolean := DefGlitchMsgOn;
|
||||
XOn: Boolean := DefGlitchXOn;
|
||||
MsgOnChecks: Boolean := DefMsgOnChecks;
|
||||
XOnChecks: Boolean := DefXOnChecks;
|
||||
InstancePath: STRING := "*" );
|
||||
|
||||
port (
|
||||
d : in std_logic := '0';
|
||||
clk : in std_logic := '0';
|
||||
ena : in std_logic := '1';
|
||||
clrn : in std_logic := '1';
|
||||
prn : in std_logic := '1';
|
||||
aload : in std_logic := '0';
|
||||
asdata : in std_logic := '1';
|
||||
sclr : in std_logic := '0';
|
||||
sload : in std_logic := '0';
|
||||
devclrn : in std_logic := '1';
|
||||
devpor : in std_logic := '1';
|
||||
q : out std_logic );
|
||||
end component;
|
||||
|
||||
component tff
|
||||
port(
|
||||
t, clk, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component tffe
|
||||
port(
|
||||
t, clk, ena, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component jkff
|
||||
port(
|
||||
j, k, clk, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component jkffe
|
||||
port(
|
||||
j, k, clk, ena, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component srff
|
||||
port(
|
||||
s, r, clk, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component srffe
|
||||
port(
|
||||
s, r, clk, ena, clrn, prn : in std_logic;
|
||||
q : out std_logic);
|
||||
end component;
|
||||
|
||||
component clklock
|
||||
generic(
|
||||
input_frequency : natural := 10000;
|
||||
clockboost : natural := 1);
|
||||
|
||||
port(
|
||||
inclk : in std_logic;
|
||||
outclk : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_inbuf
|
||||
generic(
|
||||
io_standard : string := "NONE";
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_inbuf" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
o : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_outbuf
|
||||
generic(
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
slow_slew_rate : string := "NONE";
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_outbuf" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
o : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_outbuf_tri
|
||||
generic(
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
slow_slew_rate : string := "NONE";
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_outbuf_tri" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
oe : in std_logic;
|
||||
o : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_iobuf
|
||||
generic(
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
slow_slew_rate : string := "NONE";
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
input_termination : string := "NONE";
|
||||
output_termination : string := "NONE";
|
||||
lpm_type : string := "alt_iobuf" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
oe : in std_logic;
|
||||
io : inout std_logic;
|
||||
o : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_inbuf_diff
|
||||
generic(
|
||||
io_standard : string := "NONE";
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_inbuf_diff" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
ibar : in std_logic;
|
||||
o : out std_logic);
|
||||
end component;
|
||||
|
||||
component alt_outbuf_diff
|
||||
generic (
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_outbuf_diff" );
|
||||
|
||||
port(
|
||||
i : in std_logic;
|
||||
o : out std_logic;
|
||||
obar : out std_logic );
|
||||
end component;
|
||||
|
||||
component alt_outbuf_tri_diff
|
||||
generic (
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
lpm_type : string := "alt_outbuf_tri_diff" );
|
||||
port(
|
||||
i : in std_logic;
|
||||
oe : in std_logic;
|
||||
o : out std_logic;
|
||||
obar : out std_logic );
|
||||
end component;
|
||||
|
||||
component alt_iobuf_diff
|
||||
generic (
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
input_termination : string := "NONE";
|
||||
output_termination : string := "NONE";
|
||||
lpm_type : string := "alt_iobuf_diff" );
|
||||
port(
|
||||
i : in std_logic;
|
||||
oe : in std_logic;
|
||||
io : inout std_logic;
|
||||
iobar : inout std_logic;
|
||||
o : out std_logic );
|
||||
end component;
|
||||
|
||||
component alt_bidir_diff
|
||||
generic (
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
input_termination : string := "NONE";
|
||||
output_termination : string := "NONE";
|
||||
lpm_type : string := "alt_bidir_diff" );
|
||||
port(
|
||||
oe : in std_logic;
|
||||
bidirin : inout std_logic;
|
||||
io : inout std_logic;
|
||||
iobar : inout std_logic );
|
||||
end component;
|
||||
|
||||
component alt_bidir_buf
|
||||
generic (
|
||||
io_standard : string := "NONE";
|
||||
current_strength : string := "NONE";
|
||||
current_strength_new : string := "NONE";
|
||||
slew_rate : integer := -1;
|
||||
location : string := "NONE";
|
||||
enable_bus_hold : string := "NONE";
|
||||
weak_pull_up_resistor : string := "NONE";
|
||||
termination : string := "NONE";
|
||||
input_termination : string := "NONE";
|
||||
output_termination : string := "NONE";
|
||||
lpm_type : string := "alt_bidir_buf" );
|
||||
port(
|
||||
oe : in std_logic;
|
||||
bidirin : inout std_logic;
|
||||
io : inout std_logic );
|
||||
end component;
|
||||
|
||||
end altera_primitives_components;
|
||||
|
||||
@@ -1,45 +0,0 @@
|
||||
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
-- the Altera MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Altera and sold by Altera or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
library std;
|
||||
use std.standard.all;
|
||||
|
||||
package altera_standard_functions is
|
||||
|
||||
function maximum (L, R: integer) return integer;
|
||||
function minimum (L, R: integer) return integer;
|
||||
|
||||
end altera_standard_functions;
|
||||
|
||||
package body altera_standard_functions is
|
||||
|
||||
function maximum (L, R: integer) return integer is
|
||||
begin
|
||||
if L > R then
|
||||
return L;
|
||||
else
|
||||
return R;
|
||||
end if;
|
||||
end maximum;
|
||||
|
||||
function minimum (L, R: integer) return integer is
|
||||
begin
|
||||
if L > R then
|
||||
return R;
|
||||
else
|
||||
return L;
|
||||
end if;
|
||||
end minimum;
|
||||
|
||||
end altera_standard_functions;
|
||||
@@ -1,94 +0,0 @@
|
||||
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
-- the Altera MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Altera and sold by Altera or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
-----------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 2006 by Altera Corp. All rights reserved. --
|
||||
-- --
|
||||
-- --
|
||||
-- Description: Package containing Attribute Declarations for all --
|
||||
-- attributes that control Quartus II Integrated Synthesis. --
|
||||
-- Please refer to the Quartus II Help for documentation --
|
||||
-- on using these attributes. --
|
||||
-- --
|
||||
-- --
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
library std;
|
||||
use std.standard.all;
|
||||
|
||||
|
||||
PACKAGE altera_syn_attributes is
|
||||
|
||||
-- Directs Quartus II to implement input, output, and output
|
||||
-- enable registers in I/O cells that have fast, direct connections to
|
||||
-- an I/O pin, when possible
|
||||
ATTRIBUTE useioff : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from minimizing or removing a register
|
||||
ATTRIBUTE preserve : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from removing a dangling register
|
||||
ATTRIBUTE noprune : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from merging a register with a duplicate
|
||||
ATTRIBUTE dont_merge : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from replicating a register to improve timing
|
||||
ATTRIBUTE dont_replicate : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from retiming a register
|
||||
ATTRIBUTE dont_retime : BOOLEAN;
|
||||
|
||||
-- Identifies the critical clock enable signal for a register. The
|
||||
-- Quartus II software will attempt to connect this signal to the
|
||||
-- dedicated clock enable port.
|
||||
ATTRIBUTE direct_enable : BOOLEAN;
|
||||
|
||||
-- Prevents Quartus II from minimizing or removing a particular
|
||||
-- signal net during combinational logic optimization
|
||||
ATTRIBUTE keep : BOOLEAN;
|
||||
|
||||
-- Sets a fan-out limit on a register or net.
|
||||
ATTRIBUTE maxfan : NATURAL;
|
||||
|
||||
-- Controls the implementation of a multiplication (*) operations in VHDL
|
||||
ATTRIBUTE multstyle : STRING;
|
||||
|
||||
-- Controls the implementation of inferred memories
|
||||
ATTRIBUTE ramstyle : STRING;
|
||||
|
||||
-- Controls the implementation of inferred ROMs
|
||||
ATTRIBUTE romstyle : STRING;
|
||||
|
||||
-- Specifies a Memory Initialization File (.mif) for an inferred RAM
|
||||
ATTRIBUTE ram_init_file : STRING;
|
||||
|
||||
-- Assigns a logic encoding to an enumerated type. Prevents state
|
||||
-- machine extraction for all objects with the enumerated type.
|
||||
ATTRIBUTE enum_encoding : STRING;
|
||||
|
||||
-- Assigns a state encoding to an enumerated type that models the states
|
||||
-- of an extracted state machine.
|
||||
ATTRIBUTE syn_encoding : STRING;
|
||||
|
||||
-- Specifies device pin assignments for a VHDL entity port
|
||||
ATTRIBUTE chip_pin : STRING;
|
||||
|
||||
-- Applies an arbitrary number of Quartus Settings File (QSF) assignments
|
||||
-- to a signal, entity, architecture, instance, or inferred register
|
||||
ATTRIBUTE altera_attribute : STRING;
|
||||
|
||||
END altera_syn_attributes;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,242 +0,0 @@
|
||||
-----------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 1996 by Altera Corp. All rights reserved. --
|
||||
-- --
|
||||
-- --
|
||||
-- Description: Package file for Altera mega functions. --
|
||||
-- --
|
||||
-- --
|
||||
------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package megacore is
|
||||
component a16450
|
||||
port (
|
||||
mr : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
a : IN std_logic_vector(2 downto 0);
|
||||
din : IN std_logic_vector(7 downto 0);
|
||||
cs0 : IN std_logic;
|
||||
cs1 : IN std_logic;
|
||||
ncs2 : IN std_logic;
|
||||
nads : IN std_logic;
|
||||
rd : IN std_logic;
|
||||
nrd : IN std_logic;
|
||||
wr : IN std_logic;
|
||||
nwr : IN std_logic;
|
||||
sin : IN std_logic;
|
||||
rclk : IN std_logic;
|
||||
ncts : IN std_logic;
|
||||
ndsr : IN std_logic;
|
||||
ndcd : IN std_logic;
|
||||
nri : IN std_logic;
|
||||
dout : OUT std_logic_vector(7 downto 0);
|
||||
ddis : OUT std_logic;
|
||||
csout : OUT std_logic;
|
||||
sout : OUT std_logic;
|
||||
nbaudout : OUT std_logic;
|
||||
nrts : OUT std_logic;
|
||||
ndtr : OUT std_logic;
|
||||
nout1 : OUT std_logic;
|
||||
nout2 : OUT std_logic;
|
||||
intr : OUT std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component a6402
|
||||
port (
|
||||
cls1 : IN std_logic;
|
||||
cls2 : IN std_logic;
|
||||
crl : IN std_logic;
|
||||
ndrr : IN std_logic;
|
||||
epe : IN std_logic;
|
||||
mr : IN std_logic;
|
||||
pi : IN std_logic;
|
||||
rrc : IN std_logic;
|
||||
rri : IN std_logic;
|
||||
sbs : IN std_logic;
|
||||
tbr : IN std_logic_vector(7 downto 0);
|
||||
ntbrl : IN std_logic;
|
||||
trc : IN std_logic;
|
||||
dr : OUT std_logic;
|
||||
fe : OUT std_logic;
|
||||
oe : OUT std_logic;
|
||||
pe : OUT std_logic;
|
||||
rbr : OUT std_logic_vector(7 downto 0);
|
||||
tbre : OUT std_logic;
|
||||
tro : OUT std_logic;
|
||||
tre : OUT std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component a6850
|
||||
port (
|
||||
nreset : IN std_logic;
|
||||
di : IN std_logic_vector(7 downto 0);
|
||||
e : IN std_logic;
|
||||
rnw : IN std_logic;
|
||||
cs : IN std_logic_vector(2 downto 0);
|
||||
rs : IN std_logic;
|
||||
txclk : IN std_logic;
|
||||
rxclk : IN std_logic;
|
||||
rxdata : IN std_logic;
|
||||
ncts : IN std_logic;
|
||||
ndcd : IN std_logic;
|
||||
do : OUT std_logic_vector(7 downto 0);
|
||||
nirq : OUT std_logic;
|
||||
txdata : OUT std_logic;
|
||||
nrts : OUT std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component a8237
|
||||
port (
|
||||
reset : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ncs : IN std_logic;
|
||||
niorin : IN std_logic;
|
||||
niowin : IN std_logic;
|
||||
ready : IN std_logic;
|
||||
hlda : IN std_logic;
|
||||
neopin : IN std_logic;
|
||||
ain : IN std_logic_vector(3 downto 0);
|
||||
dreq : IN std_logic_vector(3 downto 0);
|
||||
dbin : IN std_logic_vector(7 downto 0);
|
||||
dbout : OUT std_logic_vector(7 downto 0);
|
||||
dben : OUT std_logic;
|
||||
aout : OUT std_logic_vector(7 downto 0);
|
||||
hrq : OUT std_logic;
|
||||
dack : OUT std_logic_vector(3 downto 0);
|
||||
aen : OUT std_logic;
|
||||
adstb : OUT std_logic;
|
||||
niorout : OUT std_logic;
|
||||
niowout : OUT std_logic;
|
||||
nmemr : OUT std_logic;
|
||||
nmemw : OUT std_logic;
|
||||
neopout : OUT std_logic;
|
||||
dmaenable : OUT std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component a8251
|
||||
port (
|
||||
clk : IN std_logic;
|
||||
nreset : IN std_logic;
|
||||
nwr : IN std_logic;
|
||||
nrd : IN std_logic;
|
||||
ncs : IN std_logic;
|
||||
cnd : IN std_logic;
|
||||
ndsr : IN std_logic;
|
||||
ncts : IN std_logic;
|
||||
extsyncd : IN std_logic;
|
||||
ntxc : IN std_logic;
|
||||
nrxc : IN std_logic;
|
||||
rxd : IN std_logic;
|
||||
din : IN std_logic_vector(7 downto 0);
|
||||
txd : OUT std_logic;
|
||||
txrdy : OUT std_logic;
|
||||
txempty : OUT std_logic;
|
||||
rxrdy : OUT std_logic;
|
||||
ndtr : OUT std_logic;
|
||||
nrts : OUT std_logic;
|
||||
syn_brk : OUT std_logic;
|
||||
nen : OUT std_logic;
|
||||
dout : OUT std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component a8255
|
||||
port (
|
||||
reset : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ncs : IN std_logic;
|
||||
nrd : IN std_logic;
|
||||
nwr : IN std_logic;
|
||||
a : IN std_logic_vector(1 downto 0);
|
||||
din : IN std_logic_vector(7 downto 0);
|
||||
pain : IN std_logic_vector(7 downto 0);
|
||||
pbin : IN std_logic_vector(7 downto 0);
|
||||
pcin : IN std_logic_vector(7 downto 0);
|
||||
dout : OUT std_logic_vector(7 downto 0);
|
||||
paout : OUT std_logic_vector(7 downto 0);
|
||||
paen : OUT std_logic;
|
||||
pbout : OUT std_logic_vector(7 downto 0);
|
||||
pben : OUT std_logic;
|
||||
pcout : OUT std_logic_vector(7 downto 0);
|
||||
pcen : OUT std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component rgb2ycrcb
|
||||
port (
|
||||
R : IN std_logic_vector(7 downto 0);
|
||||
G : IN std_logic_vector(7 downto 0);
|
||||
B : IN std_logic_vector(7 downto 0);
|
||||
CLOCK : IN std_logic := '0';
|
||||
ACLR : IN std_logic := '0';
|
||||
Y : OUT std_logic_vector(15 downto 0);
|
||||
Cr: OUT std_logic_vector(14 downto 0);
|
||||
Cb: OUT std_logic_vector(14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ycrcb2rgb
|
||||
port (
|
||||
Y : IN std_logic_vector(7 downto 0);
|
||||
CR : IN std_logic_vector(7 downto 0);
|
||||
CB : IN std_logic_vector(7 downto 0);
|
||||
CLOCK : IN std_logic := '0';
|
||||
ACLR : IN std_logic := '0';
|
||||
R : OUT std_logic_vector(16 downto 0);
|
||||
G: OUT std_logic_vector(16 downto 0);
|
||||
B: OUT std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component a8259
|
||||
port (
|
||||
nmrst, clk, ncs, nwr, nrd, a0, nsp, ninta : IN std_logic;
|
||||
casin : IN std_logic_vector(2 downto 0);
|
||||
din, ir : IN std_logic_vector(7 downto 0);
|
||||
nen, cas_en, int : OUT std_logic;
|
||||
dout : OUT std_logic_vector(7 downto 0);
|
||||
casout : OUT std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component fft
|
||||
generic (
|
||||
WIDTH_DATA : POSITIVE;
|
||||
WIDTH_TWIDDLE : POSITIVE;
|
||||
PIPE_DATA : INTEGER;
|
||||
PIPE_TWIDDLE : INTEGER;
|
||||
WIDTH_EXPONENT : POSITIVE;
|
||||
WIDTH_ADD : POSITIVE;
|
||||
EXPONENT_INITIAL_VALUE : INTEGER
|
||||
);
|
||||
port (
|
||||
clock : IN std_logic := '0';
|
||||
start_fft : IN std_logic;
|
||||
data_left_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
data_left_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
data_right_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
data_right_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
twiddle_re : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
|
||||
twiddle_im : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
|
||||
done : OUT std_logic;
|
||||
data_direction : OUT std_logic;
|
||||
we_left : OUT std_logic;
|
||||
add_left : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
|
||||
we_right : OUT std_logic;
|
||||
add_right : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
|
||||
add_twiddle : OUT std_logic_vector(WIDTH_ADD-2 downto 0);
|
||||
data_out_re : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
data_out_im : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
|
||||
exponent : OUT std_logic_vector(WIDTH_EXPONENT-1 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
end megacore;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,221 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2002 Altera Corporation
|
||||
--
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any
|
||||
-- other associated documentation or information provided by Altera or a
|
||||
-- partner under Altera's Megafunction Partnership Program may be used only
|
||||
-- to program PLD devices (but not masked PLD devices) from Altera. Any
|
||||
-- other use of such megafunction design, net list, support information,
|
||||
-- device programming or simulation file, or any other related
|
||||
-- documentation or information is prohibited for any other purpose,
|
||||
-- including, but not limited to modification, reverse engineering, de-
|
||||
-- compiling, or use with any other silicon devices, unless such use is
|
||||
-- explicitly licensed under a separate agreement with Altera or a
|
||||
-- megafunction partner. Title to the intellectual property, including
|
||||
-- patents, copyrights, trademarks, trade secrets, or maskworks, embodied
|
||||
-- in any such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information provided by Altera or a megafunction partner, remains with
|
||||
-- Altera, the megafunction partner, or their respective licensors. No
|
||||
-- other licenses, including any licenses needed under any third party's
|
||||
-- intellectual property, are provided herein.
|
||||
----------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------
|
||||
-- ALtera Stratix GX Megafunction Component Declaration File
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package stratixgx_mf_components is
|
||||
function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
|
||||
channel_width : integer) return integer;
|
||||
function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
|
||||
dwidth_factor : integer) return integer;
|
||||
component altgxb
|
||||
generic (
|
||||
operation_mode : string := "DUPLEX";
|
||||
loopback_mode : string := "NONE";
|
||||
reverse_loopback_mode : string := "NONE";
|
||||
protocol : string := "CUSTOM";
|
||||
number_of_channels: integer := 20;
|
||||
number_of_quads : integer := 1;
|
||||
channel_width : positive := 20;
|
||||
pll_inclock_period : integer := 20000;
|
||||
data_rate : integer := 0;
|
||||
data_rate_remainder : integer := 0;
|
||||
|
||||
rx_data_rate : integer := 0;
|
||||
rx_data_rate_remainder : integer := 0;
|
||||
|
||||
use_8b_10b_mode : string := "OFF";
|
||||
use_double_data_mode : string := "OFF";
|
||||
dwidth_factor : integer := 1;
|
||||
|
||||
-- RX Mode
|
||||
disparity_mode : string := "OFF";
|
||||
cru_inclock_period : integer := 0; -- Units in ps
|
||||
run_length : integer := 128;
|
||||
run_length_enable : string := "OFF";
|
||||
use_channel_align : string := "OFF";
|
||||
use_auto_bit_slip : string := "OFF";
|
||||
use_rate_match_fifo : string := "OFF";
|
||||
use_symbol_align : string := "OFF";
|
||||
align_pattern : string := "X";
|
||||
align_pattern_length : integer := 0;
|
||||
infiniband_invalid_code : integer := 0;
|
||||
clk_out_mode_reference : string := "ON";
|
||||
-- TX Mode
|
||||
use_fifo_mode : string := "ON";
|
||||
intended_device_family : string := "STRATIXGX";
|
||||
force_disparity_mode : string := "OFF";
|
||||
lpm_type : string := "altgxb";
|
||||
tx_termination : integer := 0;
|
||||
-- Quartus 2.2 New Parameters
|
||||
-- common
|
||||
use_self_test_mode : string := "OFF";
|
||||
self_test_mode : integer := 0;
|
||||
|
||||
-- Receiver
|
||||
use_equalizer_ctrl_signal : string := "OFF";
|
||||
equalizer_ctrl_setting : integer := 0;
|
||||
signal_threshold_select : integer := 80;
|
||||
rx_bandwidth_type : string := "NEW_MEDIUM";
|
||||
rx_enable_dc_coupling : string := "OFF";
|
||||
use_vod_ctrl_signal : string := "OFF";
|
||||
vod_ctrl_setting : integer := 1000;
|
||||
use_preemphasis_ctrl_signal : string := "OFF";
|
||||
preemphasis_ctrl_setting : integer := 0;
|
||||
use_phase_shift : string := "ON";
|
||||
pll_bandwidth_type : string := "LOW";
|
||||
pll_use_dc_coupling : string := "OFF";
|
||||
rx_ppm_setting : integer := 1000;
|
||||
use_generic_fifo : string := "OFF";
|
||||
use_rx_cruclk : string := "OFF";
|
||||
use_rx_clkout : string := "OFF";
|
||||
use_rx_coreclk : string := "OFF";
|
||||
use_tx_coreclk : string := "OFF";
|
||||
instantiate_transmitter_pll : string := "OFF";
|
||||
consider_instantiate_transmitter_pll_param : string := "OFF";
|
||||
rx_force_signal_detect : string := "OFF";
|
||||
flip_rx_out : string := "OFF";
|
||||
flip_tx_in : string := "OFF";
|
||||
add_generic_fifo_we_synch_register : string := "OFF";
|
||||
consider_enable_tx_8b_10b_i1i2_generation : string := "OFF";
|
||||
enable_tx_8b_10b_i1i2_generation : string := "OFF";
|
||||
for_engineering_sample_device : string := "ON";
|
||||
device_family : string := ""
|
||||
|
||||
);
|
||||
|
||||
port (
|
||||
inclk : in std_logic_vector(number_of_quads-1 downto 0) := (others => '0');
|
||||
rx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
pll_areset : in std_logic_vector(number_of_quads-1 downto 0):= (others => '0');
|
||||
rx_cruclk : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '0');
|
||||
rx_in : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
rx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
rx_bitslip : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
rx_enacdet : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
|
||||
rx_we: in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
rx_re: in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
|
||||
rx_slpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
rx_a1a2size : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
rx_equalizerctrl : in std_logic_vector(number_of_channels * 3 -1 downto 0) := (others => '0');
|
||||
rx_locktorefclk : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
|
||||
rx_locktodata : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
|
||||
|
||||
tx_in : in std_logic_vector(channel_width * number_of_channels-1 downto 0) := (others => '0');
|
||||
tx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
tx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
tx_ctrlenable : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
|
||||
tx_forcedisparity : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
|
||||
tx_srlpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
|
||||
tx_vodctrl : in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
|
||||
tx_preemphasisctrl: in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
|
||||
|
||||
|
||||
-- XGM Input ports, common for Both Rx and Tx Mode
|
||||
|
||||
txdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
rxdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
rxanalogreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
|
||||
pllenable : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '1');
|
||||
|
||||
|
||||
pll_locked : out std_logic_vector(number_of_quads-1 downto 0);
|
||||
coreclk_out : out std_logic_vector(number_of_quads-1 downto 0);
|
||||
rx_out : out std_logic_vector(get_rx_channel_width(use_generic_fifo,
|
||||
clk_out_mode_reference, channel_width) * number_of_channels-1 downto 0);
|
||||
rx_clkout : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_locked : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_freqlocked : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_syncstatus : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
|
||||
|
||||
rx_patterndetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
rx_ctrldetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
rx_errdetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
rx_disperr : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
rx_signaldetect : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_fifoalmostempty : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_fifoalmostfull : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_channelaligned : out std_logic_vector(number_of_quads-1 downto 0);
|
||||
rx_bisterr : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_bistdone : out std_logic_vector(number_of_channels-1 downto 0);
|
||||
rx_a1a2sizeout : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
|
||||
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
|
||||
tx_out : out std_logic_vector(number_of_channels-1 downto 0)
|
||||
);
|
||||
|
||||
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
end;
|
||||
|
||||
package body stratixgx_mf_components is
|
||||
|
||||
function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
|
||||
channel_width : integer) return integer is
|
||||
variable rx_channel_width : integer;
|
||||
begin
|
||||
rx_channel_width := channel_width;
|
||||
if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
|
||||
if (channel_width = 16) or (channel_width = 20) then
|
||||
rx_channel_width := channel_width/2;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
return rx_channel_width;
|
||||
|
||||
end get_rx_channel_width;
|
||||
|
||||
|
||||
function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
|
||||
dwidth_factor : integer) return integer is
|
||||
variable rx_dwidth_factor : integer;
|
||||
begin
|
||||
rx_dwidth_factor := dwidth_factor;
|
||||
if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
|
||||
if (dwidth_factor = 2) then
|
||||
rx_dwidth_factor := dwidth_factor/2;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
return rx_dwidth_factor;
|
||||
|
||||
end get_rx_dwidth_factor;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,847 +0,0 @@
|
||||
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, the Altera Quartus II License Agreement,
|
||||
-- the Altera MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Altera and sold by Altera or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
-- Quartus II 15.0.0 Build 145 04/22/2015
|
||||
|
||||
LIBRARY IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.VITAL_Timing.all;
|
||||
use work.cycloneive_atom_pack.all;
|
||||
|
||||
package cycloneive_components is
|
||||
|
||||
|
||||
--
|
||||
-- cycloneive_lcell_comb
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_lcell_comb
|
||||
generic (
|
||||
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
|
||||
sum_lutc_input : string := "datac";
|
||||
dont_touch : string := "off";
|
||||
lpm_type : string := "cycloneive_lcell_comb";
|
||||
TimingChecksOn: Boolean := True;
|
||||
MsgOn: Boolean := DefGlitchMsgOn;
|
||||
XOn: Boolean := DefGlitchXOn;
|
||||
MsgOnChecks: Boolean := DefMsgOnChecks;
|
||||
XOnChecks: Boolean := DefXOnChecks;
|
||||
InstancePath: STRING := "*";
|
||||
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_dataa : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_datab : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_datac : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_datad : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_cin : VitalDelayType01 := DefPropDelay01
|
||||
);
|
||||
port (
|
||||
dataa : in std_logic := '1';
|
||||
datab : in std_logic := '1';
|
||||
datac : in std_logic := '1';
|
||||
datad : in std_logic := '1';
|
||||
cin : in std_logic := '0';
|
||||
combout : out std_logic;
|
||||
cout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_routing_wire
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_routing_wire
|
||||
generic (
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_datain : VitalDelayType01 := DefPropDelay01
|
||||
);
|
||||
PORT (
|
||||
datain : in std_logic;
|
||||
dataout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_pll
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_pll
|
||||
GENERIC (
|
||||
operation_mode : string := "normal";
|
||||
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
|
||||
compensate_clock : string := "clock0";
|
||||
inclk0_input_frequency : integer := 0;
|
||||
inclk1_input_frequency : integer := 0;
|
||||
self_reset_on_loss_lock : string := "off";
|
||||
switch_over_type : string := "auto";
|
||||
switch_over_counter : integer := 1;
|
||||
enable_switch_over_counter : string := "off";
|
||||
bandwidth : integer := 0;
|
||||
bandwidth_type : string := "auto";
|
||||
use_dc_coupling : string := "false";
|
||||
lock_c : integer := 4;
|
||||
sim_gate_lock_device_behavior : string := "off";
|
||||
lock_high : integer := 0;
|
||||
lock_low : integer := 0;
|
||||
lock_window_ui : string := "0.05";
|
||||
lock_window : time := 5 ps;
|
||||
test_bypass_lock_detect : string := "off";
|
||||
clk0_output_frequency : integer := 0;
|
||||
clk0_multiply_by : integer := 0;
|
||||
clk0_divide_by : integer := 0;
|
||||
clk0_phase_shift : string := "0";
|
||||
clk0_duty_cycle : integer := 50;
|
||||
clk1_output_frequency : integer := 0;
|
||||
clk1_multiply_by : integer := 0;
|
||||
clk1_divide_by : integer := 0;
|
||||
clk1_phase_shift : string := "0";
|
||||
clk1_duty_cycle : integer := 50;
|
||||
clk2_output_frequency : integer := 0;
|
||||
clk2_multiply_by : integer := 0;
|
||||
clk2_divide_by : integer := 0;
|
||||
clk2_phase_shift : string := "0";
|
||||
clk2_duty_cycle : integer := 50;
|
||||
clk3_output_frequency : integer := 0;
|
||||
clk3_multiply_by : integer := 0;
|
||||
clk3_divide_by : integer := 0;
|
||||
clk3_phase_shift : string := "0";
|
||||
clk3_duty_cycle : integer := 50;
|
||||
clk4_output_frequency : integer := 0;
|
||||
clk4_multiply_by : integer := 0;
|
||||
clk4_divide_by : integer := 0;
|
||||
clk4_phase_shift : string := "0";
|
||||
clk4_duty_cycle : integer := 50;
|
||||
pfd_min : integer := 0;
|
||||
pfd_max : integer := 0;
|
||||
vco_min : integer := 0;
|
||||
vco_max : integer := 0;
|
||||
vco_center : integer := 0;
|
||||
m_initial : integer := 1;
|
||||
m : integer := 0;
|
||||
n : integer := 1;
|
||||
c0_high : integer := 1;
|
||||
c0_low : integer := 1;
|
||||
c0_initial : integer := 1;
|
||||
c0_mode : string := "bypass";
|
||||
c0_ph : integer := 0;
|
||||
c1_high : integer := 1;
|
||||
c1_low : integer := 1;
|
||||
c1_initial : integer := 1;
|
||||
c1_mode : string := "bypass";
|
||||
c1_ph : integer := 0;
|
||||
c2_high : integer := 1;
|
||||
c2_low : integer := 1;
|
||||
c2_initial : integer := 1;
|
||||
c2_mode : string := "bypass";
|
||||
c2_ph : integer := 0;
|
||||
c3_high : integer := 1;
|
||||
c3_low : integer := 1;
|
||||
c3_initial : integer := 1;
|
||||
c3_mode : string := "bypass";
|
||||
c3_ph : integer := 0;
|
||||
c4_high : integer := 1;
|
||||
c4_low : integer := 1;
|
||||
c4_initial : integer := 1;
|
||||
c4_mode : string := "bypass";
|
||||
c4_ph : integer := 0;
|
||||
m_ph : integer := 0;
|
||||
clk0_counter : string := "unused";
|
||||
clk1_counter : string := "unused";
|
||||
clk2_counter : string := "unused";
|
||||
clk3_counter : string := "unused";
|
||||
clk4_counter : string := "unused";
|
||||
c1_use_casc_in : string := "off";
|
||||
c2_use_casc_in : string := "off";
|
||||
c3_use_casc_in : string := "off";
|
||||
c4_use_casc_in : string := "off";
|
||||
m_test_source : integer := -1;
|
||||
c0_test_source : integer := -1;
|
||||
c1_test_source : integer := -1;
|
||||
c2_test_source : integer := -1;
|
||||
c3_test_source : integer := -1;
|
||||
c4_test_source : integer := -1;
|
||||
vco_multiply_by : integer := 0;
|
||||
vco_divide_by : integer := 0;
|
||||
vco_post_scale : integer := 1;
|
||||
vco_frequency_control : string := "auto";
|
||||
vco_phase_shift_step : integer := 0;
|
||||
charge_pump_current : integer := 10;
|
||||
loop_filter_r : string := " 1.0";
|
||||
loop_filter_c : integer := 0;
|
||||
pll_compensation_delay : integer := 0;
|
||||
simulation_type : string := "functional";
|
||||
lpm_type : string := "cycloneive_pll";
|
||||
clk0_use_even_counter_mode : string := "off";
|
||||
clk1_use_even_counter_mode : string := "off";
|
||||
clk2_use_even_counter_mode : string := "off";
|
||||
clk3_use_even_counter_mode : string := "off";
|
||||
clk4_use_even_counter_mode : string := "off";
|
||||
clk0_use_even_counter_value : string := "off";
|
||||
clk1_use_even_counter_value : string := "off";
|
||||
clk2_use_even_counter_value : string := "off";
|
||||
clk3_use_even_counter_value : string := "off";
|
||||
clk4_use_even_counter_value : string := "off";
|
||||
init_block_reset_a_count : integer := 1;
|
||||
init_block_reset_b_count : integer := 1;
|
||||
charge_pump_current_bits : integer := 0;
|
||||
lock_window_ui_bits : integer := 0;
|
||||
loop_filter_c_bits : integer := 0;
|
||||
loop_filter_r_bits : integer := 0;
|
||||
test_counter_c0_delay_chain_bits : integer := 0;
|
||||
test_counter_c1_delay_chain_bits : integer := 0;
|
||||
test_counter_c2_delay_chain_bits : integer := 0;
|
||||
test_counter_c3_delay_chain_bits : integer := 0;
|
||||
test_counter_c4_delay_chain_bits : integer := 0;
|
||||
test_counter_c5_delay_chain_bits : integer := 0;
|
||||
test_counter_m_delay_chain_bits : integer := 0;
|
||||
test_counter_n_delay_chain_bits : integer := 0;
|
||||
test_feedback_comp_delay_chain_bits : integer := 0;
|
||||
test_input_comp_delay_chain_bits : integer := 0;
|
||||
test_volt_reg_output_mode_bits : integer := 0;
|
||||
test_volt_reg_output_voltage_bits : integer := 0;
|
||||
test_volt_reg_test_mode : string := "false";
|
||||
vco_range_detector_high_bits : integer := -1;
|
||||
vco_range_detector_low_bits : integer := -1;
|
||||
scan_chain_mif_file : string := "";
|
||||
auto_settings : string := "true";
|
||||
family_name : string := "Cycloneive";
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
MsgOnChecks : Boolean := DefMsgOnChecks;
|
||||
XOnChecks : Boolean := DefXOnChecks;
|
||||
TimingChecksOn : Boolean := true;
|
||||
InstancePath : STRING := "*";
|
||||
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_fbin : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_scandata : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
|
||||
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
|
||||
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
|
||||
use_vco_bypass : string := "false"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
inclk : in std_logic_vector(1 downto 0);
|
||||
fbin : in std_logic := '0';
|
||||
fbout : out std_logic;
|
||||
clkswitch : in std_logic := '0';
|
||||
areset : in std_logic := '0';
|
||||
pfdena : in std_logic := '1';
|
||||
scandata : in std_logic := '0';
|
||||
scanclk : in std_logic := '0';
|
||||
scanclkena : in std_logic := '1';
|
||||
configupdate : in std_logic := '0';
|
||||
clk : out std_logic_vector(4 downto 0);
|
||||
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
|
||||
phaseupdown : in std_logic := '0';
|
||||
phasestep : in std_logic := '0';
|
||||
clkbad : out std_logic_vector(1 downto 0);
|
||||
activeclock : out std_logic;
|
||||
locked : out std_logic;
|
||||
scandataout : out std_logic;
|
||||
scandone : out std_logic;
|
||||
phasedone : out std_logic;
|
||||
vcooverrange : out std_logic;
|
||||
vcounderrange : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_ff
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_ff
|
||||
generic (
|
||||
power_up : string := "low";
|
||||
x_on_violation : string := "on";
|
||||
lpm_type : string := "cycloneive_ff";
|
||||
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_d : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_asdata : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sclr : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sload : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clrn : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_aload : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
TimingChecksOn: Boolean := True;
|
||||
MsgOn: Boolean := DefGlitchMsgOn;
|
||||
XOn: Boolean := DefGlitchXOn;
|
||||
MsgOnChecks: Boolean := DefMsgOnChecks;
|
||||
XOnChecks: Boolean := DefXOnChecks;
|
||||
InstancePath: STRING := "*"
|
||||
);
|
||||
port (
|
||||
d : in std_logic := '0';
|
||||
clk : in std_logic := '0';
|
||||
clrn : in std_logic := '1';
|
||||
aload : in std_logic := '0';
|
||||
sclr : in std_logic := '0';
|
||||
sload : in std_logic := '0';
|
||||
ena : in std_logic := '1';
|
||||
asdata : in std_logic := '0';
|
||||
devclrn : in std_logic := '1';
|
||||
devpor : in std_logic := '1';
|
||||
q : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_ram_block
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_ram_block
|
||||
GENERIC (
|
||||
operation_mode : STRING := "single_port";
|
||||
mixed_port_feed_through_mode : STRING := "dont_care";
|
||||
ram_block_type : STRING := "auto";
|
||||
logical_ram_name : STRING := "ram_name";
|
||||
init_file : STRING := "init_file.hex";
|
||||
init_file_layout : STRING := "none";
|
||||
data_interleave_width_in_bits : INTEGER := 1;
|
||||
data_interleave_offset_in_bits : INTEGER := 1;
|
||||
port_a_logical_ram_depth : INTEGER := 0;
|
||||
port_a_logical_ram_width : INTEGER := 0;
|
||||
port_a_first_address : INTEGER := 0;
|
||||
port_a_last_address : INTEGER := 0;
|
||||
port_a_first_bit_number : INTEGER := 0;
|
||||
port_a_address_clear : STRING := "none";
|
||||
port_a_data_out_clear : STRING := "none";
|
||||
port_a_data_in_clock : STRING := "clock0";
|
||||
port_a_address_clock : STRING := "clock0";
|
||||
port_a_write_enable_clock : STRING := "clock0";
|
||||
port_a_read_enable_clock : STRING := "clock0";
|
||||
port_a_byte_enable_clock : STRING := "clock0";
|
||||
port_a_data_out_clock : STRING := "none";
|
||||
port_a_data_width : INTEGER := 1;
|
||||
port_a_address_width : INTEGER := 1;
|
||||
port_a_byte_enable_mask_width : INTEGER := 1;
|
||||
port_b_logical_ram_depth : INTEGER := 0;
|
||||
port_b_logical_ram_width : INTEGER := 0;
|
||||
port_b_first_address : INTEGER := 0;
|
||||
port_b_last_address : INTEGER := 0;
|
||||
port_b_first_bit_number : INTEGER := 0;
|
||||
port_b_address_clear : STRING := "none";
|
||||
port_b_data_out_clear : STRING := "none";
|
||||
port_b_data_in_clock : STRING := "clock1";
|
||||
port_b_address_clock : STRING := "clock1";
|
||||
port_b_write_enable_clock: STRING := "clock1";
|
||||
port_b_read_enable_clock: STRING := "clock1";
|
||||
port_b_byte_enable_clock : STRING := "clock1";
|
||||
port_b_data_out_clock : STRING := "none";
|
||||
port_b_data_width : INTEGER := 1;
|
||||
port_b_address_width : INTEGER := 1;
|
||||
port_b_byte_enable_mask_width : INTEGER := 1;
|
||||
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
|
||||
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
|
||||
power_up_uninitialized : STRING := "false";
|
||||
port_b_byte_size : INTEGER := 0;
|
||||
port_a_byte_size : INTEGER := 0;
|
||||
safe_write : STRING := "err_on_2clk";
|
||||
init_file_restructured : STRING := "unused";
|
||||
lpm_type : string := "cycloneive_ram_block";
|
||||
lpm_hint : string := "true";
|
||||
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
|
||||
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
|
||||
clk0_output_clock_enable : STRING := "none"; -- ena0,none
|
||||
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
|
||||
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
|
||||
clk1_output_clock_enable : STRING := "none"; -- ena1,none
|
||||
mem_init0 : BIT_VECTOR := X"0";
|
||||
mem_init1 : BIT_VECTOR := X"0";
|
||||
mem_init2 : BIT_VECTOR := X"0";
|
||||
mem_init3 : BIT_VECTOR := X"0";
|
||||
mem_init4 : BIT_VECTOR := X"0";
|
||||
connectivity_checking : string := "off"
|
||||
);
|
||||
PORT (
|
||||
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
||||
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
||||
portawe : IN STD_LOGIC := '0';
|
||||
portare : IN STD_LOGIC := '1';
|
||||
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
|
||||
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
|
||||
portbwe : IN STD_LOGIC := '0';
|
||||
portbre : IN STD_LOGIC := '1';
|
||||
clk0 : IN STD_LOGIC := '0';
|
||||
clk1 : IN STD_LOGIC := '0';
|
||||
ena0 : IN STD_LOGIC := '1';
|
||||
ena1 : IN STD_LOGIC := '1';
|
||||
ena2 : IN STD_LOGIC := '1';
|
||||
ena3 : IN STD_LOGIC := '1';
|
||||
clr0 : IN STD_LOGIC := '0';
|
||||
clr1 : IN STD_LOGIC := '0';
|
||||
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
||||
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
|
||||
devclrn : IN STD_LOGIC := '1';
|
||||
devpor : IN STD_LOGIC := '1';
|
||||
portaaddrstall : IN STD_LOGIC := '0';
|
||||
portbaddrstall : IN STD_LOGIC := '0';
|
||||
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
|
||||
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_mac_mult
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_mac_mult
|
||||
GENERIC (
|
||||
dataa_width : integer := 18;
|
||||
datab_width : integer := 18;
|
||||
dataa_clock : string := "none";
|
||||
datab_clock : string := "none";
|
||||
signa_clock : string := "none";
|
||||
signb_clock : string := "none";
|
||||
TimingChecksOn : Boolean := True;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOnChecks : Boolean := DefMsgOnChecks;
|
||||
XOnChecks : Boolean := DefXOnChecks;
|
||||
InstancePath : STRING := "*";
|
||||
lpm_hint : string := "true";
|
||||
lpm_type : string := "cycloneive_mac_mult"
|
||||
);
|
||||
PORT (
|
||||
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
|
||||
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
|
||||
signa : IN std_logic := '1';
|
||||
signb : IN std_logic := '1';
|
||||
clk : IN std_logic := '0';
|
||||
aclr : IN std_logic := '0';
|
||||
ena : IN std_logic := '0';
|
||||
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
|
||||
devclrn : IN std_logic := '1';
|
||||
devpor : IN std_logic := '1'
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_mac_out
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_mac_out
|
||||
GENERIC (
|
||||
dataa_width : integer := 1;
|
||||
output_clock : string := "none";
|
||||
TimingChecksOn : Boolean := True;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOnChecks : Boolean := DefMsgOnChecks;
|
||||
XOnChecks : Boolean := DefXOnChecks;
|
||||
InstancePath : STRING := "*";
|
||||
tipd_dataa : VitalDelayArrayType01(35 downto 0)
|
||||
:= (OTHERS => DefPropDelay01);
|
||||
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_aclr : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
|
||||
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
|
||||
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
|
||||
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
|
||||
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
|
||||
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
|
||||
lpm_hint : string := "true";
|
||||
lpm_type : string := "cycloneive_mac_out");
|
||||
PORT (
|
||||
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
|
||||
clk : IN std_logic := '0';
|
||||
aclr : IN std_logic := '0';
|
||||
ena : IN std_logic := '1';
|
||||
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
|
||||
devclrn : IN std_logic := '1';
|
||||
devpor : IN std_logic := '1'
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_io_ibuf
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_io_ibuf
|
||||
GENERIC (
|
||||
tipd_i : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ibar : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
differential_mode : string := "false";
|
||||
bus_hold : string := "false";
|
||||
simulate_z_as : string := "Z";
|
||||
lpm_type : string := "cycloneive_io_ibuf"
|
||||
);
|
||||
PORT (
|
||||
i : IN std_logic := '0';
|
||||
ibar : IN std_logic := '0';
|
||||
o : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_io_obuf
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_io_obuf
|
||||
GENERIC (
|
||||
tipd_i : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_oe : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
|
||||
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
open_drain_output : string := "false";
|
||||
bus_hold : string := "false";
|
||||
lpm_type : string := "cycloneive_io_obuf"
|
||||
);
|
||||
PORT (
|
||||
i : IN std_logic := '0';
|
||||
oe : IN std_logic := '1';
|
||||
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
|
||||
devoe : IN std_logic := '1';
|
||||
o : OUT std_logic;
|
||||
obar : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_ddio_oe
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_ddio_oe
|
||||
generic(
|
||||
tipd_oe : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sreset : VitalDelayType01 := DefPropDelay01;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
power_up : string := "low";
|
||||
async_mode : string := "none";
|
||||
sync_mode : string := "none";
|
||||
lpm_type : string := "cycloneive_ddio_oe"
|
||||
);
|
||||
PORT (
|
||||
oe : IN std_logic := '1';
|
||||
clk : IN std_logic := '0';
|
||||
ena : IN std_logic := '1';
|
||||
areset : IN std_logic := '0';
|
||||
sreset : IN std_logic := '0';
|
||||
dataout : OUT std_logic;
|
||||
dfflo : OUT std_logic;
|
||||
dffhi : OUT std_logic;
|
||||
devclrn : IN std_logic := '1';
|
||||
devpor : IN std_logic := '1'
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_ddio_out
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_ddio_out
|
||||
generic(
|
||||
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clk : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_clklo : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_areset : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_sreset : VitalDelayType01 := DefPropDelay01;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
power_up : string := "low";
|
||||
async_mode : string := "none";
|
||||
sync_mode : string := "none";
|
||||
use_new_clocking_model : string := "false";
|
||||
lpm_type : string := "cycloneive_ddio_out"
|
||||
);
|
||||
PORT (
|
||||
datainlo : IN std_logic := '0';
|
||||
datainhi : IN std_logic := '0';
|
||||
clk : IN std_logic := '0';
|
||||
clkhi : IN std_logic := '0';
|
||||
clklo : IN std_logic := '0';
|
||||
muxsel : IN std_logic := '0';
|
||||
ena : IN std_logic := '1';
|
||||
areset : IN std_logic := '0';
|
||||
sreset : IN std_logic := '0';
|
||||
dataout : OUT std_logic;
|
||||
dfflo : OUT std_logic;
|
||||
dffhi : OUT std_logic ;
|
||||
devclrn : IN std_logic := '1';
|
||||
devpor : IN std_logic := '1'
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_pseudo_diff_out
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_pseudo_diff_out
|
||||
GENERIC (
|
||||
tipd_i : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_i_o : VitalDelayType01 := DefPropDelay01;
|
||||
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
lpm_type : string := "cycloneive_pseudo_diff_out"
|
||||
);
|
||||
PORT (
|
||||
i : IN std_logic := '0';
|
||||
o : OUT std_logic;
|
||||
obar : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_io_pad
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_io_pad
|
||||
GENERIC (
|
||||
lpm_type : string := "cycloneive_io_pad");
|
||||
PORT (
|
||||
padin : IN std_logic := '0'; -- Input Pad
|
||||
padout : OUT std_logic); -- Output Pad
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_asmiblock
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_asmiblock
|
||||
generic (
|
||||
lpm_type : string := "cycloneive_asmiblock";
|
||||
enable_sim : string := "false"
|
||||
);
|
||||
port (
|
||||
dclkin : in std_logic;
|
||||
scein : in std_logic;
|
||||
oe : in std_logic;
|
||||
sdoin : in std_logic;
|
||||
data0out: out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_clkctrl
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_clkctrl
|
||||
generic (
|
||||
clock_type : STRING := "Auto";
|
||||
lpm_type : STRING := "cycloneive_clkctrl";
|
||||
ena_register_mode : STRING := "Falling Edge";
|
||||
TimingChecksOn : Boolean := True;
|
||||
MsgOn : Boolean := DefGlitchMsgOn;
|
||||
XOn : Boolean := DefGlitchXOn;
|
||||
MsgOnChecks : Boolean := DefMsgOnChecks;
|
||||
XOnChecks : Boolean := DefXOnChecks;
|
||||
InstancePath : STRING := "*";
|
||||
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
||||
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
|
||||
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
|
||||
tipd_ena : VitalDelayType01 := DefPropDelay01
|
||||
);
|
||||
port (
|
||||
inclk : in std_logic_vector(3 downto 0) := "0000";
|
||||
clkselect : in std_logic_vector(1 downto 0) := "00";
|
||||
ena : in std_logic := '1';
|
||||
devclrn : in std_logic := '1';
|
||||
devpor : in std_logic := '1';
|
||||
outclk : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_rublock
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_rublock
|
||||
generic
|
||||
(
|
||||
sim_init_config : string := "factory";
|
||||
sim_init_watchdog_value : integer := 0;
|
||||
sim_init_status : integer := 0;
|
||||
lpm_type : string := "cycloneive_rublock"
|
||||
);
|
||||
port
|
||||
(
|
||||
clk : in std_logic;
|
||||
shiftnld : in std_logic;
|
||||
captnupdt : in std_logic;
|
||||
regin : in std_logic;
|
||||
rsttimer : in std_logic;
|
||||
rconfig : in std_logic;
|
||||
regout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_apfcontroller
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_apfcontroller
|
||||
generic
|
||||
(
|
||||
lpm_type: string := "cycloneive_apfcontroller"
|
||||
);
|
||||
port
|
||||
(
|
||||
usermode : out std_logic;
|
||||
nceout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_termination
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_termination
|
||||
GENERIC (
|
||||
pullup_control_to_core: string := "false";
|
||||
power_down : string := "true";
|
||||
test_mode : string := "false";
|
||||
left_shift_termination_code : string := "false";
|
||||
pullup_adder : integer := 0;
|
||||
pulldown_adder : integer := 0;
|
||||
clock_divide_by : integer := 32; -- 1, 4, 32
|
||||
runtime_control : string := "false";
|
||||
shift_vref_rup : string := "true";
|
||||
shift_vref_rdn : string := "true";
|
||||
shifted_vref_control : string := "true";
|
||||
lpm_type : string := "cycloneive_termination");
|
||||
PORT (
|
||||
rup : IN std_logic := '0';
|
||||
rdn : IN std_logic := '0';
|
||||
terminationclock : IN std_logic := '0';
|
||||
terminationclear : IN std_logic := '0';
|
||||
devpor : IN std_logic := '1';
|
||||
devclrn : IN std_logic := '1';
|
||||
comparatorprobe : OUT std_logic;
|
||||
terminationcontrolprobe : OUT std_logic;
|
||||
calibrationdone : OUT std_logic;
|
||||
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_jtag
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_jtag
|
||||
generic (
|
||||
lpm_type : string := "cycloneive_jtag"
|
||||
);
|
||||
port (
|
||||
tms : in std_logic := '0';
|
||||
tck : in std_logic := '0';
|
||||
tdi : in std_logic := '0';
|
||||
tdoutap : in std_logic := '0';
|
||||
tdouser : in std_logic := '0';
|
||||
tdo: out std_logic;
|
||||
tmsutap: out std_logic;
|
||||
tckutap: out std_logic;
|
||||
tdiutap: out std_logic;
|
||||
shiftuser: out std_logic;
|
||||
clkdruser: out std_logic;
|
||||
updateuser: out std_logic;
|
||||
runidleuser: out std_logic;
|
||||
usr1user: out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_crcblock
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_crcblock
|
||||
generic (
|
||||
oscillator_divider : integer := 1;
|
||||
lpm_type : string := "cycloneive_crcblock"
|
||||
);
|
||||
port (
|
||||
clk : in std_logic := '0';
|
||||
shiftnld : in std_logic := '0';
|
||||
ldsrc : in std_logic := '0';
|
||||
crcerror : out std_logic;
|
||||
regout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- cycloneive_oscillator
|
||||
--
|
||||
|
||||
COMPONENT cycloneive_oscillator
|
||||
generic
|
||||
(
|
||||
lpm_type: string := "cycloneive_oscillator";
|
||||
TimingChecksOn: Boolean := True;
|
||||
XOn: Boolean := DefGlitchXOn;
|
||||
MsgOn: Boolean := DefGlitchMsgOn;
|
||||
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
|
||||
tipd_oscena : VitalDelayType01 := DefPropDelay01
|
||||
);
|
||||
port
|
||||
(
|
||||
oscena : in std_logic;
|
||||
clkout : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
end cycloneive_components;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,34 +0,0 @@
|
||||
|
||||
|
||||
if {![file exists build]} {mkdir build}
|
||||
cd build
|
||||
if {![file exists altera]} {mkdir altera}
|
||||
cd altera
|
||||
|
||||
if {[file exists altera]} {vdel -lib altera -all}
|
||||
|
||||
vlib altera
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives_components.vhd
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives.vhd
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_internal_syn.vhd
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_europa_support_lib.vhd
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_standard_functions.vhd
|
||||
vcom -93 -work altera ../../altera/libsrc/altera/altera_syn_attributes.vhd
|
||||
|
||||
vlib altera_mf
|
||||
vcom -93 -work altera_mf ../../altera/libsrc/altera_mf/altera_mf_components.vhd
|
||||
vcom -93 -work altera_mf ../../altera/libsrc/altera_mf/altera_mf.vhd
|
||||
|
||||
vlib cycloneive
|
||||
vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_atoms.vhd
|
||||
vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_components.vhd
|
||||
|
||||
vlib altera_lnsim
|
||||
vcom -93 -work altera_lnsim ../../altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
|
||||
|
||||
vlib cyclonev
|
||||
vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_atoms.vhd
|
||||
vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_components.vhd
|
||||
|
||||
cd ..
|
||||
cd ..
|
||||
@@ -1,22 +0,0 @@
|
||||
#
|
||||
# Compile script for Modeltech
|
||||
#
|
||||
|
||||
if {![file exists build]} {mkdir build}
|
||||
cd build
|
||||
|
||||
if {![file exists modelsim]} {mkdir modelsim}
|
||||
cd modelsim
|
||||
|
||||
if {[file exists modelsim]} {vdel -lib modelsim -all}
|
||||
|
||||
vlib ieee_proposed
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_additions_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_textio_additions_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/env_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/std_logic_1164_additions.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_additions.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_float_types_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_pkg_c.vhdl
|
||||
vcom -work ieee_proposed ../../ieee_proposed/modelsim/float_pkg_c.vhdl
|
||||
@@ -1,9 +0,0 @@
|
||||
vlib build
|
||||
vlib build/xilinx
|
||||
|
||||
vlib build/xilinx/simprim
|
||||
|
||||
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
|
||||
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
|
||||
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
|
||||
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd
|
||||
@@ -1,15 +0,0 @@
|
||||
if {![file exists build]} {mkdir build}
|
||||
cd build
|
||||
if {![file exists xilinx]} {mkdir xilinx}
|
||||
cd xilinx
|
||||
|
||||
if {[file exists unisim]} {vdel -lib unisim -all}
|
||||
vlib unisim
|
||||
|
||||
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vpkg.vhd
|
||||
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vcomp.vhd
|
||||
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_smodel.vhd
|
||||
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vital.vhd
|
||||
|
||||
cd ..
|
||||
cd ..
|
||||
@@ -1,28 +0,0 @@
|
||||
# -------------------------------------------------
|
||||
# Compile script for GHDL
|
||||
# -------------------------------------------------
|
||||
include ../make/defs.mk
|
||||
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
|
||||
WORK_LIB := ieee_proposed
|
||||
TARGET := ieee_proposed
|
||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
SRCS := $(LIB_PATH)/standard_additions_c.vhdl
|
||||
SRCS += $(LIB_PATH)/standard_textio_additions_c.vhdl
|
||||
SRCS += $(LIB_PATH)/env_c.vhdl
|
||||
SRCS += $(LIB_PATH)/std_logic_1164_additions.vhdl
|
||||
SRCS += $(LIB_PATH)/numeric_std_additions.vhdl
|
||||
SRCS += $(LIB_PATH)/numeric_std_unsigned_c.vhdl
|
||||
SRCS += $(LIB_PATH)/fixed_float_types_c.vhdl
|
||||
SRCS += $(LIB_PATH)/fixed_pkg_c.vhdl
|
||||
SRCS += $(LIB_PATH)/float_pkg_c.vhdl
|
||||
|
||||
include ../make/ghdl.mk
|
||||
|
||||
@@ -1,173 +0,0 @@
|
||||
|
||||
This is the "ieee_proposed" library. This is a compatability library,
|
||||
which is designed to provide all of the functionality of the VHDL-200X-FT
|
||||
packages in VHDL-93. The "_c" after the package name is used to denote
|
||||
that this is a 1993 compliant version of this package. Otherwise, the
|
||||
name of the file and the name of the package are the same.
|
||||
|
||||
Please compile the following files into a library named "ieee_proposed":
|
||||
standard_additions_c.vhdl
|
||||
env_c.vhdl
|
||||
standard_textio_additions_c.vhdl
|
||||
std_logic_1164_additions.vhdl
|
||||
numeric_std_additions.vhdl
|
||||
numeric_std_unsigned_c.vhdl
|
||||
fixed_pkg_c.vhdl
|
||||
float_pkg_c.vhdl
|
||||
|
||||
|
||||
New/Updated functions
|
||||
A) standard_additions -- Additions to the package "std.standard"
|
||||
Use model:
|
||||
use ieee_proposed.standard_additions.all;
|
||||
Dependancies: None.
|
||||
Notes: The functions "rising_edge" and "falling_edge" are defined in
|
||||
this package. If you use "numeric_bit" they are ALSO defined in that
|
||||
package, causing a conflict. The VHDL-200X-FT version of numeric_bit
|
||||
has these functions commented out, as well as the "sll", "srl", "ror"
|
||||
and "rol" functions which are implicit.
|
||||
New types defined in this package:
|
||||
REAL_VECTOR
|
||||
TIME_VECTOR
|
||||
INTEGER_VECTOR
|
||||
BOOLEAN_VECTOR
|
||||
New constants defined in this package:
|
||||
SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
|
||||
1) "maximum" and "minimum" are defined for all default datatypes
|
||||
2) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
|
||||
These functions reduce a bit_vector to a single bit. Example:
|
||||
or_reduce ("0101") = '1'. In VHDL-2006 syntax these will be "or".
|
||||
3) "vector" and "bit" operations are defined. These will perform a
|
||||
boolean operation of a vector. Example:
|
||||
"1" xor "1010" = "0101";
|
||||
5) /??/ function is defined for "bit" ("??" operator is release)
|
||||
if (/??/('1')) then -- will return a "true".
|
||||
6) rising_edge and falling_edge functions are defined (see Notes).
|
||||
7) to_string function - Converts any of the base types into a string.
|
||||
Example:
|
||||
assert (bv = "101") report "result was " & to_string(bv) severity note;
|
||||
8) to_hstring and to_ostring function (bit_vector to hex or octal string)
|
||||
B) standard_textio_additions - Additions to the package "std.textio"
|
||||
Use model:
|
||||
use ieee_proposed.standard_textio_additions.all;
|
||||
Dependencies: std.textio, ieee_proposed.standard_additions
|
||||
1) tee - Echos the string to BOTH the file and the screen
|
||||
2) SREAD and SWRITE - String read and write routines (so you no longer
|
||||
need to do write (L, string'("ABCEDFG"));
|
||||
3) HREAD and HWRITE (Hex read and write) for bit_vector
|
||||
4) OREAD and OWRITE (octal read and write) for bit_vector
|
||||
5) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
|
||||
bit_vector
|
||||
6) justify - Justify a string left or right with a width. Example:
|
||||
justify ("ABCD", left, 6); will result in "ABCD "
|
||||
C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
|
||||
Usage model:
|
||||
use ieee.std_logic_1164.all;
|
||||
-- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
|
||||
use ieee_proposed.std_logic_1164_additions.all;
|
||||
Dependencies: ieee.std_logic_1164
|
||||
Note: The contents of the "std_logic_textio" package have now been
|
||||
included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
|
||||
package is provided in the new release.
|
||||
1) Short had aliases:
|
||||
a) to_bv - calls "to_BitVector"
|
||||
b) to_slv - calls "to_StdLogicVector"
|
||||
c) to_sulv - calls "to_stdULogicVector"
|
||||
2) Long hand aliases:
|
||||
a) to_bit_vector - calls "to_BitVector"
|
||||
b) to_std_logic_vector - calls "to_StdLogicVector"
|
||||
c) to_std_ulogic_vector - calls "to_StdULogicVector"
|
||||
3) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
|
||||
These functions reduce a std_logic_vector (or ulogic) to a single bit.
|
||||
In vhdl-2006 these will be unary "or", example "or "11011" = '1'"
|
||||
4) "vector" and "std_ulogic" operations are defined. These will perform a
|
||||
boolean operation of a vector. Example:
|
||||
"1" xor "1010" = "0101";
|
||||
5) "std_ulogic" and "boolean" operations are defined. Thus:
|
||||
if '1' and true then -- returns a "true".
|
||||
6) "\??\" function is defined for "std_ulogic" ("??" operator is release)
|
||||
if (bool('1')) then -- will return a "true".
|
||||
7) READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
|
||||
and "std_ulogic" are defined.
|
||||
8) HREAD and HWRITE (Hex read and write) for std_logic_vector
|
||||
and std_ulogic_vector. These are more "forgiving" than the ones
|
||||
originally from "std_logic_textio"
|
||||
9) OREAD and OWRITE (octal read and write) for std_logic_vector
|
||||
and std_ulogic_vector. These are more "forgiving" than the ones
|
||||
originally from "std_logic_textio"
|
||||
10) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
|
||||
std_logic_vector and std_ulogic_vector.
|
||||
11) to_string function - Converts a "std_ulogic", "std_logic_vector" or
|
||||
"std_ulogic_vector" types into a string.
|
||||
Example:
|
||||
assert (slv = "101") report "result was " & to_string(slv) severity note;
|
||||
12) to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
|
||||
string)
|
||||
D) numeric_std_additions - additions the the package "ieee.numeric_std"
|
||||
Usage Model:
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.numeric_std_additions.all;
|
||||
Dependencies: ieee.std_logic_1164, ieee.numeric_std
|
||||
1) SIGNED or UNSIGNED + std_ulogic operators
|
||||
2) SIGNED or UNSIGNED - std_ulogic operators
|
||||
3) type UNRESOLVED_UNSIGNED (aliased to U_UNSIGNED) is an unresolved
|
||||
verion of UNSIGNED. It is aliased to "UNSIGNED" for compatability.
|
||||
4) type UNRESOLVED_SIGNED (aliased to U_SIGNED) is an unresolved
|
||||
verion of SIGNED. It is aliased to "SIGNED" for compatability.
|
||||
5) \?=\, \?/=\ - similar to "std_match", but return std_ulogic values.
|
||||
\?<\, \?<=\, \?>\, \?>=\ - compare functions which retrun std_ulogic.
|
||||
(these will be "?="... operators in the release)
|
||||
7) To_X01, To_X01Z, To_U01X, Is_X - same as std_logic_1164 functions,
|
||||
but overloaded for SIGNED and UNSIGNED.
|
||||
8) "sla" and "sra" - Mathmetically correct versions of these functions.
|
||||
9) minimum and maximum - smaller or larger of two SIGNED or UNSIGNED values.
|
||||
10) find_rightmost and find_leftmost - finds the first bit in a string.
|
||||
Example:
|
||||
find_leftmost (c12, '1'); -- returns the Log2 of "c12".
|
||||
returns -1 if not found.
|
||||
11) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
|
||||
These functions reduce a SIGNED or an UNSIGNED to a single bit.
|
||||
(will overload the "or" and "and", ... operators in the release)
|
||||
12) SIGNED or UNSIGNED and "std_ulogic" operations are defined.
|
||||
These will perform a boolean operation of a vector. Example:
|
||||
"1" xor "1010" = "0101";
|
||||
13) READ and WRITE procedures for "SIGNED", and "UNSIGNED" are defined.
|
||||
14) HREAD and HWRITE (Hex read and write) for SIGNED and UNSIGNED.
|
||||
These are more "forgiving" than the ones
|
||||
originally from "std_logic_textio"
|
||||
15) OREAD and OWRITE (octal read and write) for "SIGNED" and "UNSIGNED.
|
||||
These are more "forgiving" than the ones
|
||||
originally from "std_logic_textio"
|
||||
16) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
|
||||
SIGNED and UNSIGNED.
|
||||
17) to_string function - Converts a "SIGNED" or "UNSIGNED" types into a
|
||||
string. Example:
|
||||
assert (UNS = "101") report "result was " & to_string(UNS) severity note;
|
||||
18) to_hstring and to_ostring function (SIGNED or UNSIGNED to hex or octal
|
||||
string)
|
||||
E) numeric_std_unsigned - Simular to the "std_logic_unsigned" packages, but
|
||||
with all of the functionality of the "numeric_std" package.
|
||||
use model:
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee_proposed.numeric_std_unsigned.all;
|
||||
dependencies: ieee.numeric_std, ieee_proposed.numeric_std_additions
|
||||
|
||||
F) For fixed point package:
|
||||
use model:
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_float_types.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
See fixed point package documentation
|
||||
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
|
||||
|
||||
G) For floating point package:
|
||||
use model:
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_float_types.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
use ieee_proposed.float_pkg.all;
|
||||
See floating point package documentation
|
||||
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf
|
||||
@@ -1,14 +0,0 @@
|
||||
#
|
||||
# Compile script for Modeltech
|
||||
#
|
||||
vlib ieee_proposed.lib
|
||||
vmap ieee_proposed ieee_proposed.lib
|
||||
vcom -work ieee_proposed standard_additions_c.vhdl
|
||||
vcom -work ieee_proposed standard_textio_additions_c.vhdl
|
||||
vcom -work ieee_proposed env_c.vhdl
|
||||
vcom -work ieee_proposed std_logic_1164_additions.vhdl
|
||||
vcom -work ieee_proposed numeric_std_additions.vhdl
|
||||
vcom -work ieee_proposed numeric_std_unsigned_c.vhdl
|
||||
vcom -work ieee_proposed fixed_float_types_c.vhdl
|
||||
vcom -work ieee_proposed fixed_pkg_c.vhdl
|
||||
vcom -work ieee_proposed float_pkg_c.vhdl
|
||||
@@ -1,48 +0,0 @@
|
||||
package ENV is
|
||||
|
||||
procedure STOP (STATUS : INTEGER);
|
||||
procedure FINISH (STATUS : INTEGER);
|
||||
|
||||
function RESOLUTION_LIMIT return DELAY_LENGTH;
|
||||
|
||||
end package ENV;
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.standard_additions.all;
|
||||
package body ENV is
|
||||
|
||||
procedure STOP (STATUS : INTEGER) is
|
||||
begin
|
||||
report "Procedure STOP called with status: " & INTEGER'image(STATUS)
|
||||
severity failure;
|
||||
end procedure STOP;
|
||||
procedure FINISH (STATUS : INTEGER) is
|
||||
begin
|
||||
report "Procedure FINISH called with status: " & INTEGER'image(STATUS)
|
||||
severity failure;
|
||||
end procedure FINISH;
|
||||
|
||||
constant BASE_TIME_ARRAY : time_vector :=
|
||||
(
|
||||
1 fs, 10 fs, 100 fs,
|
||||
1 ps, 10 ps, 100 ps,
|
||||
1 ns, 10 ns, 100 ns,
|
||||
1 us, 10 us, 100 us,
|
||||
1 ms, 10 ms, 100 ms,
|
||||
1 sec, 10 sec, 100 sec,
|
||||
1 min, 10 min, 100 min,
|
||||
1 hr, 10 hr, 100 hr
|
||||
) ;
|
||||
|
||||
function RESOLUTION_LIMIT return DELAY_LENGTH is
|
||||
begin
|
||||
for i in BASE_TIME_ARRAY'range loop
|
||||
if BASE_TIME_ARRAY(i) > 0 hr then
|
||||
return BASE_TIME_ARRAY(i);
|
||||
end if;
|
||||
end loop;
|
||||
report "STANDATD.RESOLUTION_LIMIT: Simulator resolution not less than 100 hr"
|
||||
severity failure;
|
||||
return 1 ns;
|
||||
end function RESOLUTION_LIMIT;
|
||||
|
||||
end package body ENV;
|
||||
@@ -1,34 +0,0 @@
|
||||
-- --------------------------------------------------------------------
|
||||
-- "fixed_float_types" package contains types used in the fixed and floating
|
||||
-- point packages..
|
||||
-- Please see the documentation for the floating point package.
|
||||
-- This package should be compiled into "ieee_proposed" and used as follows:
|
||||
--
|
||||
-- This verison is designed to work with the VHDL-93 compilers. Please
|
||||
-- note the "%%%" comments. These are where we diverge from the
|
||||
-- VHDL-200X LRM.
|
||||
--
|
||||
-- --------------------------------------------------------------------
|
||||
-- Version : $Revision: 1.1 $
|
||||
-- Date : $Date: 2010/09/22 18:44:20 $
|
||||
-- --------------------------------------------------------------------
|
||||
|
||||
package fixed_float_types is
|
||||
|
||||
-- Types used for generics of fixed_generic_pkg
|
||||
|
||||
type fixed_round_style_type is (fixed_round, fixed_truncate);
|
||||
|
||||
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
|
||||
|
||||
-- Type used for generics of float_generic_pkg
|
||||
|
||||
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
|
||||
-- and FE_TOWARDZERO floating point rounding macros.
|
||||
|
||||
type round_type is (round_nearest, -- Default, nearest LSB '0'
|
||||
round_inf, -- Round toward positive infinity
|
||||
round_neginf, -- Round toward negative infinity
|
||||
round_zero); -- Round toward zero (truncate)
|
||||
|
||||
end package fixed_float_types;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,736 +0,0 @@
|
||||
-- Synthesis test for the fixed point math package
|
||||
-- This test is designed to be synthesizable and exercise much of the package.
|
||||
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
|
||||
-- --------------------------------------------------------------------
|
||||
-- modification history : Last Modified $Date: 2006-06-08 10:49:35-04 $
|
||||
-- Version $Id: fixed_synth.vhdl,v 1.1 2006-06-08 10:49:35-04 l435385 Exp $
|
||||
-- --------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee, ieee_proposed;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_float_types.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
entity fixed_synth is
|
||||
|
||||
port (
|
||||
in1, in2 : in STD_LOGIC_VECTOR (15 downto 0); -- inputs
|
||||
out1 : out STD_LOGIC_VECTOR (15 downto 0); -- output
|
||||
cmd : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
clk, rst_n : in STD_ULOGIC); -- clk and reset
|
||||
|
||||
end entity fixed_synth;
|
||||
|
||||
architecture rtl of fixed_synth is
|
||||
|
||||
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
|
||||
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
|
||||
type cmd_type is array (1 to 15) of STD_ULOGIC_VECTOR (cmd'range); -- cmd
|
||||
signal cmdarray : cmd_type; -- command pipeline
|
||||
type cry_type is array (0 to 4) of sfixed16; -- arrays
|
||||
signal outarray0, outarray1, outarray2, outarray3, outarray4,
|
||||
outarray5, outarray6, outarray7, outarray8, outarray9, outarray10,
|
||||
outarray11, outarray12, outarray13, outarray14, outarray15 : sfixed16;
|
||||
signal in1reg3, in2reg3 : sfixed16; -- register stages
|
||||
begin -- architecture rtl
|
||||
|
||||
-- purpose: "0000" test the "+" operator
|
||||
cmd0reg : process (clk, rst_n) is
|
||||
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
|
||||
SFixed_low(7, -8, '+', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray0 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray0 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1pin2 := in1array(3) + in2array(3);
|
||||
outarray(0) := resize (in1pin2, outarray(0));
|
||||
end if;
|
||||
end process cmd0reg;
|
||||
|
||||
-- purpose: "0001" test the "-" operator
|
||||
cmd1reg : process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
variable in1min2 : sfixed (SFixed_high(in1array(0), '-', in2array(0)) downto
|
||||
SFixed_low(in1array(0), '-', in2array(0)));
|
||||
-- variable in1min2 : sfixed (SFixed_high(7, -8, '-', 7, -8) downto
|
||||
-- SFixed_low(7, -8, '-', 7, -8));
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray1 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray1 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1min2 := in1array(3) - in2array(3);
|
||||
outarray(0) := resize (in1min2, outarray(0));
|
||||
end if;
|
||||
end process cmd1reg;
|
||||
|
||||
-- purpose: "0010" test the "*" operator
|
||||
cmd2reg : process (clk, rst_n) is
|
||||
-- variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto
|
||||
-- SFixed_low(in1reg3, '*', in2reg3));
|
||||
variable in1min2 : sfixed (SFixed_high(7, -8, '*', 7, -8) downto
|
||||
SFixed_low(7, -8, '*', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray2 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray2 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1min2 := in1array(3) * in2array(3);
|
||||
outarray(0) := resize (in1min2, outarray(0));
|
||||
end if;
|
||||
end process cmd2reg;
|
||||
|
||||
-- purpose: "0011" test the "/" operator
|
||||
cmd3reg : process (clk, rst_n) is
|
||||
variable in1min2 : sfixed (SFixed_high(in1reg3'high, in1reg3'low,
|
||||
'/', in2reg3'high, in2reg3'low)
|
||||
downto
|
||||
SFixed_low(in1reg3'high, in1reg3'low,
|
||||
'/', in2reg3'high, in2reg3'low));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd3reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray3 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := to_sfixed(1, in2array(0));
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray3 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
if (in2reg3 = 0) then
|
||||
in2array(0) := to_sfixed(1, in2array(0));
|
||||
else
|
||||
in2array(0) := in2reg3;
|
||||
end if;
|
||||
in1min2 := in1array(3) / in2array(3);
|
||||
outarray(0) := resize (in1min2, outarray(0));
|
||||
end if;
|
||||
end process cmd3reg;
|
||||
|
||||
-- purpose: "0100" test the "+" operator
|
||||
cmd4reg : process (clk, rst_n) is
|
||||
variable in1pin2 : ufixed (uFixed_high(7, -8, '+', 7, -8) downto
|
||||
uFixed_low(7, -8, '+', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray4 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray4 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1pin2 := ufixed(in1array(3)) + ufixed(in2array(3));
|
||||
outarray(0) := sfixed (resize (in1pin2, outarray4'high, outarray4'low));
|
||||
end if;
|
||||
end process cmd4reg;
|
||||
|
||||
-- purpose: "0101" test the "-" operator
|
||||
cmd5reg : process (clk, rst_n) is
|
||||
variable in1min2 : ufixed (uFixed_high(7, -8, '-', 7, -8) downto
|
||||
uFixed_low(7, -8, '-', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray5 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray5 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1min2 := ufixed(in1array(3)) - ufixed(in2array(3));
|
||||
outarray(0) := sfixed(resize (in1min2, outarray5'high, outarray5'low));
|
||||
end if;
|
||||
end process cmd5reg;
|
||||
|
||||
-- purpose: "0110" test the "*" operator
|
||||
cmd6reg : process (clk, rst_n) is
|
||||
variable in1min2 : ufixed (uFixed_high(7, -8, '*', 7, -8) downto
|
||||
uFixed_low(7, -8, '*', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray6 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray6 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
in1min2 := ufixed(in1array(3)) * ufixed(in2array(3));
|
||||
outarray(0) := sfixed(resize (in1min2, outarray6'high, outarray6'low));
|
||||
end if;
|
||||
end process cmd6reg;
|
||||
|
||||
-- purpose: "0111" test the "/" operator
|
||||
cmd7reg : process (clk, rst_n) is
|
||||
variable in1min2 : ufixed (uFixed_high(7, -8, '/', 7, -8) downto
|
||||
uFixed_low(7, -8, '/', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray7 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray7 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
if (in2reg3 = 0) then
|
||||
in2array(0) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
|
||||
else
|
||||
in2array(0) := in2reg3;
|
||||
end if;
|
||||
in1min2 := ufixed(in1array(3)) / ufixed(in2array(3));
|
||||
outarray(0) := sfixed(resize (in1min2, outarray7'high, outarray7'low));
|
||||
end if;
|
||||
end process cmd7reg;
|
||||
|
||||
-- purpose: "1000" test the resize test
|
||||
cmd8reg : process (clk, rst_n) is
|
||||
variable tmpfp71, tmpfp72 : sfixed7; -- 8 bit fp number
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray8 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray8 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
-- Resize test Convert inputs into two 8 bit numbers
|
||||
tmpfp71 := resize (in1array(3), tmpfp71'high, tmpfp71'low,
|
||||
fixed_wrap, fixed_truncate);
|
||||
tmpfp72 := resize (in2array(3), tmpfp72'high, tmpfp72'low,
|
||||
fixed_saturate, fixed_round);
|
||||
outarray(0) := (others => '0');
|
||||
fx1 : for i in tmpfp71'range loop
|
||||
outarray(0)(i+4) := tmpfp71(i);
|
||||
end loop fx1;
|
||||
fx2 : for i in tmpfp72'range loop
|
||||
outarray(0)(i-4) := tmpfp72(i);
|
||||
end loop fx2;
|
||||
end if;
|
||||
end process cmd8reg;
|
||||
|
||||
-- purpose: "1001" test the to_signed/unsigned test
|
||||
cmd9reg : process (clk, rst_n) is
|
||||
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
|
||||
variable tmpsig : SIGNED (7 downto 0); -- signed number
|
||||
variable tmpuns : UNSIGNED (15 downto 0); -- unsigned number
|
||||
variable tmpint : INTEGER;
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray9 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray9 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
|
||||
if (tmp = "00") then
|
||||
-- Signed to sfixed and back
|
||||
tmpsig := to_signed (in1array(3), tmpsig'length);
|
||||
outarray(0) := to_sfixed (tmpsig, outarray(0));
|
||||
elsif (tmp = "01") then
|
||||
-- unsigned to ufixed and back
|
||||
tmpuns := to_unsigned (ufixed(in1array(3)), tmpuns'length);
|
||||
outarray(0) := sfixed(to_ufixed (tmpuns, outarray(0)'high,
|
||||
outarray(0)'low));
|
||||
elsif (tmp = "10") then
|
||||
tmpint := to_integer (in1array(3));
|
||||
outarray(0) := to_sfixed (tmpint, outarray(0));
|
||||
else
|
||||
tmpint := to_integer (ufixed(in1array(3)));
|
||||
outarray(0) := sfixed(to_ufixed (tmpint, outarray(0)'high,
|
||||
outarray(0)'low));
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process cmd9reg;
|
||||
|
||||
-- purpose: "1010" test the reciprocal, abs, - test
|
||||
cmd10reg : process (clk, rst_n) is
|
||||
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
|
||||
variable in1recip : sfixed (-in1reg3'low+1 downto -in1reg3'high);
|
||||
variable uin1recip : ufixed (-in1reg3'low downto -in1reg3'high-1);
|
||||
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
|
||||
SFixed_low(7, -8, '+', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray10 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := to_sfixed(1, in1reg3);
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray10 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
if (in1reg3 = 0) then
|
||||
in1array(0) := to_sfixed(1, in1reg3);
|
||||
else
|
||||
in1array(0) := in1reg3;
|
||||
end if;
|
||||
in2array(0) := in2reg3;
|
||||
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
|
||||
if (tmp = "00") then
|
||||
in1recip := reciprocal (in1array(3));
|
||||
outarray(0) := resize (in1recip, outarray(0)'high,
|
||||
outarray(0)'low);
|
||||
elsif (tmp = "01") then
|
||||
uin1recip := reciprocal (ufixed(in1array(3)));
|
||||
outarray(0) := sfixed(resize (uin1recip, outarray(0)'high,
|
||||
outarray(0)'low));
|
||||
elsif (tmp = "10") then
|
||||
-- abs
|
||||
in1pin2 := abs(in1array(3));
|
||||
outarray(0) := resize (in1pin2,
|
||||
outarray(0)'high,
|
||||
outarray(0)'low);
|
||||
else
|
||||
-- -
|
||||
in1pin2 := - in1array(3);
|
||||
outarray(0) := resize (in1pin2,
|
||||
outarray(0)'high,
|
||||
outarray(0)'low);
|
||||
end if;
|
||||
end if;
|
||||
end process cmd10reg;
|
||||
|
||||
-- purpose: "1011" test the mod operator
|
||||
cmd11reg : process (clk, rst_n) is
|
||||
variable in1min2 : sfixed (SFixed_high(7, -8, 'M', 7, -8) downto
|
||||
SFixed_low(7, -8, 'm', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray11 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := to_sfixed(1, in2array(0));
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray11 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
if (in2reg3 = 0) then
|
||||
in2array(0) := to_sfixed(1, in2array(0));
|
||||
else
|
||||
in2array(0) := in2reg3;
|
||||
end if;
|
||||
in1min2 := in1array(3) mod in2array(3);
|
||||
outarray(0) := resize (in1min2, outarray(0));
|
||||
end if;
|
||||
end process cmd11reg;
|
||||
|
||||
-- purpose: "1100" test the rem operator
|
||||
cmd12reg : process (clk, rst_n) is
|
||||
variable in1min2 : sfixed (SFixed_high(7, -8, 'R', 7, -8) downto
|
||||
SFixed_low(7, -8, 'r', 7, -8));
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray12 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := to_sfixed(1, in2array(0));
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray12 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
if (in2reg3 = 0) then
|
||||
in2array(0) := to_sfixed(1, in2array(0));
|
||||
else
|
||||
in2array(0) := in2reg3;
|
||||
end if;
|
||||
in1min2 := in1array(3) rem in2array(3);
|
||||
outarray(0) := resize (in1min2, outarray(0));
|
||||
end if;
|
||||
end process cmd12reg;
|
||||
|
||||
-- purpose: "1101" test the srl operator
|
||||
cmd13reg : process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray13 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray13 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
outarray(0) := in1array(3) srl to_integer(in2array(3));
|
||||
end if;
|
||||
end process cmd13reg;
|
||||
|
||||
-- purpose: "1110" test the sra operator
|
||||
cmd14reg : process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray14 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray14 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
outarray(0) := in1array(3) sra to_integer(in2array(3));
|
||||
end if;
|
||||
end process cmd14reg;
|
||||
|
||||
-- purpose: "1111" test the sra operator
|
||||
cmd15reg : process (clk, rst_n) is
|
||||
constant match_data : sfixed16 := "01HL----10HL----"; -- for ?= command
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable in1array, in2array : cry_type; -- array for input
|
||||
begin -- process cmd0reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outarray15 <= (others => '0');
|
||||
jrloop : for j in 0 to 4 loop
|
||||
outarray (j) := (others => '0');
|
||||
in1array (j) := (others => '0');
|
||||
in2array (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outarray15 <= outarray(4);
|
||||
jcloop : for j in 4 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
j1loop : for j in 3 downto 1 loop
|
||||
in1array (j) := in1array(j-1);
|
||||
end loop j1loop;
|
||||
j2loop : for j in 3 downto 1 loop
|
||||
in2array (j) := in2array(j-1);
|
||||
end loop j2loop;
|
||||
in1array(0) := in1reg3;
|
||||
in2array(0) := in2reg3;
|
||||
-- compare test
|
||||
if (in1array(3) = in2array(3)) then
|
||||
outarray(0)(-8) := '1';
|
||||
else
|
||||
outarray(0)(-8) := '0';
|
||||
end if;
|
||||
if (in1array(3) /= in2array(3)) then
|
||||
outarray(0)(-7) := '1';
|
||||
else
|
||||
outarray(0)(-7) := '0';
|
||||
end if;
|
||||
if (in1array(3) < in2array(3)) then
|
||||
outarray(0)(-6) := '1';
|
||||
else
|
||||
outarray(0)(-6) := '0';
|
||||
end if;
|
||||
if (in1array(3) > in2array(3)) then
|
||||
outarray(0)(-5) := '1';
|
||||
else
|
||||
outarray(0)(-5) := '0';
|
||||
end if;
|
||||
if (in1array(3) <= in2array(3)) then
|
||||
outarray(0)(-4) := '1';
|
||||
else
|
||||
outarray(0)(-4) := '0';
|
||||
end if;
|
||||
if (in1array(3) >= in2array(3)) then
|
||||
outarray(0)(-3) := '1';
|
||||
else
|
||||
outarray(0)(-3) := '0';
|
||||
end if;
|
||||
if (in1array(3) = 45) then
|
||||
outarray(0)(-2) := '1';
|
||||
else
|
||||
outarray(0)(-2) := '0';
|
||||
end if;
|
||||
if (in1array(3) = 3.125) then
|
||||
outarray(0)(-1) := '1';
|
||||
else
|
||||
outarray(0)(-1) := '0';
|
||||
end if;
|
||||
-- add integer and real
|
||||
outarray(0)(0) := \?=\ (in1array(3), in2array(3) + 45);
|
||||
if (in1array(3) = in2array(3) + 3.125) then
|
||||
outarray(0)(1) := '1';
|
||||
else
|
||||
outarray(0)(1) := '0';
|
||||
end if;
|
||||
if (std_match (in1array(3), match_data)) then
|
||||
outarray(0)(2) := '1';
|
||||
else
|
||||
outarray(0)(2) := '0';
|
||||
end if;
|
||||
outarray(0)(3) := nor_reduce (in1array(3) or in2array(3));
|
||||
outarray(0)(4) := xnor_reduce (in1array(3) xor in2array(3));
|
||||
outarray(0)(5) := nand_reduce (not in1array(3));
|
||||
outarray(0)(6) := or_reduce ('1' and ufixed(in1array(3)));
|
||||
if find_leftmost(in1array(3), '1') = 3 then
|
||||
outarray(0)(7) := '1';
|
||||
else
|
||||
outarray(0)(7) := '0';
|
||||
end if;
|
||||
end if;
|
||||
end process cmd15reg;
|
||||
|
||||
-- purpose: register the inputs and the outputs
|
||||
-- type : sequential
|
||||
-- inputs : clk, rst_n, in1, in2
|
||||
-- outputs: out1
|
||||
cmdreg : process (clk, rst_n) is
|
||||
variable outreg : sfixed16; -- register stages
|
||||
variable in1reg, in2reg : sfixed16; -- register stages
|
||||
variable in1reg2, in2reg2 : sfixed16; -- register stages
|
||||
begin -- process mulreg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
in1reg := (others => '0');
|
||||
in2reg := (others => '0');
|
||||
in1reg2 := (others => '0');
|
||||
in2reg2 := (others => '0');
|
||||
in1reg3 <= (others => '0');
|
||||
in2reg3 <= (others => '0');
|
||||
out1 <= (others => '0');
|
||||
outreg := (others => '0');
|
||||
rcloop : for i in 1 to 15 loop
|
||||
cmdarray (i) <= (others => '0');
|
||||
end loop rcloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
out1 <= to_slv (outreg);
|
||||
outregc : case cmdarray (13) is
|
||||
when "0000" => outreg := outarray0;
|
||||
when "0001" => outreg := outarray1;
|
||||
when "0010" => outreg := outarray2;
|
||||
when "0011" => outreg := outarray3;
|
||||
when "0100" => outreg := outarray4;
|
||||
when "0101" => outreg := outarray5;
|
||||
when "0110" => outreg := outarray6;
|
||||
when "0111" => outreg := outarray7;
|
||||
when "1000" => outreg := outarray8;
|
||||
when "1001" => outreg := outarray9;
|
||||
when "1010" => outreg := outarray10;
|
||||
when "1011" => outreg := outarray11;
|
||||
when "1100" => outreg := outarray12;
|
||||
when "1101" => outreg := outarray13;
|
||||
when "1110" => outreg := outarray14;
|
||||
when "1111" => outreg := outarray15;
|
||||
when others => null;
|
||||
end case outregc;
|
||||
cmdpipe : for i in 15 downto 3 loop
|
||||
cmdarray (i) <= cmdarray (i-1);
|
||||
end loop cmdpipe;
|
||||
cmdarray (2) <= STD_ULOGIC_VECTOR(cmd);
|
||||
in1reg3 <= in1reg2;
|
||||
in2reg3 <= in2reg2;
|
||||
in1reg2 := in1reg;
|
||||
in2reg2 := in2reg;
|
||||
in1reg := to_sfixed (in1, in1reg);
|
||||
in2reg := to_sfixed (in2, in2reg);
|
||||
end if;
|
||||
end process cmdreg;
|
||||
|
||||
end architecture rtl;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,709 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Synthesis test for the floating point math package
|
||||
-- This test is designed to be synthesizable and exercise much of the package.
|
||||
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
|
||||
-- --------------------------------------------------------------------
|
||||
-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $
|
||||
-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $
|
||||
-------------------------------------------------------------------------------
|
||||
library ieee, ieee_proposed;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_float_types.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
use ieee_proposed.float_pkg.all;
|
||||
use ieee.math_real.all;
|
||||
entity float_synth is
|
||||
|
||||
port (
|
||||
in1, in2 : in std_logic_vector (31 downto 0); -- inputs
|
||||
out1 : out std_logic_vector (31 downto 0); -- output
|
||||
cmd : in std_logic_vector (3 downto 0);
|
||||
clk, rst_n : in std_ulogic); -- clk and reset
|
||||
|
||||
end entity float_synth;
|
||||
|
||||
architecture rtl of float_synth is
|
||||
subtype fp16 is float (6 downto -9); -- 16 bit
|
||||
|
||||
type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd
|
||||
signal cmdarray : cmd_type; -- command pipeline
|
||||
type cry_type is array (0 to 15) of float32; -- arrays
|
||||
signal outx : cry_type;
|
||||
signal in1reg3, in2reg3 : float32; -- register stages
|
||||
|
||||
begin -- architecture rtl
|
||||
|
||||
-- purpose: "0000" test the "+" operator
|
||||
cmd0reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd0reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(0) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(0) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := in1reg3 + in2reg3;
|
||||
end if;
|
||||
|
||||
end process cmd0reg;
|
||||
|
||||
-- purpose: "0001" test the "-" operator
|
||||
cmd1reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd1reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(1) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(1) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := in1reg3 - in2reg3;
|
||||
end if;
|
||||
|
||||
end process cmd1reg;
|
||||
|
||||
-- purpose: "0010" test the "*" operator
|
||||
cmd2reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(2) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(2) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := in1reg3 * in2reg3;
|
||||
end if;
|
||||
|
||||
end process cmd2reg;
|
||||
|
||||
-- purpose: "0011" performs test the "/" operator
|
||||
cmd3reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd1reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(3) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(3) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
if (cmdarray(4) = "0011") then
|
||||
outarray(0) := in1reg3 / in2reg3;
|
||||
else
|
||||
outarray(0) := (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process cmd3reg;
|
||||
|
||||
-- purpose: "0100" test the "resize" function
|
||||
cmd4reg: process (clk, rst_n) is
|
||||
variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
begin -- process cmd1reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(4) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(4) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => true,
|
||||
denormalize => false,
|
||||
round_style => round_zero);
|
||||
when "001" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
-- size_res => tmpfp161,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => false,
|
||||
denormalize => false);
|
||||
when "010" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => false,
|
||||
denormalize => false);
|
||||
when "011" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
-- size_res => tmpfp161,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => true,
|
||||
denormalize => false,
|
||||
round_style => round_inf);
|
||||
when "100" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => true,
|
||||
denormalize => false,
|
||||
round_style => round_neginf);
|
||||
when "101" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
-- size_res => tmpfp161,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low,
|
||||
denormalize_in => true,
|
||||
denormalize => false,
|
||||
check_error => false,
|
||||
round_style => round_zero);
|
||||
when "110" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low);
|
||||
when "111" =>
|
||||
tmpfp161 := resize ( arg => in1reg3,
|
||||
exponent_width => tmpfp161'high,
|
||||
fraction_width => -tmpfp161'low
|
||||
-- size_res => tmpfp161
|
||||
);
|
||||
when others => null;
|
||||
end case;
|
||||
outarray(0)(-8 downto -23) := tmpfp161;
|
||||
outarray(0)(8 downto 6) := float(tmpcmd);
|
||||
outarray(0)(6 downto -7) := (others => '0');
|
||||
end if;
|
||||
end process cmd4reg;
|
||||
|
||||
-- purpose: "0101" Conversion function test
|
||||
cmd5reg: process (clk, rst_n) is
|
||||
variable uns : unsigned (15 downto 0); -- unsigned number
|
||||
variable s : signed (15 downto 0); -- signed number
|
||||
variable uf : ufixed (8 downto -7); -- unsigned fixed
|
||||
variable sf : sfixed (8 downto -7); -- signed fixed point
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
begin -- process cmd1reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(5) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(5) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
uns := to_unsigned (in1reg3, uns'length);
|
||||
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
|
||||
when "001" =>
|
||||
uns := to_unsigned (in1reg3, uns);
|
||||
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
|
||||
when "010" =>
|
||||
s := to_signed (in1reg3, s'length);
|
||||
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
|
||||
when "011" =>
|
||||
s := to_signed (in1reg3, s);
|
||||
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
|
||||
when "100" =>
|
||||
uf := to_ufixed (in1reg3, uf'high, uf'low);
|
||||
outarray(0)(-8 downto -23) := float(to_slv(uf));
|
||||
when "101" =>
|
||||
uf := to_ufixed (in1reg3, uf);
|
||||
outarray(0)(-8 downto -23) := float(to_slv(uf));
|
||||
when "110" =>
|
||||
sf := to_sfixed (in1reg3, sf'high, sf'low);
|
||||
outarray(0)(-8 downto -23) := float(to_slv(sf));
|
||||
when "111" =>
|
||||
sf := to_sfixed (in1reg3, sf);
|
||||
outarray(0)(-8 downto -23) := float(to_slv(sf));
|
||||
when others => null;
|
||||
end case;
|
||||
outarray(0)(8 downto 6) := float(tmpcmd);
|
||||
outarray(0)(5 downto -7) := (others => '0');
|
||||
end if;
|
||||
end process cmd5reg;
|
||||
|
||||
-- purpose: "0110" to_float()
|
||||
cmd6reg: process (clk, rst_n) is
|
||||
variable uns : unsigned (15 downto 0); -- unsigned number
|
||||
variable s : signed (15 downto 0); -- signed number
|
||||
variable uf : ufixed (8 downto -7); -- unsigned fixed
|
||||
variable sf : sfixed (8 downto -7); -- signed fixed point
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
begin -- process cmd1reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(6) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(6) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
|
||||
outarray(0) := to_float(uns, 8, 23);
|
||||
when "001" =>
|
||||
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
|
||||
outarray(0) := to_float(uns, in1reg3);
|
||||
when "010" =>
|
||||
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
|
||||
outarray(0) := to_float(s, 8, 23);
|
||||
when "011" =>
|
||||
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
|
||||
outarray(0) := to_float(s, in1reg3);
|
||||
when "100" =>
|
||||
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);
|
||||
outarray(0) := to_float(uf, 8, 23);
|
||||
when "101" =>
|
||||
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);
|
||||
outarray(0) := to_float(uf, in1reg3);
|
||||
when "110" =>
|
||||
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);
|
||||
outarray(0) := to_float(sf, 8, 23);
|
||||
when "111" =>
|
||||
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);
|
||||
outarray(0) := to_float(sf, in1reg3);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process cmd6reg;
|
||||
|
||||
-- purpose: "0111" mod function
|
||||
cmd7reg: process (clk, rst_n) is
|
||||
variable tmpuns : unsigned (31 downto 0); -- unsigned number
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd1reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(7) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(7) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := in1reg3 mod in2reg3;
|
||||
end if;
|
||||
end process cmd7reg;
|
||||
|
||||
-- purpose: "1000" rem function
|
||||
cmd8reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(8) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(8) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := in1reg3 rem in2reg3;
|
||||
end if;
|
||||
|
||||
end process cmd8reg;
|
||||
|
||||
-- purpose: "1001" to_float (constants) test
|
||||
cmd9reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(9) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(9) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
outarray(0) := to_float(0, 8, 23);
|
||||
when "001" =>
|
||||
outarray(0) := to_float(0.0, 8, 23);
|
||||
when "010" =>
|
||||
outarray(0) := to_float(8, in1reg3);
|
||||
when "011" =>
|
||||
outarray(0) := to_float(8.0, in1reg3);
|
||||
when "100" =>
|
||||
outarray(0) := to_float(-8, 8, 23);
|
||||
when "101" =>
|
||||
outarray(0) := to_float(-8.0, 8, 23);
|
||||
when "110" =>
|
||||
outarray(0) := to_float(27000, in2reg3);
|
||||
when "111" =>
|
||||
-- outarray(0) := "01000000010010010000111111011011";
|
||||
outarray(0) := to_float(MATH_PI, in2reg3);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process cmd9reg;
|
||||
|
||||
-- purpose: "1010" data manipulation (+, -, scalb, etc)
|
||||
cmd10reg: process (clk, rst_n) is
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
variable s : SIGNED (7 downto 0); -- signed number
|
||||
variable outarray : cry_type; -- array for output
|
||||
constant posinf : float32 := "01111111100000000000000000000000"; -- +inf
|
||||
constant neginf : float32 := "11111111100000000000000000000000"; -- +inf
|
||||
constant onept5 : float32 := "00111111110000000000000000000000"; -- 1.5
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(10) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(10) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
outarray(0) := - in1reg3;
|
||||
when "001" =>
|
||||
outarray(0) := abs( in1reg3);
|
||||
when "010" =>
|
||||
if (cmdarray(4) = "1010") then
|
||||
s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);
|
||||
outarray(0) := Scalb (in1reg3, s);
|
||||
else
|
||||
outarray(0) := (others => '0');
|
||||
end if;
|
||||
when "011" =>
|
||||
if (cmdarray(4) = "1010") then
|
||||
s := logb (in1reg3);
|
||||
outarray(0) := (others => '0');
|
||||
outarray(0)(-16 downto -23) := float(std_logic_vector(s));
|
||||
else
|
||||
outarray(0) := (others => '0');
|
||||
end if;
|
||||
when "100" =>
|
||||
outarray(0) := Nextafter ( in1reg3, onept5);
|
||||
when "101" =>
|
||||
outarray(0) := Nextafter ( in1reg3, -onept5);
|
||||
when "110" =>
|
||||
outarray(0) := Nextafter ( x => in1reg3, y => posinf,
|
||||
check_error => false,
|
||||
denormalize => false);
|
||||
when "111" =>
|
||||
outarray(0) := Nextafter (x => in1reg3, y => neginf,
|
||||
check_error => false,
|
||||
denormalize => false);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process cmd10reg;
|
||||
|
||||
-- purpose "1011" copysign
|
||||
cmd11reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(11) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(11) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := Copysign (in1reg3, in2reg3);
|
||||
end if;
|
||||
end process cmd11reg;
|
||||
|
||||
-- purpose "1100" compare test
|
||||
cmd12reg: process (clk, rst_n) is
|
||||
variable outarray : cry_type; -- array for output
|
||||
constant fifteenpt5 : float32 := "01000001011110000000000000000000";-- 15.5
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(12) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(12) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
outarray(0) := (others => '0');
|
||||
if (in1reg3 = in2reg3) then
|
||||
outarray(0)(outarray(0)'high) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high) := '0';
|
||||
end if;
|
||||
if (in1reg3 /= in2reg3) then
|
||||
outarray(0)(outarray(0)'high-1) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-1) := '0';
|
||||
end if;
|
||||
if (in1reg3 > in2reg3) then
|
||||
outarray(0)(outarray(0)'high-2) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-2) := '0';
|
||||
end if;
|
||||
if (in1reg3 < in2reg3) then
|
||||
outarray(0)(outarray(0)'high-3) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-3) := '0';
|
||||
end if;
|
||||
if (in1reg3 >= in2reg3) then
|
||||
outarray(0)(outarray(0)'high-4) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-4) := '0';
|
||||
end if;
|
||||
if (in1reg3 <= in2reg3) then
|
||||
outarray(0)(outarray(0)'high-5) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-5) := '0';
|
||||
end if;
|
||||
outarray(0)(outarray(0)'high-6) := \?=\ (in1reg3, 15);
|
||||
outarray(0)(outarray(0)'high-7) := \?=\ (in1reg3, 15.5);
|
||||
if (Unordered (in1reg3, in2reg3)) then
|
||||
outarray(0)(outarray(0)'high-8) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-8) := '0';
|
||||
end if;
|
||||
if (Finite (in1reg3)) then
|
||||
outarray(0)(outarray(0)'high-9) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-9) := '0';
|
||||
end if;
|
||||
if (Isnan (in1reg3)) then
|
||||
outarray(0)(outarray(0)'high-10) := '1';
|
||||
else
|
||||
outarray(0)(outarray(0)'high-10) := '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process cmd12reg;
|
||||
|
||||
-- purpose "1101" boolean test
|
||||
cmd13reg: process (clk, rst_n) is
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(13) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(13) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
outarray(0) := not (in1reg3);
|
||||
when "001" =>
|
||||
outarray(0) := in1reg3 and in2reg3;
|
||||
when "010" =>
|
||||
outarray(0) := in1reg3 or in2reg3;
|
||||
when "011" =>
|
||||
outarray(0) := in1reg3 nand in2reg3;
|
||||
when "100" =>
|
||||
outarray(0) := in1reg3 nor in2reg3;
|
||||
when "101" =>
|
||||
outarray(0) := in1reg3 xor in2reg3;
|
||||
when "110" =>
|
||||
outarray(0) := in1reg3 xnor in2reg3;
|
||||
when "111" =>
|
||||
outarray(0) := in1reg3 xor '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process cmd13reg;
|
||||
|
||||
-- purpose "1110" reduce and vector test
|
||||
cmd14reg: process (clk, rst_n) is
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(14) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(14) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
outarray(0) := (others => '0');
|
||||
outarray(0)(outarray(0)'high) := and_reduce (in1reg3);
|
||||
outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);
|
||||
outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);
|
||||
outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);
|
||||
outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);
|
||||
outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);
|
||||
when "001" =>
|
||||
outarray(0) := in1reg3 and in2reg3(in2reg3'high);
|
||||
when "010" =>
|
||||
outarray(0) := in1reg3 or in2reg3(in2reg3'high);
|
||||
when "011" =>
|
||||
outarray(0) := in1reg3 nand in2reg3(in2reg3'high);
|
||||
when "100" =>
|
||||
outarray(0) := in1reg3 nor in2reg3(in2reg3'high);
|
||||
when "101" =>
|
||||
outarray(0) := in2reg3(in2reg3'high) xor in1reg3;
|
||||
when "110" =>
|
||||
outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;
|
||||
when "111" =>
|
||||
outarray(0) := in2reg3(in2reg3'high) and in1reg3;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process cmd14reg;
|
||||
|
||||
-- purpose "1111" + constant
|
||||
cmd15reg: process (clk, rst_n) is
|
||||
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
|
||||
variable outarray : cry_type; -- array for output
|
||||
begin -- process cmd2reg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
outx(15) <= ( others => '0');
|
||||
jrloop: for j in 0 to 7 loop
|
||||
outarray (j) := (others => '0');
|
||||
end loop jrloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
outx(15) <= outarray(7);
|
||||
jcloop: for j in 7 downto 1 loop
|
||||
outarray (j) := outarray(j-1);
|
||||
end loop jcloop;
|
||||
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
|
||||
case tmpcmd is
|
||||
when "000" =>
|
||||
outarray(0) := in1reg3 + 1;
|
||||
when "001" =>
|
||||
outarray(0) := 1 + in1reg3;
|
||||
when "010" =>
|
||||
outarray(0) := in1reg3 + 1.0;
|
||||
when "011" =>
|
||||
outarray(0) := 1.0 + in1reg3;
|
||||
when "100" =>
|
||||
outarray(0) := in1reg3 * 1;
|
||||
when "101" =>
|
||||
outarray(0) := 1 * in1reg3;
|
||||
when "110" =>
|
||||
outarray(0) := in1reg3 * 1.0;
|
||||
when "111" =>
|
||||
outarray(0) := 1.0 * in1reg3;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process cmd15reg;
|
||||
|
||||
-- purpose: multiply floating point
|
||||
-- type : sequential
|
||||
-- inputs : clk, rst_n, in1, in2
|
||||
-- outputs: out1
|
||||
cmdreg: process (clk, rst_n) is
|
||||
variable outreg : float32; -- register stages
|
||||
variable in1reg, in2reg : float32; -- register stages
|
||||
variable in1reg2, in2reg2 : float32; -- register stages
|
||||
begin -- process mulreg
|
||||
|
||||
if rst_n = '0' then -- asynchronous reset (active low)
|
||||
in1reg := ( others => '0');
|
||||
in2reg := ( others => '0');
|
||||
in1reg2 := ( others => '0');
|
||||
in2reg2 := ( others => '0');
|
||||
in1reg3 <= ( others => '0');
|
||||
in2reg3 <= ( others => '0');
|
||||
out1 <= ( others => '0');
|
||||
outreg := (others => '0');
|
||||
rcloop: for i in 1 to 15 loop
|
||||
cmdarray (i) <= (others => '0');
|
||||
end loop rcloop;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
out1 <= to_slv (outreg);
|
||||
outregc: case cmdarray (13) is
|
||||
when "0000" => outreg := outx (0);
|
||||
when "0001" => outreg := outx (1);
|
||||
when "0010" => outreg := outx (2);
|
||||
when "0011" => outreg := outx (3);
|
||||
when "0100" => outreg := outx (4);
|
||||
when "0101" => outreg := outx (5);
|
||||
when "0110" => outreg := outx (6);
|
||||
when "0111" => outreg := outx (7);
|
||||
when "1000" => outreg := outx (8);
|
||||
when "1001" => outreg := outx (9);
|
||||
when "1010" => outreg := outx (10);
|
||||
when "1011" => outreg := outx (11);
|
||||
when "1100" => outreg := outx (12);
|
||||
when "1101" => outreg := outx (13);
|
||||
when "1110" => outreg := outx (14);
|
||||
when "1111" => outreg := outx (15);
|
||||
when others => null;
|
||||
end case outregc;
|
||||
cmdpipe: for i in 15 downto 3 loop
|
||||
cmdarray (i) <= cmdarray (i-1);
|
||||
end loop cmdpipe;
|
||||
cmdarray (2) <= std_ulogic_vector(cmd);
|
||||
in1reg3 <= in1reg2;
|
||||
in2reg3 <= in2reg2;
|
||||
in1reg2 := in1reg;
|
||||
in2reg2 := in2reg;
|
||||
in1reg := to_float (in1, in1reg);
|
||||
in2reg := to_float (in2, in2reg);
|
||||
end if;
|
||||
|
||||
end process cmdreg;
|
||||
|
||||
end architecture rtl;
|
||||
@@ -1,16 +0,0 @@
|
||||
<pre>
|
||||
Tested with Modeltech 6.5b
|
||||
|
||||
When you compile you will get a warning:
|
||||
(vcom-1246) Range 0 downto 1 is null.
|
||||
To suppress this warning compile with "-suppress 1236"
|
||||
In the MTI install you will find a premapped library called
|
||||
"floatfixlib". This contains an old version of "fixed_pkg" and "float_pkg".
|
||||
The versions in this release are newer.
|
||||
|
||||
To compile: source the "compile.mti" script. This will create the
|
||||
IEEE_PROPOSED VHDL library.
|
||||
|
||||
See the README for an explination of the new functions in these packages.
|
||||
|
||||
</pre>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,478 +0,0 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- "standard_textio_additions" package contains the additions to the built in
|
||||
-- "standard.textio" package.
|
||||
-- This package should be compiled into "ieee_proposed" and used as follows:
|
||||
-- use ieee_proposed.standard_textio_additions.all;
|
||||
-- Last Modified: $Date: 2007/03/13 18:25:58 $
|
||||
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
|
||||
--
|
||||
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
|
||||
------------------------------------------------------------------------------
|
||||
use std.textio.all;
|
||||
package standard_textio_additions is
|
||||
|
||||
-- procedure DEALLOCATE (P : inout LINE);
|
||||
|
||||
procedure FLUSH (file F : TEXT);
|
||||
|
||||
function MINIMUM (L, R : SIDE) return SIDE;
|
||||
function MAXIMUM (L, R : SIDE) return SIDE;
|
||||
|
||||
function TO_STRING (VALUE : SIDE) return STRING;
|
||||
|
||||
function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
|
||||
|
||||
procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
|
||||
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
|
||||
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
|
||||
alias BREAD is READ [LINE, BIT_VECTOR];
|
||||
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
|
||||
alias BINARY_READ is READ [LINE, BIT_VECTOR];
|
||||
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
|
||||
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
|
||||
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
|
||||
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
|
||||
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
|
||||
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
|
||||
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
|
||||
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
|
||||
procedure TEE (file F : TEXT; L : inout LINE);
|
||||
procedure WRITE (L : inout LINE; VALUE : in REAL;
|
||||
FORMAT : in STRING);
|
||||
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
|
||||
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
|
||||
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
|
||||
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
|
||||
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
|
||||
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
|
||||
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
|
||||
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
|
||||
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
|
||||
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
|
||||
|
||||
end package standard_textio_additions;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.standard_additions.all;
|
||||
|
||||
package body standard_textio_additions is
|
||||
-- pragma synthesis_off
|
||||
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
|
||||
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
|
||||
|
||||
-- Writes L to a file without modifying the contents of the line
|
||||
procedure TEE (file F : TEXT; L : inout LINE) is
|
||||
begin
|
||||
write (OUTPUT, L.all & LF);
|
||||
writeline(F, L);
|
||||
end procedure TEE;
|
||||
|
||||
procedure FLUSH (file F: TEXT) is -- Implicit
|
||||
begin
|
||||
file_close (F);
|
||||
end procedure FLUSH;
|
||||
|
||||
-- Read and Write procedure for strings
|
||||
procedure SREAD (L : inout LINE;
|
||||
VALUE : out STRING;
|
||||
STRLEN : out natural) is
|
||||
variable ok : BOOLEAN;
|
||||
variable c : CHARACTER;
|
||||
-- Result is padded with space characters
|
||||
variable result : STRING (1 to VALUE'length) := (others => ' ');
|
||||
begin
|
||||
VALUE := result;
|
||||
loop -- skip white space
|
||||
read(L, c, ok);
|
||||
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
|
||||
end loop;
|
||||
-- Bail out if there was a bad read
|
||||
if not ok then
|
||||
STRLEN := 0;
|
||||
return;
|
||||
end if;
|
||||
result (1) := c;
|
||||
STRLEN := 1;
|
||||
for i in 2 to VALUE'length loop
|
||||
read(L, c, ok);
|
||||
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
|
||||
exit;
|
||||
else
|
||||
result (i) := c;
|
||||
end if;
|
||||
STRLEN := i;
|
||||
end loop;
|
||||
VALUE := result;
|
||||
end procedure SREAD;
|
||||
|
||||
-- Hex Read and Write procedures for bit_vector.
|
||||
-- Procedure only visible internally.
|
||||
procedure Char2QuadBits (C : CHARACTER;
|
||||
RESULT : out BIT_VECTOR(3 downto 0);
|
||||
GOOD : out BOOLEAN;
|
||||
ISSUE_ERROR : in BOOLEAN) is
|
||||
begin
|
||||
case c is
|
||||
when '0' => result := x"0"; good := true;
|
||||
when '1' => result := x"1"; good := true;
|
||||
when '2' => result := x"2"; good := true;
|
||||
when '3' => result := x"3"; good := true;
|
||||
when '4' => result := x"4"; good := true;
|
||||
when '5' => result := x"5"; good := true;
|
||||
when '6' => result := x"6"; good := true;
|
||||
when '7' => result := x"7"; good := true;
|
||||
when '8' => result := x"8"; good := true;
|
||||
when '9' => result := x"9"; good := true;
|
||||
when 'A' | 'a' => result := x"A"; good := true;
|
||||
when 'B' | 'b' => result := x"B"; good := true;
|
||||
when 'C' | 'c' => result := x"C"; good := true;
|
||||
when 'D' | 'd' => result := x"D"; good := true;
|
||||
when 'E' | 'e' => result := x"E"; good := true;
|
||||
when 'F' | 'f' => result := x"F"; good := true;
|
||||
when others =>
|
||||
assert not ISSUE_ERROR report
|
||||
"TEXTIO.HREAD Error: Read a '" & c &
|
||||
"', expected a Hex character (0-F)." severity error;
|
||||
GOOD := false;
|
||||
end case;
|
||||
end procedure Char2QuadBits;
|
||||
|
||||
procedure HREAD (L : inout LINE;
|
||||
VALUE : out BIT_VECTOR;
|
||||
GOOD : out BOOLEAN) is
|
||||
variable ok : BOOLEAN;
|
||||
variable c : CHARACTER;
|
||||
constant ne : INTEGER := (VALUE'length+3)/4;
|
||||
constant pad : INTEGER := ne*4 - VALUE'length;
|
||||
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
|
||||
variable s : STRING(1 to ne-1);
|
||||
begin
|
||||
VALUE := (VALUE'range => '0');
|
||||
loop -- skip white space
|
||||
read(l, c, ok);
|
||||
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
|
||||
end loop;
|
||||
-- Bail out if there was a bad read
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
Char2QuadBits(c, sv(0 to 3), ok, false);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
read(L, s, ok);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
for i in 1 to ne-1 loop
|
||||
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
if or_reduce (sv (0 to pad-1)) = '1' then
|
||||
GOOD := false; -- vector was truncated.
|
||||
else
|
||||
GOOD := true;
|
||||
VALUE := sv (pad to sv'high);
|
||||
end if;
|
||||
end procedure HREAD;
|
||||
|
||||
procedure HREAD (L : inout LINE;
|
||||
VALUE : out BIT_VECTOR) is
|
||||
variable ok : BOOLEAN;
|
||||
variable c : CHARACTER;
|
||||
constant ne : INTEGER := (VALUE'length+3)/4;
|
||||
constant pad : INTEGER := ne*4 - VALUE'length;
|
||||
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
|
||||
variable s : STRING(1 to ne-1);
|
||||
begin
|
||||
VALUE := (VALUE'range => '0');
|
||||
loop -- skip white space
|
||||
read(l, c, ok);
|
||||
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
|
||||
end loop;
|
||||
-- Bail out if there was a bad read
|
||||
if not ok then
|
||||
report "TEXTIO.HREAD Error: Failed skipping white space"
|
||||
severity error;
|
||||
return;
|
||||
end if;
|
||||
Char2QuadBits(c, sv(0 to 3), ok, true);
|
||||
if not ok then
|
||||
return;
|
||||
end if;
|
||||
read(L, s, ok);
|
||||
if not ok then
|
||||
report "TEXTIO.HREAD Error: Failed to read the STRING"
|
||||
severity error;
|
||||
return;
|
||||
end if;
|
||||
for i in 1 to ne-1 loop
|
||||
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
|
||||
if not ok then
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
if or_reduce (sv (0 to pad-1)) = '1' then
|
||||
report "TEXTIO.HREAD Error: Vector truncated"
|
||||
severity error;
|
||||
else
|
||||
VALUE := sv (pad to sv'high);
|
||||
end if;
|
||||
end procedure HREAD;
|
||||
|
||||
procedure HWRITE (L : inout LINE;
|
||||
VALUE : in BIT_VECTOR;
|
||||
JUSTIFIED : in SIDE := right;
|
||||
FIELD : in WIDTH := 0) is
|
||||
begin
|
||||
write (L => L,
|
||||
VALUE => to_hstring(VALUE),
|
||||
JUSTIFIED => JUSTIFIED,
|
||||
FIELD => FIELD);
|
||||
end procedure HWRITE;
|
||||
|
||||
-- Procedure only visible internally.
|
||||
procedure Char2TriBits (C : CHARACTER;
|
||||
RESULT : out BIT_VECTOR(2 downto 0);
|
||||
GOOD : out BOOLEAN;
|
||||
ISSUE_ERROR : in BOOLEAN) is
|
||||
begin
|
||||
case c is
|
||||
when '0' => result := o"0"; good := true;
|
||||
when '1' => result := o"1"; good := true;
|
||||
when '2' => result := o"2"; good := true;
|
||||
when '3' => result := o"3"; good := true;
|
||||
when '4' => result := o"4"; good := true;
|
||||
when '5' => result := o"5"; good := true;
|
||||
when '6' => result := o"6"; good := true;
|
||||
when '7' => result := o"7"; good := true;
|
||||
when others =>
|
||||
assert not ISSUE_ERROR
|
||||
report
|
||||
"TEXTIO.OREAD Error: Read a '" & c &
|
||||
"', expected an Octal character (0-7)."
|
||||
severity error;
|
||||
GOOD := false;
|
||||
end case;
|
||||
end procedure Char2TriBits;
|
||||
|
||||
-- Read and Write procedures for Octal values
|
||||
procedure OREAD (L : inout LINE;
|
||||
VALUE : out BIT_VECTOR;
|
||||
GOOD : out BOOLEAN) is
|
||||
variable ok : BOOLEAN;
|
||||
variable c : CHARACTER;
|
||||
constant ne : INTEGER := (VALUE'length+2)/3;
|
||||
constant pad : INTEGER := ne*3 - VALUE'length;
|
||||
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
|
||||
variable s : STRING(1 to ne-1);
|
||||
begin
|
||||
VALUE := (VALUE'range => '0');
|
||||
loop -- skip white space
|
||||
read(l, c, ok);
|
||||
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
|
||||
end loop;
|
||||
-- Bail out if there was a bad read
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
Char2TriBits(c, sv(0 to 2), ok, false);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
read(L, s, ok);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
for i in 1 to ne-1 loop
|
||||
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
|
||||
if not ok then
|
||||
GOOD := false;
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
if or_reduce (sv (0 to pad-1)) = '1' then
|
||||
GOOD := false; -- vector was truncated.
|
||||
else
|
||||
GOOD := true;
|
||||
VALUE := sv (pad to sv'high);
|
||||
end if;
|
||||
end procedure OREAD;
|
||||
|
||||
procedure OREAD (L : inout LINE;
|
||||
VALUE : out BIT_VECTOR) is
|
||||
variable c : CHARACTER;
|
||||
variable ok : BOOLEAN;
|
||||
constant ne : INTEGER := (VALUE'length+2)/3;
|
||||
constant pad : INTEGER := ne*3 - VALUE'length;
|
||||
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
|
||||
variable s : STRING(1 to ne-1);
|
||||
begin
|
||||
VALUE := (VALUE'range => '0');
|
||||
loop -- skip white space
|
||||
read(l, c, ok);
|
||||
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
|
||||
end loop;
|
||||
-- Bail out if there was a bad read
|
||||
if not ok then
|
||||
report "TEXTIO.OREAD Error: Failed skipping white space"
|
||||
severity error;
|
||||
return;
|
||||
end if;
|
||||
Char2TriBits(c, sv(0 to 2), ok, true);
|
||||
if not ok then
|
||||
return;
|
||||
end if;
|
||||
read(L, s, ok);
|
||||
if not ok then
|
||||
report "TEXTIO.OREAD Error: Failed to read the STRING"
|
||||
severity error;
|
||||
return;
|
||||
end if;
|
||||
for i in 1 to ne-1 loop
|
||||
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
|
||||
if not ok then
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
if or_reduce (sv (0 to pad-1)) = '1' then
|
||||
report "TEXTIO.OREAD Error: Vector truncated"
|
||||
severity error;
|
||||
else
|
||||
VALUE := sv (pad to sv'high);
|
||||
end if;
|
||||
end procedure OREAD;
|
||||
|
||||
procedure OWRITE (L : inout LINE;
|
||||
VALUE : in BIT_VECTOR;
|
||||
JUSTIFIED : in SIDE := right;
|
||||
FIELD : in WIDTH := 0) is
|
||||
begin
|
||||
write (L => L,
|
||||
VALUE => to_ostring(VALUE),
|
||||
JUSTIFIED => JUSTIFIED,
|
||||
FIELD => FIELD);
|
||||
end procedure OWRITE;
|
||||
|
||||
-- read and write for vector versions
|
||||
-- These versions produce "value1, value2, value3 ...."
|
||||
procedure read (L : inout LINE;
|
||||
VALUE : out boolean_vector;
|
||||
GOOD : out BOOLEAN) is
|
||||
variable dummy : CHARACTER;
|
||||
variable igood : BOOLEAN := true;
|
||||
begin
|
||||
for i in VALUE'range loop
|
||||
read (L => L,
|
||||
VALUE => VALUE(i),
|
||||
GOOD => igood);
|
||||
if (igood) and (i /= value'right) then
|
||||
read (L => L,
|
||||
VALUE => dummy, -- Toss the comma or seperator
|
||||
good => igood);
|
||||
end if;
|
||||
if (not igood) then
|
||||
good := false;
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
good := true;
|
||||
end procedure read;
|
||||
|
||||
procedure read (L : inout LINE;
|
||||
VALUE : out boolean_vector) is
|
||||
variable dummy : CHARACTER;
|
||||
variable igood : BOOLEAN;
|
||||
begin
|
||||
for i in VALUE'range loop
|
||||
read (L => L,
|
||||
VALUE => VALUE(i),
|
||||
good => igood);
|
||||
if (igood) and (i /= value'right) then
|
||||
read (L => L,
|
||||
VALUE => dummy, -- Toss the comma or seperator
|
||||
good => igood);
|
||||
end if;
|
||||
if (not igood) then
|
||||
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
|
||||
& "Read error ecounted during vector read" severity error;
|
||||
return;
|
||||
end if;
|
||||
end loop;
|
||||
end procedure read;
|
||||
|
||||
procedure write (L : inout LINE;
|
||||
VALUE : in boolean_vector;
|
||||
JUSTIFIED : in SIDE := right;
|
||||
FIELD : in WIDTH := 0) is
|
||||
begin
|
||||
for i in VALUE'range loop
|
||||
write (L => L,
|
||||
VALUE => VALUE(i),
|
||||
JUSTIFIED => JUSTIFIED,
|
||||
FIELD => FIELD);
|
||||
if (i /= value'right) then
|
||||
swrite (L, ", ");
|
||||
end if;
|
||||
end loop;
|
||||
end procedure write;
|
||||
|
||||
procedure WRITE (L: inout LINE; VALUE: in REAL;
|
||||
FORMAT: in STRING) is
|
||||
begin
|
||||
swrite ( L => L,
|
||||
VALUE => to_string (VALUE, FORMAT));
|
||||
end procedure WRITE;
|
||||
|
||||
function justify (
|
||||
value : STRING;
|
||||
justified : SIDE := right;
|
||||
field : width := 0)
|
||||
return STRING is
|
||||
constant VAL_LEN : INTEGER := value'length;
|
||||
variable result : STRING (1 to field) := (others => ' ');
|
||||
begin -- function justify
|
||||
-- return value if field is too small
|
||||
if VAL_LEN >= field then
|
||||
return value;
|
||||
end if;
|
||||
if justified = left then
|
||||
result(1 to VAL_LEN) := value;
|
||||
elsif justified = right then
|
||||
result(field - VAL_LEN + 1 to field) := value;
|
||||
end if;
|
||||
return result;
|
||||
end function justify;
|
||||
|
||||
function to_string (
|
||||
VALUE : SIDE) return STRING is
|
||||
begin
|
||||
return SIDE'image(VALUE);
|
||||
end function to_string;
|
||||
|
||||
-- pragma synthesis_on
|
||||
-- Will be implicit
|
||||
function minimum (L, R : SIDE) return SIDE is
|
||||
begin
|
||||
if L > R then return R;
|
||||
else return L;
|
||||
end if;
|
||||
end function minimum;
|
||||
|
||||
function maximum (L, R : SIDE) return SIDE is
|
||||
begin
|
||||
if L > R then return L;
|
||||
else return R;
|
||||
end if;
|
||||
end function maximum;
|
||||
|
||||
end package body standard_textio_additions;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,439 +0,0 @@
|
||||
-- Test vectors for the synthesis test for the fixed point math package
|
||||
-- This test is designed to test fixed_synth and exercise much of the entity.
|
||||
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
|
||||
-- --------------------------------------------------------------------
|
||||
-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
|
||||
-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
|
||||
-- --------------------------------------------------------------------
|
||||
|
||||
entity test_fixed_synth is
|
||||
generic (
|
||||
quiet : boolean := false); -- make the simulation quiet
|
||||
end entity test_fixed_synth;
|
||||
|
||||
library ieee, ieee_proposed;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
architecture testbench of test_fixed_synth is
|
||||
|
||||
procedure report_error (
|
||||
constant errmes : in string; -- error message
|
||||
actual : in sfixed; -- data from algorithm
|
||||
constant expected : in sfixed) is -- reference data
|
||||
begin -- function report_error
|
||||
assert actual = expected
|
||||
report errmes & CR
|
||||
& "Actual: " & to_string(actual)
|
||||
& " (" & real'image(to_real(actual)) & ")" & CR
|
||||
& " /= " & to_string(expected)
|
||||
& " (" & real'image(to_real(expected)) & ")"
|
||||
severity error;
|
||||
return;
|
||||
end procedure report_error;
|
||||
|
||||
-- Device under test. Note that all inputs and outputs are std_logic_vector.
|
||||
-- This entity can be use both pre and post synthesis.
|
||||
component fixed_synth is
|
||||
port (
|
||||
in1, in2 : in std_logic_vector (15 downto 0); -- inputs
|
||||
out1 : out std_logic_vector (15 downto 0); -- output
|
||||
cmd : in std_logic_vector (3 downto 0);
|
||||
clk, rst_n : in std_ulogic); -- clk and reset
|
||||
end component fixed_synth;
|
||||
constant clock_period : time := 500 ns; -- clock period
|
||||
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
|
||||
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
|
||||
signal stop_clock : boolean := false; -- stop the clock
|
||||
signal clk, rst_n : std_ulogic; -- clk and reset
|
||||
signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
|
||||
signal in1, in2 : sfixed16; -- inputs
|
||||
signal out1 : sfixed16; -- output
|
||||
signal cmd : std_logic_vector (3 downto 0); -- command string
|
||||
begin -- architecture testbench
|
||||
|
||||
-- From fixed point to Std_logic_vector
|
||||
in1slv <= to_slv(in1);
|
||||
in2slv <= to_slv(in2);
|
||||
-- Std_logic_vector to fixed point.
|
||||
out1 <= to_sfixed(out1slv, out1'high, out1'low);
|
||||
DUT: fixed_synth
|
||||
port map (
|
||||
in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
|
||||
in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
|
||||
out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
|
||||
cmd => cmd, -- [in std_logic_vector (2 downto 0)]
|
||||
clk => clk, -- [in std_ulogic] clk and reset
|
||||
rst_n => rst_n); -- [in std_ulogic] clk and reset
|
||||
|
||||
-- purpose: clock driver
|
||||
clkprc: process is
|
||||
begin -- process clkprc
|
||||
if (not stop_clock) then
|
||||
clk <= '0';
|
||||
wait for clock_period/2.0;
|
||||
clk <= '1';
|
||||
wait for clock_period/2.0;
|
||||
else
|
||||
wait;
|
||||
end if;
|
||||
end process clkprc;
|
||||
|
||||
-- purpose: reset driver
|
||||
reset_proc: process is
|
||||
begin -- process reset_proc
|
||||
rst_n <= '0';
|
||||
wait for clock_period * 2.0;
|
||||
rst_n <= '1';
|
||||
wait;
|
||||
end process reset_proc;
|
||||
|
||||
-- purpose: main test loop
|
||||
tester: process is
|
||||
begin -- process tester
|
||||
cmd <= "0000"; -- add mode
|
||||
in1 <= (others => '0');
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0001"; -- subtract mode
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0010"; -- multiply mode
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0000"; -- add mode
|
||||
in1 <= "0000000010000000"; -- 0.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0011"; -- divide
|
||||
in1 <= "0000000010000000"; -- 0.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
cmd <= "0100"; -- unsigned add
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0101"; -- subtract mode
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0110"; -- multiply mode
|
||||
in1 <= "0000011010000000"; -- 6.5
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0100"; -- add mode
|
||||
in1 <= "0000000010000000"; -- 0.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
|
||||
in2 <= "0000001100000000"; -- 3
|
||||
wait for clock_period;
|
||||
cmd <= "0111"; -- divide
|
||||
in1 <= "0000000010000000"; -- 0.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
|
||||
in2 <= "0000000010000000"; -- 0.5
|
||||
wait for clock_period;
|
||||
-- resize
|
||||
cmd <= "1000";
|
||||
in1 <= to_sfixed (5.25, in1);
|
||||
in2 <= to_sfixed (-5.25, in2);
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (21.125, in1);
|
||||
in2 <= to_sfixed (21.125, in2);
|
||||
wait for clock_period;
|
||||
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
|
||||
cmd <= "1001"; -- SIGNED
|
||||
in1 <= to_sfixed (6.25, in1);
|
||||
wait for clock_period;
|
||||
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
|
||||
cmd <= "1001"; -- UNSIGNED
|
||||
in1 <= to_sfixed (7.25, in1);
|
||||
wait for clock_period;
|
||||
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
|
||||
cmd <= "1001"; -- SIGNED
|
||||
in1 <= to_sfixed (6.25, in1);
|
||||
wait for clock_period;
|
||||
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
|
||||
cmd <= "1001"; -- UNSIGNED
|
||||
in1 <= to_sfixed (7.25, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1010";
|
||||
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
|
||||
in1 <= to_sfixed (3, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1010";
|
||||
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
|
||||
in1 <= to_sfixed (5, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1010";
|
||||
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
|
||||
in1 <= to_sfixed (-5.5, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1010";
|
||||
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
|
||||
in1 <= to_sfixed (7.25, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1010"; -- abs (mod)
|
||||
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
|
||||
in1 <= to_sfixed (-42, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1011"; -- mod
|
||||
in1 <= to_sfixed (6.25, in1);
|
||||
in2 <= to_sfixed (6, in2);
|
||||
wait for clock_period;
|
||||
cmd <= "1100"; -- REM
|
||||
in1 <= to_sfixed (6.25, in1);
|
||||
in2 <= to_sfixed (6, in2);
|
||||
wait for clock_period;
|
||||
cmd <= "1101"; -- srl
|
||||
in1 <= to_sfixed (5.25, in1);
|
||||
in2 <= to_sfixed (-1, in2);
|
||||
wait for clock_period;
|
||||
cmd <= "1110"; -- sra
|
||||
in1 <= to_sfixed (-7.25, in1);
|
||||
in2 <= to_sfixed (1, in2);
|
||||
wait for clock_period;
|
||||
cmd <= "1111"; -- compare
|
||||
in1 <= to_sfixed (42, in1);
|
||||
in2 <= to_sfixed (42, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (45, in1);
|
||||
in2 <= to_sfixed (90, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_sfixed (3.125, in1);
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
in1 <= "0110111110101111";
|
||||
in2 <= "1111111111111111";
|
||||
wait for clock_period;
|
||||
in1 <= (others => '0');
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
in1 <= "0000111000000000";
|
||||
in2 <= "0000111000000000";
|
||||
wait for clock_period;
|
||||
in1 <= (others => '1');
|
||||
in2 <= (others => '1');
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
|
||||
wait for clock_period;
|
||||
cmd <= "0000"; -- add mode
|
||||
in1 <= (others => '0');
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait;
|
||||
end process tester;
|
||||
|
||||
-- purpose: check the output of the tester
|
||||
-- type : combinational
|
||||
-- inputs :
|
||||
-- outputs:
|
||||
checktest: process is
|
||||
constant fxzero : sfixed16 := (others => '0'); -- zero
|
||||
variable chks16 : sfixed16; -- variable
|
||||
variable sm1, sm2 : sfixed7; -- small fixed point
|
||||
begin -- process checktest
|
||||
wait for clock_period/2.0;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
waitloop: while (out1 = fxzero) loop
|
||||
wait for clock_period;
|
||||
end loop waitloop;
|
||||
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
|
||||
report_error ( "3.0 + 6.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
|
||||
report_error ( "6.5 - 3.0 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
|
||||
report_error ( "6.5 * 3.0 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
|
||||
report_error ( "0.5 + 0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
|
||||
report_error ( "3.14 + 3 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := "0000000100000000";
|
||||
report_error ( "0.5/0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
|
||||
report_error ( "-0.5/0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
|
||||
report_error ( "3.0 + 6.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
|
||||
report_error ( "6.5 - 3.0 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
|
||||
report_error ( "6.5 * 3.0 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
|
||||
report_error ( "0.5 + 0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
|
||||
report_error ( "3.14 + 3 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := "0000000100000000";
|
||||
report_error ( "0.5/0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
|
||||
report_error ( "6.5/0.5 error",
|
||||
out1,
|
||||
chks16);
|
||||
wait for clock_period;
|
||||
-- resize test
|
||||
sm1 := out1 (7 downto 1);
|
||||
sm2 := to_sfixed (5.25, sm2);
|
||||
report_error ( "resize 1 error", sm1, sm2);
|
||||
sm1 := out1 (-1 downto -7);
|
||||
sm2 := to_sfixed (-5.25, sm2);
|
||||
report_error ( "resize 2 error", sm1, sm2);
|
||||
wait for clock_period;
|
||||
sm1 := out1 (7 downto 1);
|
||||
sm2 := "0101001"; -- wrapped
|
||||
-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
|
||||
report_error ( "resize 1 error", sm1, sm2);
|
||||
sm1 := out1 (-1 downto -7);
|
||||
sm2 := "0111111"; -- saturate
|
||||
report_error ( "resize 2 error", sm1, sm2);
|
||||
wait for clock_period;
|
||||
-- to_signed and back
|
||||
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
|
||||
wait for clock_period;
|
||||
-- to_unsigned and back
|
||||
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
|
||||
wait for clock_period;
|
||||
-- to_integer and back
|
||||
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
|
||||
wait for clock_period;
|
||||
-- to_integer(ufixed) and back
|
||||
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
|
||||
wait for clock_period;
|
||||
report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
|
||||
wait for clock_period;
|
||||
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
|
||||
wait for clock_period;
|
||||
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
|
||||
wait for clock_period;
|
||||
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
|
||||
wait for clock_period;
|
||||
report_error ("abs(-42)", out1, to_sfixed (42, out1));
|
||||
wait for clock_period;
|
||||
report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
|
||||
wait for clock_period;
|
||||
report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
|
||||
wait for clock_period;
|
||||
chks16 := "0000101010000000";
|
||||
report_error ("5.25 srl -1", out1, chks16);
|
||||
wait for clock_period;
|
||||
chks16 := "1111110001100000";
|
||||
report_error ("-7.25 sra 1", out1, chks16);
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0111000000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "42=42 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
chks16 := "------0001010110";
|
||||
assert (std_match (out1, chks16))
|
||||
report "45=90 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
chks16 := "------1010101010";
|
||||
assert (std_match (out1, chks16))
|
||||
report "3.125=0 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0--1010000101010";
|
||||
assert (std_match (out1, chks16))
|
||||
report "pattern1 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0001100000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "zero = zero " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "1111000000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "pattern2 compare " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
-- 7654321012345678
|
||||
chks16 := "0111000000110001";
|
||||
assert (std_match (out1, chks16))
|
||||
report "-1 = -1 " & CR
|
||||
& "Actual " & to_string(out1) & CR
|
||||
& "Expected " & to_string(chks16) severity error;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
assert (false) report "Testing complete" severity note;
|
||||
stop_clock <= true;
|
||||
wait;
|
||||
end process checktest;
|
||||
end architecture testbench;
|
||||
@@ -1,892 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- test routine for the post synthesis 32 bit multiply
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
entity test_float_synth is
|
||||
generic (
|
||||
quiet : BOOLEAN := false);
|
||||
end entity test_float_synth;
|
||||
|
||||
use std.textio.all;
|
||||
library ieee, ieee_proposed;
|
||||
use ieee.math_real.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee_proposed.fixed_float_types.all;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
use ieee_proposed.float_pkg.all;
|
||||
|
||||
--library modelsim_lib;
|
||||
--use modelsim_lib.util.all;
|
||||
|
||||
architecture testbench of test_float_synth is
|
||||
subtype fp16 is float (6 downto -9); -- 16 bit
|
||||
function reverse (
|
||||
inpvec : STD_LOGIC_VECTOR (0 to 31))
|
||||
return float32 is
|
||||
variable result : float32;
|
||||
begin
|
||||
for i in 0 to 31 loop
|
||||
result (i-23) := inpvec(i);
|
||||
end loop; -- i
|
||||
return result;
|
||||
end function reverse;
|
||||
|
||||
-- purpose: converts an float32 into a std_logic_vector
|
||||
-- function to_slv (
|
||||
-- input : float32) -- float32 input
|
||||
-- return std_logic_vector is
|
||||
-- variable result : std_logic_vector (31 downto 0); -- result
|
||||
-- begin -- function to_slv
|
||||
-- floop: for i in float32'range loop
|
||||
-- result (i + fp_fraction_width) := input (i);
|
||||
-- end loop floop;
|
||||
-- return result;
|
||||
-- end function to_slv;
|
||||
|
||||
-- purpose: converts a std_logic_vector to an float32
|
||||
function to_float32x (
|
||||
signal input : STD_LOGIC_VECTOR (31 downto 0))
|
||||
return float32 is
|
||||
variable result : float32;
|
||||
begin -- function to_float32x
|
||||
return to_float (input, float32'high, -float32'low);
|
||||
end function to_float32x;
|
||||
|
||||
procedure report_error (
|
||||
constant errmes : STRING; -- error message
|
||||
actual : in float32; -- data from algorithm
|
||||
constant expected : float32) is -- reference data
|
||||
begin -- function report_error
|
||||
assert actual = expected
|
||||
report errmes & " miscompare" & CR &
|
||||
"Actual " & to_string (actual) & " ("
|
||||
& REAL'image(to_real(actual))& ") /= " & CR &
|
||||
"Expected " & to_string (expected) & " ("
|
||||
& REAL'image(to_real(expected))& ")"
|
||||
severity error;
|
||||
return;
|
||||
end procedure report_error;
|
||||
procedure report_error16 (
|
||||
constant errmes : STRING; -- error message
|
||||
actual : in fp16; -- data from algorithm
|
||||
constant expected : fp16) is -- reference data
|
||||
begin -- function report_error
|
||||
assert actual = expected
|
||||
report errmes & " miscompare" & CR &
|
||||
"Actual " & to_string (actual) & " ("
|
||||
& REAL'image(to_real(actual))& ") /= " & CR &
|
||||
"Expected " & to_string (expected) & " ("
|
||||
& REAL'image(to_real(expected))& ")"
|
||||
severity error;
|
||||
return;
|
||||
end procedure report_error16;
|
||||
|
||||
component float_synth is
|
||||
port (
|
||||
in1, in2 : in STD_LOGIC_VECTOR(31 downto 0); -- inputs
|
||||
out1 : out STD_LOGIC_VECTOR(31 downto 0); -- output
|
||||
cmd : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
clk, rst_n : in STD_ULOGIC); -- clk and reset
|
||||
end component float_synth;
|
||||
for all : float_synth
|
||||
use entity work.float_synth(rtl);
|
||||
constant clock_period : TIME := 500 ns; -- clock period
|
||||
signal stop_clock : BOOLEAN := false; -- stop the clock
|
||||
signal out1real : REAL; -- real version
|
||||
signal in1, in2 : float32; -- inputs
|
||||
signal out1 : float32; -- output
|
||||
constant zero0 : float32 := (others => '0'); -- zero
|
||||
signal cmd : STD_LOGIC_VECTOR (3 downto 0); -- command
|
||||
signal clk, rst_n : STD_ULOGIC; -- clk and reset
|
||||
signal in1slv, in2slv, out1slv : STD_LOGIC_VECTOR(31 downto 0);
|
||||
signal indelay : float32; -- spied signal
|
||||
begin -- architecture testbench
|
||||
out1real <= to_real (out1);
|
||||
in1slv <= to_slv(in1);
|
||||
in2slv <= to_slv(in2);
|
||||
out1 <= to_float32x(out1slv);
|
||||
DUT : float_synth
|
||||
port map (
|
||||
in1 => in1slv, -- [in float32] inputs
|
||||
in2 => in2slv, -- [in float32] inputs
|
||||
out1 => out1slv, -- [out float32] output
|
||||
cmd => cmd,
|
||||
clk => clk, -- [in std_ulogic] clk and reset
|
||||
rst_n => rst_n); -- [in std_ulogic] clk and reset
|
||||
|
||||
-- spy_process : process
|
||||
-- begin
|
||||
-- signal_force ("/DUT/in2reg3", "00000000000000000000000000000000",
|
||||
-- 500 ns, freeze, 5000 ns, 1);
|
||||
-- wait;
|
||||
-- end process spy_process;
|
||||
|
||||
-- purpose: clock driver
|
||||
-- type : combinational
|
||||
-- inputs :
|
||||
-- outputs:
|
||||
clkprc : process is
|
||||
|
||||
begin -- process clkprc
|
||||
if (not stop_clock) then
|
||||
clk <= '0';
|
||||
wait for clock_period/2.0;
|
||||
clk <= '1';
|
||||
wait for clock_period/2.0;
|
||||
else
|
||||
wait;
|
||||
end if;
|
||||
end process clkprc;
|
||||
|
||||
-- purpose: reset driver
|
||||
-- type : combinational
|
||||
-- inputs :
|
||||
-- outputs:
|
||||
reset_proc : process is
|
||||
|
||||
begin -- process reset_proc
|
||||
|
||||
rst_n <= '0';
|
||||
wait for clock_period * 2.0;
|
||||
rst_n <= '1';
|
||||
wait;
|
||||
end process reset_proc;
|
||||
|
||||
-- purpose: main test loop
|
||||
-- type : combinational
|
||||
-- inputs :
|
||||
-- outputs:
|
||||
tester : process is
|
||||
|
||||
begin -- process tester
|
||||
cmd <= "0110"; -- 16 bit to float32 mode
|
||||
in1 <= "10000000000000000000001000101111"; -- 4.33 ufixed
|
||||
in2 <= "00000000000000000000000000000100"; -- 4
|
||||
floop1: for i in 1 to 100 loop
|
||||
wait for clock_period;
|
||||
end loop floop1;
|
||||
cmd <= "0110"; -- 16 bit to float32 mode
|
||||
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
|
||||
in2 <= "00000000000000000000000000000100"; -- 4
|
||||
floop2: for i in 1 to 100 loop
|
||||
wait for clock_period;
|
||||
end loop floop2;
|
||||
cmd <= "0010";
|
||||
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
in2 <= reverse("00000000000000000001010001000010"); -- 42
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000001010001000010"); -- 42
|
||||
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000001010001000010"); -- 42
|
||||
in2 <= "01000000000000000000000000000000"; -- 2
|
||||
wait for clock_period;
|
||||
in1 <= "00111110101010101010101010101011"; -- 1/3
|
||||
in2 <= "01000000000000000000000000000000"; -- 2
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000001010001000010"); -- 42
|
||||
in2 <= reverse("00000000000000000000101100000011"); -- -6.5
|
||||
wait for clock_period;
|
||||
in1 <= reverse("10000000000000000000000000000000"); -- 2**-149
|
||||
in2 <= "11000000000000000000000000000000"; -- -2.0
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000000001000000000"); -- 2**-127
|
||||
in2 <= "00111110100000000000000000000000"; -- 0.25
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000001010001000010"); -- 42
|
||||
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
wait for clock_period;
|
||||
cmd <= "0001"; -- subtract mode
|
||||
in2 <= "01001011111001110011000110011011"; -- 30303030
|
||||
in1 <= "01001011111001110011000110011100"; -- 30303033
|
||||
wait for clock_period;
|
||||
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
in2 <= "01000000100000000000000000000000"; -- 4
|
||||
wait for clock_period;
|
||||
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
|
||||
in1 <= "01000000100000000000000000000000"; -- 4
|
||||
wait for clock_period;
|
||||
in1 <= "01000000100010101010101010101011"; -- 4.333333
|
||||
in2 <= "00111110101010101010101010101011"; -- 1/3
|
||||
wait for clock_period;
|
||||
cmd <= "0000"; -- add mode
|
||||
in1 <= "00111110101010101010101010101011"; -- 1/3
|
||||
in2 <= "01000000000000000000000000000000"; -- 2
|
||||
wait for clock_period;
|
||||
in2 <= "00111110101010101010101010101011"; -- 1/3
|
||||
in1 <= "01000000000000000000000000000000"; -- 2
|
||||
wait for clock_period;
|
||||
in1 <= "00000000100000000000000000000001"; -- 2**-126
|
||||
in2 <= "01000000100000000000000000000001"; -- 4+
|
||||
wait for clock_period;
|
||||
cmd <= "0011"; -- divide mode
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= "01000000010000000000000000000000"; -- 3.0
|
||||
wait for clock_period;
|
||||
in1 <= "01001100000011001011110001001111"; -- 36892987
|
||||
in2 <= "00000000010000000000000000000000"; -- 2**-127
|
||||
wait for clock_period;
|
||||
in1 <= "10111110101010101010101010101011"; -- -1/3
|
||||
in2 <= "01000000000000000000000000000000"; -- 2
|
||||
wait for clock_period;
|
||||
cmd <= "0100"; -- 32 to 16 conversion mode
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
in1 <= "10111110101010101010101010101011"; -- -1/3, no round
|
||||
wait for clock_period;
|
||||
in1 <= "10111110101010101010101010101011"; -- -1/3
|
||||
in2 <= "00000000000000000000000000000001"; -- opcode 1
|
||||
wait for clock_period;
|
||||
cmd <= "0101"; -- conversion mode
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= "01000000000000000000000000000000"; -- opcode zero
|
||||
wait for clock_period;
|
||||
in1 <= "01000010001010000000000000000000"; -- 42.0
|
||||
in2 <= "00000000000000000000000000000001"; -- opcode 1
|
||||
wait for clock_period;
|
||||
in1 <= "10111111100000000000000000000000"; -- -1.0
|
||||
in2 <= "00000000000000000000000000000010"; -- 2
|
||||
wait for clock_period;
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= "00000000000000000000000000000011"; -- 3
|
||||
wait for clock_period;
|
||||
in1 <= "01000000100010101010101010101011"; -- 4.333333
|
||||
in2 <= "00000000000000000000000000000100"; -- 4
|
||||
wait for clock_period;
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= "00000000000000000000000000000101"; -- 5
|
||||
wait for clock_period;
|
||||
in1 <= "11000000100010101010101010101011"; -- -4.333333
|
||||
in2 <= "00000000000000000000000000000110"; -- 6 to_sfixed
|
||||
wait for clock_period;
|
||||
in1 <= "00111111100000000000000000000000"; -- 1.0
|
||||
in2 <= "00000000000000000000000000000111"; -- 7 to_sfixed
|
||||
wait for clock_period;
|
||||
cmd <= "0110"; -- 16 bit to float32 mode
|
||||
in1 <= "00000000000000000000000000000011"; -- 3
|
||||
in2 <= "01000000000000000000000000000000"; -- mode 0
|
||||
wait for clock_period;
|
||||
in1 <= "00000000000000000000000000000100"; -- 4
|
||||
in2 <= "01000000000000000000000000000001"; -- 1
|
||||
wait for clock_period;
|
||||
in1 <= "00000000000000001111111111111110"; -- -2
|
||||
in2 <= "01000000000000000000000000000010"; -- 2 to_float(signed)
|
||||
wait for clock_period;
|
||||
in1 <= "00000000000000000000000000000100"; -- 4
|
||||
in2 <= "01000000000000000000000000000011"; -- mode 3
|
||||
wait for clock_period;
|
||||
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
|
||||
in2 <= "00000000000000000000000000000100"; -- 4
|
||||
wait for clock_period;
|
||||
in1 <= "10100000000000000000000010000000"; -- 1.0 ufixed
|
||||
in2 <= "00000000000000000000000000000101"; -- 5
|
||||
wait for clock_period;
|
||||
in1 <= "11000000000000001111110111010101"; -- -4.333 sfixed
|
||||
in2 <= "00000000000000000000000000000110"; -- 6
|
||||
wait for clock_period;
|
||||
in1 <= "10100000000000000000000010000000"; -- 1.0 sfixed
|
||||
in2 <= "00000000000000000000000000000111"; -- 7
|
||||
wait for clock_period;
|
||||
cmd <= "0111"; -- Mod
|
||||
in1 <= "00000000000000000000000000000011"; --
|
||||
in2 <= "00000000000000000000000000000011"; --
|
||||
wait for clock_period;
|
||||
in1 <= "00000010001100101111000100111011"; -- 36892987
|
||||
in2 <= "00000010001100101111000100111011"; -- 36892987
|
||||
wait for clock_period;
|
||||
in1 <= "11000000100010101010101010101011"; -- -4.333333
|
||||
in2 <= "01000000100000000000000000000000"; -- 4
|
||||
wait for clock_period;
|
||||
cmd <= "1000"; -- rem
|
||||
in1 <= "00000000000000000000000000000011"; --
|
||||
in2 <= "00000000000000000000000000000011"; --
|
||||
wait for clock_period;
|
||||
in1 <= "00000010001100101111000100111011"; -- 36892987
|
||||
in2 <= "00000010001100101111000100111011"; -- 36892987
|
||||
wait for clock_period;
|
||||
in1 <= "11000000100010101010101010101011"; -- -4.333333
|
||||
in2 <= "01000000100000000000000000000000"; -- 4
|
||||
wait for clock_period;
|
||||
cmd <= "1001"; -- constants conversion
|
||||
in2 <= "11000000000000000000000000000000"; -- command 0
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000001"; -- command 1
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000010"; -- command 2
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000011"; -- command 3
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000100"; -- command 4
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000101"; -- command 5
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000110"; -- command 6
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000111"; -- command 7
|
||||
wait for clock_period;
|
||||
cmd <= "1010"; -- conversions
|
||||
in1 <= to_float (1, in1);
|
||||
in2 <= "11000000000000000000000000000000"; -- command 0
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-2, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000001"; -- command 1
|
||||
wait for clock_period;
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "00010000000000000000000000000010"; -- command 2 scalb
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11110000000000000000000000000010"; -- command 2 scalb
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000011"; -- command 3 logb
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000011"; -- command 3 logb
|
||||
in1 <= to_float (0.25, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000100"; -- 4 nextafter
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (4, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000101"; -- 5 nextafter
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-4, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000110"; -- 6 nextafter
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (4, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "11000000000000000000000000000111"; -- 7 nextafter
|
||||
in1 <= to_float (1, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-4, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1011"; -- copy sign
|
||||
in1 <= to_float (2, in1);
|
||||
in2 <= to_float (2, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-3, in1);
|
||||
in2 <= to_float (3, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (4, in1);
|
||||
in2 <= to_float (-4, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-5, in1);
|
||||
in2 <= to_float (-5, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1100"; -- compare test
|
||||
in1 <= to_float (15, in1);
|
||||
in2 <= to_float (15, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (15.5, in1);
|
||||
in2 <= to_float (-2, in1);
|
||||
wait for clock_period;
|
||||
in1 <= to_float (-2, in1);
|
||||
in2 <= to_float (2, in1);
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= to_float (-2, in1);
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000001"; -- NAN
|
||||
in2 <= to_float (-2, in1);
|
||||
wait for clock_period;
|
||||
cmd <= "1101"; -- boolean test
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000000"; -- command 0 , not
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000001"; -- command 1, and
|
||||
wait for clock_period;
|
||||
in1 <= "01111111000000000000000000000000"; -- + inf
|
||||
in2 <= "00111111000000000000000000000010"; -- command 2, or
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000011"; -- command 3, nand
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000100"; -- command 4, nor
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000101"; -- command 5, xor
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000110"; -- command 6, xnor
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000111"; -- command 7, xor '1'
|
||||
wait for clock_period;
|
||||
cmd <= "1110"; -- reduce and vector test test
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000000"; -- command 0,
|
||||
wait for clock_period;
|
||||
in1 <= "11111111111111111111111111111111"; -- all 1
|
||||
wait for clock_period;
|
||||
in1 <= "10000000000000000000000000000000"; -- -0
|
||||
wait for clock_period;
|
||||
in1 <= "00000000000000000000000000000000"; -- 0
|
||||
wait for clock_period;
|
||||
in1 <= "01111111100000000000000000000000"; -- + inf
|
||||
in2 <= "00111111100000000000000000000001"; -- command 1, and '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000001"; -- command 1, and '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000010"; -- command 2, or '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000010"; -- command 2, or '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000011"; -- command 3, nand '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000011"; -- command 3, nand '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000100"; -- command 4, nor '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000100"; -- command 4, nor '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000101"; -- command 5, xor '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000101"; -- command 5, xor '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000110"; -- command 6, xnor '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000110"; -- command 6, xnor '1'
|
||||
wait for clock_period;
|
||||
in2 <= "00111111100000000000000000000111"; -- command 7, and '0'
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000111"; -- command 7, and '1'
|
||||
wait for clock_period;
|
||||
cmd <= "1111"; -- add and mult by constant
|
||||
in2 <= "10111111100000000000000000000000"; -- command 0, + 1
|
||||
in1 <= to_float (2, in1);
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000001"; -- command 1, 1 +
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000010"; -- command 2, + 1.0
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000011"; -- command 3, 1.0 +
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000100"; -- command 4, * 1
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000101"; -- command 5, 1 *
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000110"; -- command 6, * 1.0
|
||||
wait for clock_period;
|
||||
in2 <= "10111111100000000000000000000111"; -- command 7, 1.0 *
|
||||
wait for clock_period;
|
||||
|
||||
|
||||
wait for clock_period;
|
||||
cmd <= "0000"; -- add mode
|
||||
in1 <= (others => '0');
|
||||
in2 <= (others => '0');
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
wait;
|
||||
end process tester;
|
||||
|
||||
-- purpose: check the output of the tester
|
||||
-- type : combinational
|
||||
-- inputs :
|
||||
-- outputs:
|
||||
checktest : process is
|
||||
variable out16, out16t : fp16; -- 16 bit fp variables
|
||||
variable out1t, out2t : float32; -- 32 bit float
|
||||
variable s16, s16t : SIGNED(7 downto 0); -- 7 bit SIGNED
|
||||
variable latency : INTEGER := 0;
|
||||
begin -- process checktest
|
||||
wait for clock_period/2.0;
|
||||
floop3: for i in 1 to 100 loop
|
||||
wait for clock_period;
|
||||
end loop floop3;
|
||||
latency := 0;
|
||||
out2t := "01000000100010101100000000000000";
|
||||
wl1: while out1 /= out2t loop
|
||||
wait for clock_period;
|
||||
latency := latency + 1;
|
||||
assert latency /= 100 report "After 100 loops, pattern never found"
|
||||
severity failure;
|
||||
end loop wl1;
|
||||
report "Latency was " & INTEGER'image(latency) severity note;
|
||||
floop4: for i in 1 to 100 loop
|
||||
wait for clock_period;
|
||||
end loop floop4;
|
||||
report_error ("42 * 6.5 error",
|
||||
out1,
|
||||
to_float (273, out1));
|
||||
wait for clock_period;
|
||||
report_error ("6.5 * 42 error",
|
||||
out1,
|
||||
to_float (273, out1'high, -out1'low));
|
||||
wait for clock_period;
|
||||
report_error ("Multiply 42.25 miscompare",
|
||||
out1,
|
||||
"01000010001010010000000000000000"); -- 42.25
|
||||
wait for clock_period;
|
||||
report_error ("Multiply 84 miscompare",
|
||||
out1,
|
||||
"01000010101010000000000000000000"); -- 84
|
||||
wait for clock_period;
|
||||
report_error ("Multiply 2/3 miscompare",
|
||||
out1,
|
||||
"00111111001010101010101010101011"); -- 2/3
|
||||
wait for clock_period;
|
||||
report_error ("Multiply -273 miscompare",
|
||||
out1,
|
||||
"11000011100010001000000000000000"); -- -273
|
||||
wait for clock_period;
|
||||
report_error ("mult 2**-148 test miscompare",
|
||||
out1,
|
||||
reverse("01000000000000000000000000000001")); -- -2*-148
|
||||
wait for clock_period;
|
||||
report_error ("Multiply 2**-129 miscompare",
|
||||
out1,
|
||||
reverse("00000000000000000000100000000000")); -- 2**-129
|
||||
wait for clock_period;
|
||||
report_error ("6.5 * 42 error",
|
||||
out1,
|
||||
to_float (273, out1));
|
||||
wait for clock_period;
|
||||
report_error ("Subtract 30303033 - 30303030 miscompare",
|
||||
out1,
|
||||
"01000000000000000000000000000000"); -- 2 (not 3, rounding)
|
||||
wait for clock_period;
|
||||
report_error ("Subtract 6.5 - 4 miscompare",
|
||||
out1,
|
||||
"01000000001000000000000000000000"); -- 2.5
|
||||
wait for clock_period;
|
||||
report_error ("Subtract 4 - 6.5 miscompare",
|
||||
out1,
|
||||
"11000000001000000000000000000000"); -- -2.5
|
||||
wait for clock_period;
|
||||
report_error ("Subtract 4.333 - 1/3 miscompare",
|
||||
out1,
|
||||
"01000000100000000000000000000000"); -- 4
|
||||
wait for clock_period;
|
||||
report_error ("Add 2.333 miscompare",
|
||||
out1,
|
||||
"01000000000101010101010101010101"); -- 2.333333
|
||||
wait for clock_period;
|
||||
report_error ("Add 2.333 rev miscompare",
|
||||
out1,
|
||||
"01000000000101010101010101010101"); -- 2.333333
|
||||
wait for clock_period;
|
||||
report_error ("Add 4 + miscompare",
|
||||
out1,
|
||||
"01000000100000000000000000000001"); -- 4
|
||||
wait for clock_period;
|
||||
report_error ("div 1/3 test miscompare",
|
||||
out1,
|
||||
"00111110101010101010101010101011"); -- 1/3
|
||||
wait for clock_period;
|
||||
report_error ("div 369297/2**-126 test miscompare",
|
||||
out1,
|
||||
"01111111100000000000000000000000");
|
||||
wait for clock_period;
|
||||
report_error ("-1/6 test miscompare",
|
||||
out1, "10111110001010101010101010101011"); -- -1/6
|
||||
wait for clock_period;
|
||||
-- resize function
|
||||
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
|
||||
out16t := to_float (1, out16t);
|
||||
report_error16 ("1.0 fp16 converserion",
|
||||
out16, out16t);
|
||||
wait for clock_period;
|
||||
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
|
||||
out16t := to_float (arg => -1.0/3.0, size_res => out16t,
|
||||
round_style => round_zero);
|
||||
report_error16 ("-1/3 not rounded fp16 converserion",
|
||||
out16, out16t);
|
||||
wait for clock_period;
|
||||
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
|
||||
out16t := to_float (-1.0/3.0, out16t);
|
||||
report_error16 ("-1/3 fp16 converserion",
|
||||
out16, out16t);
|
||||
-- conversion test
|
||||
wait for clock_period;
|
||||
report_error ("1.0 to unsigned miscompare",
|
||||
out1, "00000000000000000000000000000001");
|
||||
wait for clock_period;
|
||||
report_error ("42 to unsigned miscompare",
|
||||
out1, "00100000000000000000000000101010");
|
||||
wait for clock_period;
|
||||
report_error ("-1.0 to signed miscompare",
|
||||
out1, "01000000000000001111111111111111");
|
||||
wait for clock_period;
|
||||
report_error ("1.0 to signed miscompare",
|
||||
out1, "01100000000000000000000000000001");
|
||||
wait for clock_period;
|
||||
report_error ("4.33 to ufixed miscompare",
|
||||
out1, "10000000000000000000001000101011");
|
||||
wait for clock_period;
|
||||
report_error ("1.0 to ufixed miscompare",
|
||||
out1, "10100000000000000000000010000000");
|
||||
wait for clock_period;
|
||||
report_error ("4.333 to sfixed miscompare",
|
||||
out1, "11000000000000001111110111010101");
|
||||
wait for clock_period;
|
||||
report_error ("1.0 to sfixed miscompare",
|
||||
out1, "11100000000000000000000010000000");
|
||||
wait for clock_period;
|
||||
report_error ("unsigned 3 to float miscompare",
|
||||
out1, to_float(3, out1));
|
||||
wait for clock_period;
|
||||
report_error ("unsigned 4 to float miscompare",
|
||||
out1, to_float(4, out1));
|
||||
wait for clock_period;
|
||||
report_error ("signed -2 to float miscompare",
|
||||
out1, to_float(-2, out1));
|
||||
wait for clock_period;
|
||||
report_error ("signed 4 to float miscompare",
|
||||
out1, to_float(4, out1));
|
||||
wait for clock_period;
|
||||
report_error ("ufixed 4.333 to float miscompare",
|
||||
out1, "01000000100010101100000000000000"); -- 4.333333
|
||||
wait for clock_period;
|
||||
report_error ("ufixed 1.0 to float miscompare",
|
||||
out1, "00111111100000000000000000000000"); -- 1.0
|
||||
wait for clock_period;
|
||||
report_error ("sfixed -4.333 to float miscompare",
|
||||
out1, "11000000100010101100000000000000"); -- -4.333333
|
||||
wait for clock_period;
|
||||
report_error ("sfixed 1.0 to float miscompare",
|
||||
out1, "00111111100000000000000000000000"); -- 1.0
|
||||
wait for clock_period;
|
||||
report_error ("denormal mod denormal miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
report_error ("large mod large miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
report_error ("-4.333 mod 4 miscompare",
|
||||
out1,
|
||||
from_string ("01000000011010101010101010101010", out1));
|
||||
wait for clock_period;
|
||||
report_error ("denormal rem denormal miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
report_error ("large rem large miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
out1t := "10111110101010101010101010110000";
|
||||
report_error ("-4.333 rem 4 miscompare",
|
||||
out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("to_float(0) miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
report_error ("to_float(0.0) miscompare",
|
||||
out1, zero0);
|
||||
wait for clock_period;
|
||||
report_error ("to_float(8) miscompare",
|
||||
out1, to_float(8.0, out1));
|
||||
wait for clock_period;
|
||||
report_error ("to_float(8.0) miscompare",
|
||||
out1, to_float(8, out1));
|
||||
wait for clock_period;
|
||||
report_error ("to_float(-8) miscompare",
|
||||
out1, to_float(-8.0, out1));
|
||||
wait for clock_period;
|
||||
report_error ("to_float(-8.0) miscompare",
|
||||
out1, to_float(-8, out1));
|
||||
wait for clock_period;
|
||||
report_error ("to_float(27000) miscompare",
|
||||
out1, to_float(27000.0, out1));
|
||||
wait for clock_period;
|
||||
report_error ("to_float(PI) miscompare",
|
||||
out1, to_float(3.141592653589, out1));
|
||||
-- Conversion test
|
||||
wait for clock_period;
|
||||
report_error ("-1 miscompare",
|
||||
out1, to_float(-1, out1));
|
||||
wait for clock_period;
|
||||
report_error ("-(-2) miscompare",
|
||||
out1, to_float(2, out1));
|
||||
wait for clock_period;
|
||||
report_error ("abs(-2) miscompare",
|
||||
out1, to_float(2, out1));
|
||||
wait for clock_period;
|
||||
report_error ("abs(1) miscompare",
|
||||
out1, to_float(1, out1));
|
||||
wait for clock_period;
|
||||
report_error ("scalb (1, 1) miscompare",
|
||||
out1, to_float(2, out1));
|
||||
wait for clock_period;
|
||||
report_error ("scalb (1, -1) miscompare",
|
||||
out1, to_float(0.5, out1));
|
||||
wait for clock_period;
|
||||
s16 := SIGNED (to_slv (out1(-16 downto -23)));
|
||||
assert (s16 = 0) report "logb (1) returned "
|
||||
& to_string(to_sfixed(s16)) severity error;
|
||||
wait for clock_period;
|
||||
s16 := SIGNED (to_slv (out1(-16 downto -23)));
|
||||
assert (s16 = -2) report "logb (0.25) returned "
|
||||
& to_string(to_sfixed(s16)) severity error;
|
||||
wait for clock_period;
|
||||
out1t := "00111111100000000000000000000001";
|
||||
report_error ("nextafter (1, 1.5)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01000000011111111111111111111111";
|
||||
report_error ("nextafter (4, 1.5)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00111111011111111111111111111111";
|
||||
report_error ("nextafter (1, -1.5)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "11000000011111111111111111111111";
|
||||
report_error ("nextafter (-4, -1.5)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00111111100000000000000000000001";
|
||||
report_error ("nextafter (1, inf)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01000000100000000000000000000001";
|
||||
report_error ("nextafter (4, inf)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00111111011111111111111111111111";
|
||||
report_error ("nextafter (1, neginf)", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "11000000100000000000000000000001";
|
||||
report_error ("nextafter (-4, neginf)", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("Copysign (2,2)", out1, to_float(2, out1));
|
||||
wait for clock_period;
|
||||
report_error ("Copysign (-3,3)", out1, to_float(3, out1));
|
||||
wait for clock_period;
|
||||
report_error ("Copysign (4,-4)", out1, to_float(-4, out1));
|
||||
wait for clock_period;
|
||||
report_error ("Copysign (-5,-5)", out1, to_float(-5, out1));
|
||||
wait for clock_period;
|
||||
out1t := "10001110000000000000000000000000";
|
||||
report_error ("compare test 15, 15", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01101001000000000000000000000000";
|
||||
report_error ("compare test 15.5, -2", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01010100000000000000000000000000";
|
||||
report_error ("compare test -2, 2", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01101000010000000000000000000000";
|
||||
report_error ("compare test inf, -2", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01000000101000000000000000000000";
|
||||
report_error ("compare test NAN, -2", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- not + inf
|
||||
report_error ("not +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00111111100000000000000000000000"; -- and
|
||||
report_error ("and +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111000000000000000000000010"; -- or
|
||||
report_error ("or +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "11000000011111111111111111111111"; -- nand
|
||||
report_error ("nand +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111011"; -- nor
|
||||
report_error ("nor +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01000000000000000000000000000101"; -- xor
|
||||
report_error ("xor +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10111111111111111111111111111001"; -- xnor
|
||||
report_error ("xnor +inf", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- xnor '1'
|
||||
report_error ("+inf xor '1'", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01100100000000000000000000000000"; -- reduce test
|
||||
report_error ("_reduce test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10100100000000000000000000000000"; -- reduce test
|
||||
report_error ("_reduce all 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01101000000000000000000000000000"; -- reduce test
|
||||
report_error ("_reduce -0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01010100000000000000000000000000"; -- reduce test
|
||||
report_error ("_reduce 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00000000000000000000000000000000"; -- 0
|
||||
report_error ("and 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111100000000000000000000000"; -- + inf
|
||||
report_error ("and 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111100000000000000000000000"; -- + inf
|
||||
report_error ("or 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "11111111111111111111111111111111"; -- all 1
|
||||
assert (to_slv (out1) = to_slv (out1t))
|
||||
report "or 1 test error " & to_string (out1) & " /= "
|
||||
& to_string (out1t) severity error;
|
||||
wait for clock_period;
|
||||
out1t := "11111111111111111111111111111111"; -- all 1
|
||||
assert (to_slv (out1) = to_slv (out1t))
|
||||
report "nand 0 test error " & to_string (out1) & " /= "
|
||||
& to_string (out1t) severity error;
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- - denormal
|
||||
report_error ("nand 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- - denormal
|
||||
report_error ("nor 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00000000000000000000000000000000"; -- 0
|
||||
report_error ("nor 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111100000000000000000000000"; -- + inf
|
||||
report_error ("xor 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- - denormal
|
||||
report_error ("xor 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "10000000011111111111111111111111"; -- - denormal
|
||||
report_error ("xnor 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111100000000000000000000000"; -- + inf
|
||||
report_error ("xnor 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "00000000000000000000000000000000"; -- 0
|
||||
report_error ("and 0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := "01111111100000000000000000000000"; -- + inf
|
||||
report_error ("and 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := to_float(3, out1t);
|
||||
report_error ("2 + 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("1 + 2 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("2 + 1.0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("1.0 + 2 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
out1t := to_float(2, out1t);
|
||||
report_error ("2 * 1 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("1 * 2 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("2 * 1.0 test", out1, out1t);
|
||||
wait for clock_period;
|
||||
report_error ("1.0 * 2 test", out1, out1t);
|
||||
|
||||
wait for clock_period;
|
||||
assert (false) report "Testing complete" severity note;
|
||||
stop_clock <= true;
|
||||
wait;
|
||||
end process checktest;
|
||||
end architecture testbench;
|
||||
@@ -1,26 +0,0 @@
|
||||
# -------------------------------------------------
|
||||
# Compile script for GHDL
|
||||
# -------------------------------------------------
|
||||
include ../make/defs.mk
|
||||
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
|
||||
WORK_LIB := unisim
|
||||
TARGET := unisim
|
||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
SRCS := $(LIB_PATH)/unisims/unisim_VPKG.vhd
|
||||
SRCS += $(LIB_PATH)/unisims/unisim_VCOMP.vhd
|
||||
SRCS += $(LIB_PATH)/unisims/unisim_SMODEL.vhd
|
||||
SRCS += $(LIB_PATH)/unisims/unisim_VITAL.vhd
|
||||
|
||||
GHDL_OPTS := -fsynopsys -fexplicit
|
||||
|
||||
include ../make/ghdl.mk
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,675 +0,0 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
# Bus clock nets
|
||||
NET "sys_clk" TNM_NET = "sys_clk";
|
||||
NET "tft_clk" TNM_NET = "tft_clk";
|
||||
NET sys_clk_in TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET sys_clk_in LOC = AE14;
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_rst_in LOC = D6;
|
||||
NET sys_rst_in PULLUP;
|
||||
NET sys_rst_in TIG;
|
||||
|
||||
NET uart_RX LOC = W2;
|
||||
NET uart_RX IOSTANDARD = LVCMOS33;
|
||||
NET uart_RX TIG;
|
||||
NET uart_TX LOC = W1;
|
||||
NET uart_TX IOSTANDARD = LVCMOS33;
|
||||
NET uart_TX TIG;
|
||||
|
||||
NET ext_irq TIG;
|
||||
|
||||
# Reset timing ignore - treat as async paths
|
||||
NET sys_rst TIG;
|
||||
NET opb_v20_0_OPB_Rst TIG;
|
||||
NET lmb_v10_1_OPB_Rst TIG;
|
||||
NET lmb_v10_0_OPB_Rst TIG;
|
||||
NET opb_v20_0_Debug_SYS_Rst TIG;
|
||||
NET Debug_Rst TIG;
|
||||
NET plb_v34_0_PLB_Rst TIG;
|
||||
NET dcm_locked TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
|
||||
INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
|
||||
INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
|
||||
|
||||
INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0;
|
||||
INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
|
||||
INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
|
||||
|
||||
INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31;
|
||||
INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
# GPLED 0-3
|
||||
NET gpio<0> LOC = G5; #GPLED0
|
||||
NET gpio<1> LOC = G6; #GPLED1
|
||||
NET gpio<2> LOC = A11; #GPLED2
|
||||
NET gpio<3> LOC = A12; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET gpio<4> LOC = C6; # C LED
|
||||
NET gpio<5> LOC = F9; # W LED
|
||||
NET gpio<6> LOC = A5; # S LED
|
||||
NET gpio<7> LOC = E10; # E LED
|
||||
NET gpio<8> LOC = E2; # N LED
|
||||
# North-East-South-West-Center Buttons
|
||||
NET gpio<9> LOC = B6; # C Button
|
||||
NET gpio<10> LOC = E9; # W Button
|
||||
NET gpio<11> LOC = A6; # S Button
|
||||
NET gpio<12> LOC = F10; # E Button
|
||||
NET gpio<13> LOC = E7; # N Button
|
||||
# Dip Switches 1-8
|
||||
NET gpio<14> LOC = U24; # DIP SW 8
|
||||
NET gpio<15> LOC = U25; # DIP SW 7
|
||||
NET gpio<16> LOC = V23; # DIP SW 6
|
||||
NET gpio<17> LOC = U23; # DIP SW 5
|
||||
NET gpio<18> LOC = U26; # DIP SW 4
|
||||
NET gpio<19> LOC = T26; # DIP SW 3
|
||||
NET gpio<20> LOC = R19; # DIP SW 2
|
||||
NET gpio<21> LOC = R20; # DIP SW 1
|
||||
NET gpio<14> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<15> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<16> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<17> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<18> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<19> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<20> IOSTANDARD = LVCMOS33;
|
||||
NET gpio<21> IOSTANDARD = LVCMOS33;
|
||||
#SMA Connectors
|
||||
NET gpio<22> LOC = C12; # SMA_IN_N
|
||||
NET gpio<23> LOC = C13; # SMA_IN_P
|
||||
NET gpio<24> LOC = D7; # SMA_OUT_N
|
||||
NET gpio<25> LOC = D8; # SMA_OUT_P
|
||||
NET gpio<26> LOC = AD12;# USERCLK
|
||||
NET gpio<26> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "gpio<*>" PULLDOWN;
|
||||
NET "gpio<*>" TIG;
|
||||
NET "gpio<*>" SLEW = SLOW;
|
||||
NET "gpio<*>" DRIVE = 2;
|
||||
|
||||
NET "gpio<22>" SLEW = FAST;
|
||||
NET "gpio<22>" DRIVE = 12;
|
||||
NET "gpio<23>" SLEW = FAST;
|
||||
NET "gpio<23>" DRIVE = 12;
|
||||
NET "gpio<24>" SLEW = FAST;
|
||||
NET "gpio<24>" DRIVE = 12;
|
||||
NET "gpio<25>" SLEW = FAST;
|
||||
NET "gpio<25>" DRIVE = 12;
|
||||
|
||||
NET "gpio2_d_out<*>" TIG;
|
||||
NET "gpio2_t_out<*>" TIG;
|
||||
NET "gpio2_in<*>" TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for PS/2 Ports
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#Keyboard
|
||||
NET ps2_keyb_clk LOC = D2;
|
||||
NET ps2_keyb_clk SLEW = SLOW;
|
||||
NET ps2_keyb_clk DRIVE = 2;
|
||||
NET ps2_keyb_clk TIG;
|
||||
NET ps2_keyb_data LOC = G9;
|
||||
NET ps2_keyb_data SLEW = SLOW;
|
||||
NET ps2_keyb_data DRIVE = 2;
|
||||
NET ps2_keyb_data TIG;
|
||||
|
||||
#Mouse
|
||||
NET ps2_mouse_clk LOC = B14;
|
||||
NET ps2_mouse_clk SLEW = SLOW;
|
||||
NET ps2_mouse_clk DRIVE = 2;
|
||||
NET ps2_mouse_clk TIG;
|
||||
NET ps2_mouse_data LOC = C14;
|
||||
NET ps2_mouse_data SLEW = SLOW;
|
||||
NET ps2_mouse_data DRIVE = 2;
|
||||
NET ps2_mouse_data TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for IIC Controller
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET iic_scl LOC = A17;
|
||||
NET iic_sda LOC = B17;
|
||||
NET iic_scl SLEW = SLOW;
|
||||
NET iic_scl DRIVE = 6;
|
||||
NET iic_scl TIG;
|
||||
NET iic_sda SLEW = SLOW;
|
||||
NET iic_sda DRIVE = 6;
|
||||
NET iic_sda TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for AC97 Sound Controller
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET ac97_bit_clk LOC = AE10;
|
||||
NET ac97_bit_clk IOSTANDARD = LVCMOS33;
|
||||
NET ac97_bit_clk PERIOD = 80;
|
||||
NET ac97_sdata_in LOC = AD16;
|
||||
NET ac97_sdata_in IOSTANDARD = LVCMOS33;
|
||||
NET ac97_reset_n LOC = AD10;
|
||||
NET ac97_reset_n IOSTANDARD = LVCMOS33;
|
||||
NET ac97_reset_n TIG;
|
||||
NET ac97_sdata_out LOC = C8;
|
||||
NET ac97_sync LOC = D9;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for System ACE MPU / USB
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sysace_clk_in LOC = AF11;
|
||||
NET sysace_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sysace_clk_in TNM_NET = "sysace_clk_in";
|
||||
# Leave 1 ns margin
|
||||
TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
|
||||
|
||||
NET sace_usb_a<0> LOC = U22;
|
||||
NET sace_usb_a<1> LOC = Y10;
|
||||
NET sace_usb_a<2> LOC = AA10;
|
||||
NET sace_usb_a<3> LOC = AC7;
|
||||
NET sace_usb_a<4> LOC = Y7;
|
||||
NET sace_usb_a<5> LOC = AA9;
|
||||
NET sace_usb_a<6> LOC = Y9;
|
||||
NET sace_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
NET sace_usb_a<*> SLEW = FAST;
|
||||
NET sace_usb_a<*> DRIVE = 8;
|
||||
NET sace_mpce LOC = AD5;
|
||||
NET sace_mpce IOSTANDARD = LVCMOS33;
|
||||
NET sace_mpce SLEW = FAST;
|
||||
NET sace_mpce DRIVE = 8;
|
||||
NET sace_usb_d<0> LOC = AB7;
|
||||
NET sace_usb_d<1> LOC = AC9;
|
||||
NET sace_usb_d<2> LOC = AB9;
|
||||
NET sace_usb_d<3> LOC = AE6;
|
||||
NET sace_usb_d<4> LOC = AD6;
|
||||
NET sace_usb_d<5> LOC = AF9;
|
||||
NET sace_usb_d<6> LOC = AE9;
|
||||
NET sace_usb_d<7> LOC = AD8;
|
||||
NET sace_usb_d<8> LOC = AC8;
|
||||
NET sace_usb_d<9> LOC = AF4;
|
||||
NET sace_usb_d<10> LOC = AE4;
|
||||
NET sace_usb_d<11> LOC = AD3;
|
||||
NET sace_usb_d<12> LOC = AC3;
|
||||
NET sace_usb_d<13> LOC = AF6;
|
||||
NET sace_usb_d<14> LOC = AF5;
|
||||
NET sace_usb_d<15> LOC = AA7;
|
||||
NET sace_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sace_usb_d<*> SLEW = FAST;
|
||||
NET sace_usb_d<*> DRIVE = 8;
|
||||
NET sace_usb_d<*> PULLDOWN;
|
||||
NET sace_usb_oen LOC = AA8;
|
||||
NET sace_usb_oen IOSTANDARD = LVCMOS33;
|
||||
NET sace_usb_oen SLEW = FAST;
|
||||
NET sace_usb_oen DRIVE = 8;
|
||||
NET sace_usb_wen LOC = Y8;
|
||||
NET sace_usb_wen IOSTANDARD = LVCMOS33;
|
||||
NET sace_usb_wen SLEW = FAST;
|
||||
NET sace_usb_wen DRIVE = 8;
|
||||
NET sysace_mpirq LOC = AD4;
|
||||
NET sysace_mpirq IOSTANDARD = LVCMOS33;
|
||||
NET sysace_mpirq TIG;
|
||||
NET sysace_mpirq PULLDOWN;
|
||||
|
||||
NET usb_csn LOC = AF10;
|
||||
NET usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET usb_csn SLEW = FAST;
|
||||
NET usb_csn DRIVE = 8;
|
||||
NET usb_hpi_reset_n LOC = A7;
|
||||
NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
|
||||
NET usb_hpi_reset_n TIG;
|
||||
NET usb_hpi_int LOC = V5;
|
||||
NET usb_hpi_int IOSTANDARD = LVCMOS33;
|
||||
NET usb_hpi_int TIG;
|
||||
NET usb_hpi_int PULLDOWN;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET ddr_ad<0> LOC = C26; # DDR_A0
|
||||
NET ddr_ad<1> LOC = E17; # DDR_A1
|
||||
NET ddr_ad<2> LOC = D18; # DDR_A2
|
||||
NET ddr_ad<3> LOC = C19; # DDR_A3
|
||||
NET ddr_ad<4> LOC = F17; # DDR_A4
|
||||
NET ddr_ad<5> LOC = B18; # DDR_A5
|
||||
NET ddr_ad<6> LOC = B20; # DDR_A6
|
||||
NET ddr_ad<7> LOC = C20; # DDR_A7
|
||||
NET ddr_ad<8> LOC = D20; # DDR_A8
|
||||
NET ddr_ad<9> LOC = C21; # DDR_A9
|
||||
NET ddr_ad<10> LOC = A18; # DDR_A10
|
||||
NET ddr_ad<11> LOC = B21; # DDR_A11
|
||||
NET ddr_ad<12> LOC = A24; # DDR_A12
|
||||
NET ddr_ba<0> LOC = B12; # DDR_BA0
|
||||
NET ddr_ba<1> LOC = A16; # DDR_BA1
|
||||
NET ddr_casb LOC = F23; # DDR_CAS_N
|
||||
NET ddr_cke LOC = G22; # DDR_CKE
|
||||
NET ddr_csb LOC = G21; # DDR_CS_N
|
||||
NET ddr_rasb LOC = F24; # DDR_RAS_N
|
||||
NET ddr_web LOC = A23; # DDR_WE_N
|
||||
|
||||
NET ddr_clk LOC = A10; # DDR_CK1_P
|
||||
NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET ddr_clkb LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET ddr_dm<0> LOC = G19; # DDR_DM0
|
||||
NET ddr_dm<1> LOC = G24; # DDR_DM1
|
||||
NET ddr_dm<2> LOC = G20; # DDR_DM2
|
||||
NET ddr_dm<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET ddr_dqs<0> LOC = D25; # DDR_DQS0
|
||||
NET ddr_dqs<1> LOC = G18; # DDR_DQS1
|
||||
NET ddr_dqs<2> LOC = G17; # DDR_DQS2
|
||||
NET ddr_dqs<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET ddr_dq<0> LOC = H20; # DDR_D0
|
||||
NET ddr_dq<1> LOC = E23; # DDR_D1
|
||||
NET ddr_dq<2> LOC = H26; # DDR_D2
|
||||
NET ddr_dq<3> LOC = H22; # DDR_D3
|
||||
NET ddr_dq<4> LOC = E25; # DDR_D4
|
||||
NET ddr_dq<5> LOC = E26; # DDR_D5
|
||||
NET ddr_dq<6> LOC = F26; # DDR_D6
|
||||
NET ddr_dq<7> LOC = E24; # DDR_D7
|
||||
NET ddr_dq<8> LOC = E20; # DDR_D8
|
||||
NET ddr_dq<9> LOC = A22; # DDR_D9
|
||||
NET ddr_dq<10> LOC = C23; # DDR_D10
|
||||
NET ddr_dq<11> LOC = C24; # DDR_D11
|
||||
NET ddr_dq<12> LOC = A20; # DDR_D12
|
||||
NET ddr_dq<13> LOC = A21; # DDR_D13
|
||||
NET ddr_dq<14> LOC = D24; # DDR_D14
|
||||
NET ddr_dq<15> LOC = E18; # DDR_D15
|
||||
NET ddr_dq<16> LOC = F18; # DDR_D16
|
||||
NET ddr_dq<17> LOC = A19; # DDR_D17
|
||||
NET ddr_dq<18> LOC = F19; # DDR_D18
|
||||
NET ddr_dq<19> LOC = B23; # DDR_D19
|
||||
NET ddr_dq<20> LOC = E21; # DDR_D20
|
||||
NET ddr_dq<21> LOC = D22; # DDR_D21
|
||||
NET ddr_dq<22> LOC = D23; # DDR_D22
|
||||
NET ddr_dq<23> LOC = B24; # DDR_D23
|
||||
NET ddr_dq<24> LOC = E22; # DDR_D24
|
||||
NET ddr_dq<25> LOC = F20; # DDR_D25
|
||||
NET ddr_dq<26> LOC = H23; # DDR_D26
|
||||
NET ddr_dq<27> LOC = G25; # DDR_D27
|
||||
NET ddr_dq<28> LOC = G26; # DDR_D28
|
||||
NET ddr_dq<29> LOC = H25; # DDR_D29
|
||||
NET ddr_dq<30> LOC = H24; # DDR_D30
|
||||
NET ddr_dq<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET ddr_ad<*> IOSTANDARD = SSTL2_I;
|
||||
NET ddr_ba<*> IOSTANDARD = SSTL2_I;
|
||||
NET ddr_casb IOSTANDARD = SSTL2_I;
|
||||
NET ddr_cke IOSTANDARD = SSTL2_I;
|
||||
NET ddr_clk IOSTANDARD = SSTL2_I;
|
||||
NET ddr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET ddr_clkb IOSTANDARD = SSTL2_I;
|
||||
NET ddr_casb IOSTANDARD = SSTL2_I;
|
||||
NET ddr_csb IOSTANDARD = SSTL2_I;
|
||||
NET ddr_rasb IOSTANDARD = SSTL2_I;
|
||||
NET ddr_web IOSTANDARD = SSTL2_I;
|
||||
|
||||
NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
|
||||
NET ddr_dm<*> IOSTANDARD = SSTL2_II;
|
||||
NET ddr_dq<*> IOSTANDARD = SSTL2_II;
|
||||
|
||||
// Timing Constraint for DDR Feedback Clock
|
||||
NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
|
||||
TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET tft_lcd_b<0> LOC = L26; # VGA_B2
|
||||
NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
|
||||
NET tft_lcd_b<1> LOC = C5; # VGA_B3
|
||||
NET tft_lcd_b<2> LOC = C7; # VGA_B4
|
||||
NET tft_lcd_b<3> LOC = B7; # VGA_B5
|
||||
NET tft_lcd_b<4> LOC = G8; # VGA_B6
|
||||
NET tft_lcd_b<5> LOC = F8; # VGA_B7
|
||||
NET tft_lcd_b<*> SLEW = FAST;
|
||||
NET tft_lcd_b<*> DRIVE = 8;
|
||||
|
||||
NET tft_lcd_clk LOC = AF8;
|
||||
NET tft_lcd_clk IOSTANDARD = LVDCI_33;
|
||||
NET tft_lcd_clk SLEW = FAST;
|
||||
NET tft_lcd_clk DRIVE = 8;
|
||||
|
||||
NET tft_lcd_g<0> LOC = M20; # VGA_G2
|
||||
NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
|
||||
NET tft_lcd_g<1> LOC = E4; # VGA_G3
|
||||
NET tft_lcd_g<2> LOC = D3; # VGA_G4
|
||||
NET tft_lcd_g<3> LOC = H7; # VGA_G5
|
||||
NET tft_lcd_g<4> LOC = H8; # VGA_G6
|
||||
NET tft_lcd_g<5> LOC = C1; # VGA_G7
|
||||
NET tft_lcd_g<*> SLEW = FAST;
|
||||
NET tft_lcd_g<*> DRIVE = 8;
|
||||
|
||||
NET tft_lcd_hsync LOC = C10;
|
||||
NET tft_lcd_hsync SLEW = FAST;
|
||||
NET tft_lcd_hsync DRIVE = 8;
|
||||
|
||||
NET tft_lcd_r<0> LOC = N25; #VGA_R2
|
||||
NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
|
||||
NET tft_lcd_r<1> LOC = C2; #VGA_R3
|
||||
NET tft_lcd_r<2> LOC = G7; #VGA_R4
|
||||
NET tft_lcd_r<3> LOC = F7; #VGA_R5
|
||||
NET tft_lcd_r<4> LOC = E5; #VGA_R6
|
||||
NET tft_lcd_r<5> LOC = E6; #VGA_R7
|
||||
NET tft_lcd_r<*> SLEW = FAST;
|
||||
NET tft_lcd_r<*> DRIVE = 8;
|
||||
|
||||
NET tft_lcd_vsync LOC = A8;
|
||||
NET tft_lcd_vsync SLEW = FAST;
|
||||
NET tft_lcd_vsync DRIVE = 8;
|
||||
|
||||
TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
|
||||
TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET plb_error LOC = L24;
|
||||
NET plb_error IOSTANDARD = LVCMOS33;
|
||||
NET plb_error TIG;
|
||||
NET opb_error LOC = V6;
|
||||
NET opb_error IOSTANDARD = LVCMOS33;
|
||||
NET opb_error TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for Ethernet
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET phy_col LOC = E3;
|
||||
NET phy_crs LOC = D5;
|
||||
NET phy_dv LOC = A9;
|
||||
NET phy_rx_clk LOC = B15;
|
||||
NET phy_rx_data<3> LOC = C4;
|
||||
NET phy_rx_data<2> LOC = D4;
|
||||
NET phy_rx_data<1> LOC = E1;
|
||||
NET phy_rx_data<0> LOC = F1;
|
||||
|
||||
NET phy_rx_er LOC = B9;
|
||||
NET phy_tx_clk LOC = C15;
|
||||
NET phy_mii_clk LOC = D1;
|
||||
NET phy_mii_int_n LOC = H4;
|
||||
NET phy_rst_n LOC = D10;
|
||||
NET phy_tx_data<3> LOC = G1;
|
||||
NET phy_tx_data<2> LOC = H3;
|
||||
NET phy_tx_data<1> LOC = H2;
|
||||
NET phy_tx_data<0> LOC = H1;
|
||||
NET phy_tx_en LOC = F4;
|
||||
NET phy_tx_er LOC = F3;
|
||||
NET phy_mii_data LOC = G4;
|
||||
|
||||
NET phy_mii_int_n PULLUP;
|
||||
|
||||
NET phy_mii_int_n TIG;
|
||||
NET phy_rst_n TIG;
|
||||
|
||||
# Timing Constraints (these are recommended in documentation and
|
||||
# are unaltered except for the TIG)
|
||||
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
|
||||
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
|
||||
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
|
||||
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
|
||||
|
||||
NET "phy_tx_clk" MAXSKEW= 1.0 ns;
|
||||
NET "phy_rx_clk" MAXSKEW= 1.0 ns;
|
||||
NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
|
||||
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
|
||||
|
||||
NET "phy_rx_data<3>" IOBDELAY=NONE;
|
||||
NET "phy_rx_data<2>" IOBDELAY=NONE;
|
||||
NET "phy_rx_data<1>" IOBDELAY=NONE;
|
||||
NET "phy_rx_data<0>" IOBDELAY=NONE;
|
||||
NET "phy_dv" IOBDELAY=NONE;
|
||||
NET "phy_rx_er" IOBDELAY=NONE;
|
||||
NET "phy_crs" IOBDELAY=NONE;
|
||||
NET "phy_col" IOBDELAY=NONE;
|
||||
|
||||
# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
|
||||
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
|
||||
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
|
||||
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
|
||||
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
|
||||
INST "opb_ethernet_0/opb_ethernet_0/DVD_FF" IOB=FALSE;
|
||||
INST "opb_ethernet_0/opb_ethernet_0/RER_FF" IOB=FALSE;
|
||||
|
||||
# Timing ignores (to specify unconstrained paths)
|
||||
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
|
||||
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
|
||||
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
|
||||
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for SRAM/FLASH
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sram_clk LOC = AF7;
|
||||
NET sram_clk_fb LOC = AD17;
|
||||
NET flash_a23 LOC = T21;
|
||||
NET sram_flash_addr<22> LOC = U20;
|
||||
NET sram_flash_addr<21> LOC = T19;
|
||||
NET sram_flash_addr<20> LOC = AC5;
|
||||
NET sram_flash_addr<19> LOC = AB5;
|
||||
NET sram_flash_addr<18> LOC = AC4;
|
||||
NET sram_flash_addr<17> LOC = AB4;
|
||||
|
||||
NET sram_flash_addr<16> LOC = AB3;
|
||||
NET sram_flash_addr<15> LOC = AA4;
|
||||
NET sram_flash_addr<14> LOC = AA3;
|
||||
NET sram_flash_addr<13> LOC = W5;
|
||||
NET sram_flash_addr<12> LOC = W6;
|
||||
NET sram_flash_addr<11> LOC = W3;
|
||||
NET sram_flash_addr<10> LOC = AF3;
|
||||
NET sram_flash_addr<9> LOC = AE3;
|
||||
NET sram_flash_addr<8> LOC = AD2;
|
||||
NET sram_flash_addr<7> LOC = AD1;
|
||||
NET sram_flash_addr<6> LOC = AC2;
|
||||
NET sram_flash_addr<5> LOC = AC1;
|
||||
NET sram_flash_addr<4> LOC = AB2;
|
||||
NET sram_flash_addr<3> LOC = AB1;
|
||||
NET sram_flash_addr<2> LOC = AA1;
|
||||
NET sram_flash_addr<1> LOC = Y2;
|
||||
NET sram_flash_addr<0> LOC = Y1;
|
||||
NET sram_flash_data<31> LOC = F14;
|
||||
NET sram_flash_data<30> LOC = F13;
|
||||
NET sram_flash_data<29> LOC = F12;
|
||||
NET sram_flash_data<28> LOC = F11;
|
||||
NET sram_flash_data<27> LOC = F16;
|
||||
NET sram_flash_data<26> LOC = F15;
|
||||
NET sram_flash_data<25> LOC = D14;
|
||||
NET sram_flash_data<24> LOC = D13;
|
||||
NET sram_flash_data<23> LOC = D15;
|
||||
NET sram_flash_data<22> LOC = E14;
|
||||
NET sram_flash_data<21> LOC = C11;
|
||||
NET sram_flash_data<20> LOC = D11;
|
||||
NET sram_flash_data<19> LOC = D16;
|
||||
NET sram_flash_data<18> LOC = C16;
|
||||
NET sram_flash_data<17> LOC = E13;
|
||||
NET sram_flash_data<16> LOC = D12;
|
||||
NET sram_flash_data<15> LOC = AA14;
|
||||
NET sram_flash_data<14> LOC = AB14;
|
||||
NET sram_flash_data<13> LOC = AC12;
|
||||
NET sram_flash_data<12> LOC = AC11;
|
||||
NET sram_flash_data<11> LOC = AA16;
|
||||
NET sram_flash_data<10> LOC = AA15;
|
||||
NET sram_flash_data<9> LOC = AB13;
|
||||
NET sram_flash_data<8> LOC = AA13;
|
||||
NET sram_flash_data<7> LOC = AC14;
|
||||
NET sram_flash_data<6> LOC = AD14;
|
||||
NET sram_flash_data<5> LOC = AA12;
|
||||
NET sram_flash_data<4> LOC = AA11;
|
||||
NET sram_flash_data<3> LOC = AC16;
|
||||
NET sram_flash_data<2> LOC = AC15;
|
||||
NET sram_flash_data<1> LOC = AC13;
|
||||
NET sram_flash_data<0> LOC = AD13;
|
||||
NET sram_cen LOC = V7;
|
||||
NET sram_flash_oe_n LOC = AC6;
|
||||
NET sram_flash_we_n LOC = AB6;
|
||||
NET sram_bw<3> LOC = Y3; #Y4;
|
||||
NET sram_bw<2> LOC = Y4; #Y3;
|
||||
NET sram_bw<1> LOC = Y5; #Y6;
|
||||
NET sram_bw<0> LOC = Y6; #Y5;
|
||||
NET flash_ce LOC = W7;
|
||||
NET sram_adv_ld_n LOC = W4;
|
||||
NET sram_mode LOC = V26;
|
||||
|
||||
NET sram_clk IOSTANDARD = LVCMOS33;
|
||||
NET sram_clk DRIVE = 16;
|
||||
NET sram_clk SLEW = FAST;
|
||||
NET sram_clk_fb IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET flash_a23 IOSTANDARD = LVDCI_33;
|
||||
NET flash_a23 SLEW = FAST;
|
||||
NET flash_a23 DRIVE = 8;
|
||||
|
||||
NET sram_mode IOSTANDARD = LVDCI_33;
|
||||
NET sram_mode SLEW = FAST;
|
||||
NET sram_mode DRIVE = 8;
|
||||
|
||||
NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
|
||||
NET sram_flash_addr<*> SLEW = FAST;
|
||||
NET sram_flash_addr<*> DRIVE = 8;
|
||||
|
||||
NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
|
||||
NET sram_flash_data<*> DRIVE = 12;
|
||||
NET sram_flash_data<*> SLEW = FAST;
|
||||
NET sram_flash_data<*> PULLDOWN;
|
||||
|
||||
NET sram_flash_oe_n IOSTANDARD = LVDCI_33;
|
||||
NET sram_flash_oe_n SLEW = FAST;
|
||||
NET sram_flash_oe_n DRIVE = 8;
|
||||
|
||||
NET sram_flash_we_n IOSTANDARD = LVDCI_33;
|
||||
NET sram_flash_we_n SLEW = FAST;
|
||||
NET sram_flash_we_n DRIVE = 8;
|
||||
|
||||
NET sram_bw<*> IOSTANDARD = LVDCI_33;
|
||||
NET sram_bw<*> SLEW = FAST;
|
||||
NET sram_bw<*> DRIVE = 8;
|
||||
|
||||
NET flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET flash_ce SLEW = FAST;
|
||||
NET flash_ce DRIVE = 8;
|
||||
|
||||
NET sram_cen IOSTANDARD = LVDCI_33;
|
||||
NET sram_cen SLEW = FAST;
|
||||
NET sram_cen DRIVE = 8;
|
||||
|
||||
NET sram_adv_ld_n IOSTANDARD = LVDCI_33;
|
||||
NET sram_adv_ld_n SLEW = FAST;
|
||||
NET sram_adv_ld_n DRIVE = 8;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for Expansion Header GPIO
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
|
||||
NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
|
||||
NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
|
||||
NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
|
||||
NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44
|
||||
NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48
|
||||
NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
|
||||
NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
|
||||
NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46
|
||||
NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56
|
||||
NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54
|
||||
NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
|
||||
NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
|
||||
NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
|
||||
NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
|
||||
NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
|
||||
NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
|
||||
NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
|
||||
NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
|
||||
NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
|
||||
NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
|
||||
NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40
|
||||
NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38
|
||||
NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50
|
||||
NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12
|
||||
NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26
|
||||
NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32
|
||||
NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52
|
||||
NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2
|
||||
NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36
|
||||
NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42
|
||||
NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28
|
||||
NET gpio_exp_hdr1<*> TIG;
|
||||
NET gpio_exp_hdr1<*> PULLDOWN;
|
||||
|
||||
NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
|
||||
NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
|
||||
NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
|
||||
NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
|
||||
NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
|
||||
NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
|
||||
NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
|
||||
NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
|
||||
NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
|
||||
NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
|
||||
NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
|
||||
NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
|
||||
NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
|
||||
NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
|
||||
NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
|
||||
NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
|
||||
NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
|
||||
NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
|
||||
NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56
|
||||
NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
|
||||
NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
|
||||
NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
|
||||
NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8
|
||||
NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6
|
||||
NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12
|
||||
NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10
|
||||
NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20
|
||||
NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18
|
||||
NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28
|
||||
NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26
|
||||
NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4
|
||||
NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2
|
||||
NET gpio_exp_hdr2<*> TIG;
|
||||
NET gpio_exp_hdr2<*> PULLDOWN;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for Character LCD GPIO
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET gpio_char_lcd<6> LOC = AE13; # LCD_E
|
||||
NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
|
||||
NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
|
||||
NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
|
||||
NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
|
||||
NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
|
||||
NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
|
||||
NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
|
||||
NET gpio_char_lcd<*> TIG;
|
||||
NET gpio_char_lcd<*> PULLDOWN;
|
||||
@@ -1,23 +0,0 @@
|
||||
FOLDER ?= lib
|
||||
|
||||
TARGETS = $(shell find $(FOLDER)/ -name "*.make")
|
||||
INSTR := $(foreach number,$(TARGETS),make -C $(shell dirname $(number)) -f $(shell basename $(number)) $(MAKECMDGOALS) &&) true
|
||||
|
||||
all:
|
||||
$(INSTR)
|
||||
|
||||
elaborate:
|
||||
$(INSTR)
|
||||
|
||||
run:
|
||||
$(INSTR)
|
||||
|
||||
run_wave:
|
||||
$(INSTR)
|
||||
|
||||
clean:
|
||||
$(INSTR)
|
||||
|
||||
mrproper:
|
||||
$(INSTR)
|
||||
|
||||
Binary file not shown.
@@ -1,15 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/core/ram_2c_2r_2w.vhd"
|
||||
vcom -explicit -93 "../src/core/j1.vhd"
|
||||
vcom -explicit -93 "../src/tb_j1.vhd"
|
||||
|
||||
vmap work
|
||||
|
||||
vsim -t 1ps -lib work tb_j1
|
||||
do {tb_j1.wave.do}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1us
|
||||
@@ -1,58 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_j1/sys_clk_i
|
||||
add wave -noupdate -format Logic /tb_j1/sys_rst_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_din
|
||||
add wave -noupdate -format Logic /tb_j1/io_rd
|
||||
add wave -noupdate -format Logic /tb_j1/io_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_dout
|
||||
add wave -noupdate -format Logic /tb_j1/data_we
|
||||
add wave -noupdate -format Logic /tb_j1/data_en
|
||||
add wave -noupdate -divider {J1 internals}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/insn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/immediate
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/ramrd
|
||||
add wave -noupdate -format Literal /tb_j1/uut/dsp
|
||||
add wave -noupdate -format Literal /tb_j1/uut/dsp2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st02
|
||||
add wave -noupdate -format Logic /tb_j1/uut/dstkw2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc2
|
||||
add wave -noupdate -format Literal /tb_j1/uut/rsp
|
||||
add wave -noupdate -format Literal /tb_j1/uut/rsp2
|
||||
add wave -noupdate -format Logic /tb_j1/uut/rstkw2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstkd2
|
||||
add wave -noupdate -format Logic /tb_j1/uut/ramwe2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc_plus_1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/dstack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rst0
|
||||
add wave -noupdate -format Literal /tb_j1/uut/st0sel
|
||||
add wave -noupdate -format Logic /tb_j1/uut/is_alu
|
||||
add wave -noupdate -format Logic /tb_j1/uut/is_lit
|
||||
add wave -noupdate -format Literal /tb_j1/uut/dd
|
||||
add wave -noupdate -format Literal /tb_j1/uut/rd
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1600185 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1050 ns}
|
||||
@@ -1,187 +0,0 @@
|
||||
module j1(
|
||||
input sys_clk_i, input sys_rst_i, input [15:0] io_din,
|
||||
output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
|
||||
|
||||
wire [15:0] insn;
|
||||
wire [15:0] immediate = { 1'b0, insn[14:0] };
|
||||
|
||||
wire [15:0] ramrd;
|
||||
|
||||
reg [4:0] dsp; // Data stack pointer
|
||||
reg [4:0] _dsp;
|
||||
reg [15:0] st0; // Return stack pointer
|
||||
reg [15:0] _st0;
|
||||
wire _dstkW; // D stack write
|
||||
|
||||
reg [12:0] pc;
|
||||
reg [12:0] _pc;
|
||||
reg [4:0] rsp;
|
||||
reg [4:0] _rsp;
|
||||
reg _rstkW; // R stack write
|
||||
reg [15:0] _rstkD;
|
||||
wire _ramWE; // RAM write enable
|
||||
|
||||
wire [15:0] pc_plus_1;
|
||||
assign pc_plus_1 = pc + 1;
|
||||
|
||||
// The D and R stacks
|
||||
reg [15:0] dstack[0:31];
|
||||
reg [15:0] rstack[0:31];
|
||||
always @(posedge sys_clk_i)
|
||||
begin
|
||||
if (_dstkW)
|
||||
dstack[_dsp] = st0;
|
||||
if (_rstkW)
|
||||
rstack[_rsp] = _rstkD;
|
||||
end
|
||||
wire [15:0] st1 = dstack[dsp];
|
||||
wire [15:0] rst0 = rstack[rsp];
|
||||
|
||||
// st0sel is the ALU operation. For branch and call the operation
|
||||
// is T, for 0branch it is N. For ALU ops it is loaded from the instruction
|
||||
// field.
|
||||
reg [3:0] st0sel;
|
||||
always @*
|
||||
begin
|
||||
case (insn[14:13])
|
||||
2'b00: st0sel = 0; // ubranch
|
||||
2'b10: st0sel = 0; // call
|
||||
2'b01: st0sel = 1; // 0branch
|
||||
2'b11: st0sel = insn[11:8]; // ALU
|
||||
default: st0sel = 4'bxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
`define RAMS 3
|
||||
|
||||
genvar i;
|
||||
|
||||
`define w (16 >> `RAMS)
|
||||
`define w1 (`w - 1)
|
||||
|
||||
generate
|
||||
for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram
|
||||
// RAMB16_S18_S18
|
||||
RAMB16_S2_S2
|
||||
ram(
|
||||
.DIA(0),
|
||||
// .DIPA(0),
|
||||
.DOA(insn[`w*i+`w1:`w*i]),
|
||||
.WEA(0),
|
||||
.ENA(1),
|
||||
.CLKA(sys_clk_i),
|
||||
.ADDRA({_pc}),
|
||||
|
||||
.DIB(st1[`w*i+`w1:`w*i]),
|
||||
// .DIPB(2'b0),
|
||||
.WEB(_ramWE & (_st0[15:14] == 0)),
|
||||
.ENB(|_st0[15:14] == 0),
|
||||
.CLKB(sys_clk_i),
|
||||
.ADDRB(_st0[15:1]),
|
||||
.DOB(ramrd[`w*i+`w1:`w*i]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Compute the new value of T.
|
||||
always @*
|
||||
begin
|
||||
if (insn[15])
|
||||
_st0 = immediate;
|
||||
else
|
||||
case (st0sel)
|
||||
4'b0000: _st0 = st0;
|
||||
4'b0001: _st0 = st1;
|
||||
4'b0010: _st0 = st0 + st1;
|
||||
4'b0011: _st0 = st0 & st1;
|
||||
4'b0100: _st0 = st0 | st1;
|
||||
4'b0101: _st0 = st0 ^ st1;
|
||||
4'b0110: _st0 = ~st0;
|
||||
4'b0111: _st0 = {16{(st1 == st0)}};
|
||||
4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
|
||||
4'b1001: _st0 = st1 >> st0[3:0];
|
||||
4'b1010: _st0 = st0 - 1;
|
||||
4'b1011: _st0 = rst0;
|
||||
4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
|
||||
4'b1101: _st0 = st1 << st0[3:0];
|
||||
4'b1110: _st0 = {rsp, 3'b000, dsp};
|
||||
4'b1111: _st0 = {16{(st1 < st0)}};
|
||||
default: _st0 = 16'hxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
wire is_alu = (insn[15:13] == 3'b011);
|
||||
wire is_lit = (insn[15]);
|
||||
|
||||
assign io_rd = (is_alu & (insn[11:8] == 4'hc));
|
||||
assign io_wr = _ramWE;
|
||||
assign io_addr = st0;
|
||||
assign io_dout = st1;
|
||||
|
||||
assign _ramWE = is_alu & insn[5];
|
||||
assign _dstkW = is_lit | (is_alu & insn[7]);
|
||||
|
||||
wire [1:0] dd = insn[1:0]; // D stack delta
|
||||
wire [1:0] rd = insn[3:2]; // R stack delta
|
||||
|
||||
always @*
|
||||
begin
|
||||
if (is_lit) begin // literal
|
||||
_dsp = dsp + 1;
|
||||
_rsp = rsp;
|
||||
_rstkW = 0;
|
||||
_rstkD = _pc;
|
||||
end else if (is_alu) begin
|
||||
_dsp = dsp + {dd[1], dd[1], dd[1], dd};
|
||||
_rsp = rsp + {rd[1], rd[1], rd[1], rd};
|
||||
_rstkW = insn[6];
|
||||
_rstkD = st0;
|
||||
end else begin // jump/call
|
||||
// predicated jump is like DROP
|
||||
if (insn[15:13] == 3'b001) begin
|
||||
_dsp = dsp - 1;
|
||||
end else begin
|
||||
_dsp = dsp;
|
||||
end
|
||||
if (insn[15:13] == 3'b010) begin // call
|
||||
_rsp = rsp + 1;
|
||||
_rstkW = 1;
|
||||
_rstkD = {pc_plus_1[14:0], 1'b0};
|
||||
end else begin
|
||||
_rsp = rsp;
|
||||
_rstkW = 0;
|
||||
_rstkD = _pc;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @*
|
||||
begin
|
||||
if (sys_rst_i)
|
||||
_pc = pc;
|
||||
else
|
||||
if ((insn[15:13] == 3'b000) |
|
||||
((insn[15:13] == 3'b001) & (|st0 == 0)) |
|
||||
(insn[15:13] == 3'b010))
|
||||
_pc = insn[12:0];
|
||||
else if (is_alu & insn[12])
|
||||
_pc = rst0[15:1];
|
||||
else
|
||||
_pc = pc_plus_1;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk_i)
|
||||
begin
|
||||
if (sys_rst_i) begin
|
||||
pc <= 0;
|
||||
dsp <= 0;
|
||||
st0 <= 0;
|
||||
rsp <= 0;
|
||||
end else begin
|
||||
dsp <= _dsp;
|
||||
pc <= _pc;
|
||||
st0 <= _st0;
|
||||
rsp <= _rsp;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // j1
|
||||
@@ -1,282 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
entity j1 is
|
||||
Generic
|
||||
(
|
||||
R_STACK_SIZE : natural := 32;
|
||||
D_STACK_SIZE : natural := 32
|
||||
|
||||
);
|
||||
Port
|
||||
(
|
||||
sys_clk_i : in std_logic;
|
||||
sys_rst_i : in std_logic;
|
||||
io_din : in unsigned(15 downto 0);
|
||||
io_rd : out std_logic;
|
||||
io_wr : out std_logic;
|
||||
io_addr : out unsigned(15 downto 0);
|
||||
io_dout : out unsigned(15 downto 0);
|
||||
inst_din : in unsigned(15 downto 0);
|
||||
inst_addr : out unsigned(12 downto 0);
|
||||
data_addr : out unsigned(12 downto 0);
|
||||
data_we : out std_logic;
|
||||
data_en : out std_logic;
|
||||
data_din : in unsigned(15 downto 0);
|
||||
data_dout : out unsigned(15 downto 0)
|
||||
|
||||
);
|
||||
end j1;
|
||||
|
||||
architecture behave of j1 is
|
||||
|
||||
signal insn : unsigned(15 downto 0);
|
||||
signal immediate : unsigned(15 downto 0);
|
||||
signal ramrd : unsigned(15 downto 0);
|
||||
|
||||
signal dsp : unsigned(4 downto 0); -- Data stack pointer (register)
|
||||
signal dsp2 : unsigned(4 downto 0); -- register
|
||||
signal st0 : unsigned(15 downto 0); -- Return stack pointer (register)
|
||||
signal st02 : unsigned(15 downto 0); -- register
|
||||
|
||||
signal dstkW2 : std_logic; -- D stack write
|
||||
|
||||
signal pc : unsigned(12 downto 0); -- register
|
||||
signal pc2 : unsigned(12 downto 0); -- register
|
||||
signal rsp : unsigned(4 downto 0); -- register
|
||||
signal rsp2 : unsigned(4 downto 0); -- register
|
||||
|
||||
signal rstkW2 : std_logic; -- register
|
||||
signal rstkD2 : unsigned(15 downto 0); -- register
|
||||
signal ramWE2 : std_logic; -- RAM write enable
|
||||
|
||||
signal pc_plus_1 : unsigned(15 downto 0);
|
||||
|
||||
type stack_t is array (integer range <>) of unsigned(15 downto 0);
|
||||
|
||||
signal dstack : stack_t(0 to D_STACK_SIZE-1); -- register
|
||||
signal rstack : stack_t(0 to R_STACK_SIZE-1); -- register
|
||||
|
||||
signal st1 : unsigned(15 downto 0);
|
||||
signal rst0 : unsigned(15 downto 0);
|
||||
|
||||
signal st0sel : unsigned(3 downto 0);
|
||||
|
||||
signal is_alu : BOOLEAN;
|
||||
signal is_lit : BOOLEAN;
|
||||
|
||||
signal dd : unsigned(1 downto 0); -- D stack delta
|
||||
signal rd : unsigned(1 downto 0); -- R stack delta
|
||||
|
||||
signal stack_ram_en : std_logic; -- helper for RAM R/W
|
||||
signal stack_ram_we : std_logic; -- helper for RAM R/W
|
||||
|
||||
begin
|
||||
|
||||
-- LINE 25:
|
||||
pc_plus_1 <= ("000" & pc) + 1;
|
||||
|
||||
-- LINE 37:
|
||||
st1 <= dstack(to_integer(dsp));
|
||||
rst0 <= rstack(to_integer(rsp));
|
||||
immediate <= '1' & insn(14 downto 0);
|
||||
|
||||
-- LINE 112:
|
||||
is_alu <= (insn(15 downto 13) = "011");
|
||||
is_lit <= (insn(15) = '1');
|
||||
|
||||
|
||||
-- LINE 115:
|
||||
io_rd <= '1' when (is_alu and (insn(11 downto 8) = X"C")) else '0';
|
||||
io_wr <= ramWE2;
|
||||
io_addr <= st0;
|
||||
io_dout <= st1;
|
||||
ramWE2 <= '1' when (is_alu and (insn(5) = '1')) else '0';
|
||||
dstkW2 <= '1' when (is_lit or (is_alu and insn(7) = '1')) else '0';
|
||||
dd <= insn(1 downto 0);
|
||||
rd <= insn(3 downto 2);
|
||||
|
||||
|
||||
-- LINE 27:
|
||||
-- The D and R stacks
|
||||
proc_d_and_r_stack:
|
||||
process(sys_clk_i)
|
||||
begin
|
||||
if rising_edge(sys_clk_i) then
|
||||
if dstkW2 = '1' then
|
||||
dstack(to_integer(dsp2)) <= st0;
|
||||
end if;
|
||||
if rstkW2 = '1' then
|
||||
rstack(to_integer(rsp2)) <= rstkD2;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- LINE 40:
|
||||
-- st0sel is the ALU operation. For branch and call the operation
|
||||
-- is T, for 0branch it is N. For ALU ops it is loaded from the instruction
|
||||
-- field.
|
||||
|
||||
proc_aluop_sel:
|
||||
process(insn)
|
||||
begin
|
||||
|
||||
|
||||
case insn(14 downto 13) is
|
||||
|
||||
when "00" => st0sel <= "0000";
|
||||
when "10" => st0sel <= "0000";
|
||||
when "01" => st0sel <= "0001";
|
||||
when "11" => st0sel <= insn(11 downto 8);
|
||||
when others => st0sel <= "XXXX";
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
|
||||
-- LINE 55:
|
||||
-- define RAMS outside this module
|
||||
insn <= inst_din;
|
||||
inst_addr <= pc2(12 downto 0);
|
||||
data_en <= not (st02(15) or st02(14));
|
||||
data_we <= ramWE2 and not (st02(15) or st02(14));
|
||||
ramrd <= data_din;
|
||||
data_dout <= st1;
|
||||
data_addr <= st02(13 downto 1);
|
||||
|
||||
|
||||
-- LINE 85:
|
||||
-- Compute the new value of T.
|
||||
proc_alu:
|
||||
process(insn, immediate, st0sel, st0, st1, rst0, rsp, dsp)
|
||||
begin
|
||||
|
||||
if insn(15) = '1' then
|
||||
st02 <= immediate;
|
||||
else
|
||||
case st0sel is
|
||||
|
||||
when "0000" => st02 <= st0;
|
||||
when "0001" => st02 <= st1;
|
||||
when "0010" => st02 <= st0 + st1;
|
||||
when "0011" => st02 <= st0 and st1;
|
||||
when "0100" => st02 <= st0 or st1;
|
||||
when "0101" => st02 <= st0 xor st1;
|
||||
when "0110" => st02 <= not st0;
|
||||
when "0111" =>
|
||||
if st1 = st0 then
|
||||
st02 <= X"FFFF";
|
||||
else
|
||||
st02 <= X"0000";
|
||||
end if;
|
||||
|
||||
when "1000" =>
|
||||
if signed(st1) < signed(st0) then
|
||||
st02 <= X"FFFF";
|
||||
else
|
||||
st02 <= X"0000";
|
||||
end if;
|
||||
|
||||
when "1001" => st02 <= st1 srl to_integer(st0(3 downto 0));
|
||||
when "1010" => st02 <= st0 - 1;
|
||||
when "1011" => st02 <= rst0;
|
||||
when "1100" =>
|
||||
if st0(15) = '1' or st0(14) = '1' then -- LINE 104: ????
|
||||
st02 <= io_din;
|
||||
else
|
||||
st02 <= ramrd;
|
||||
end if;
|
||||
|
||||
when "1101" => st02 <= st1 sll to_integer(st0(3 downto 0));
|
||||
when "1110" => st02 <= "000" & rsp & "000" & dsp; -- LINE 106: ????
|
||||
when "1111" =>
|
||||
if st1 < st0 then
|
||||
st02 <= X"FFFF";
|
||||
else
|
||||
st02 <= X"0000";
|
||||
end if;
|
||||
when others => st02 <= "XXXXXXXXXXXXXXXX";
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- LINE 126:
|
||||
proc_stack_ctrl:
|
||||
process(is_lit, is_alu, pc2, dd, rd, insn, st0, pc_plus_1, rsp, dsp)
|
||||
begin
|
||||
if is_lit then -- literal
|
||||
dsp2 <= dsp + 1;
|
||||
rsp2 <= rsp;
|
||||
rstkW2 <= '0';
|
||||
rstkD2 <= "000" & pc2;
|
||||
elsif is_alu then
|
||||
dsp2 <= dsp + (dd(1) & dd(1) & dd(1) & dd);
|
||||
rsp2 <= rsp + (rd(1) & rd(1) & rd(1) & rd);
|
||||
rstkW2 <= insn(6);
|
||||
rstkD2 <= st0;
|
||||
else -- jump/call
|
||||
-- predicated jump is like DROP
|
||||
if insn(15 downto 13) = "001" then
|
||||
dsp2 <= dsp - 1;
|
||||
else
|
||||
dsp2 <= dsp; -- *default
|
||||
end if;
|
||||
if insn(15 downto 13) = "010" then -- call
|
||||
rsp2 <= rsp + 1;
|
||||
rstkW2 <= '1';
|
||||
rstkD2 <= pc_plus_1(14 downto 0) & '0';
|
||||
else
|
||||
rsp2 <= rsp; -- *default
|
||||
rstkW2 <= '0'; -- *default
|
||||
rstkD2 <= "000" & pc2; -- *default
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- LINE 157:
|
||||
proc_pc:
|
||||
process(sys_rst_i, is_alu, insn, pc, st0, rst0, pc_plus_1)
|
||||
begin
|
||||
|
||||
if sys_rst_i = '1' then
|
||||
pc2 <= pc;
|
||||
else
|
||||
if ((insn(15 downto 13) = "000")
|
||||
or ((insn(15 downto 13) = "001")
|
||||
and (st0 = X"0000"))
|
||||
or (insn(15 downto 13) = "010")) then
|
||||
pc2 <= insn(12 downto 0);
|
||||
elsif is_alu and (insn(12) = '1') then -- return
|
||||
pc2 <= rst0(13 downto 1); -- LINE 167: ????
|
||||
else
|
||||
pc2 <= pc_plus_1(12 downto 0); -- LINE 169: truncation ????
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- LINE 172:
|
||||
proc_next:
|
||||
process(sys_clk_i)
|
||||
begin
|
||||
|
||||
if rising_edge(sys_clk_i) then
|
||||
if sys_rst_i = '1' then
|
||||
pc <= (others => '0');
|
||||
dsp <= (others => '0');
|
||||
st0 <= (others => '0');
|
||||
rsp <= (others => '0');
|
||||
else
|
||||
dsp <= dsp2;
|
||||
pc <= pc2;
|
||||
st0 <= st02;
|
||||
rsp <= rsp2;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behave;
|
||||
@@ -1,84 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: Generic RAM. Infers BlockRAM for Xilinx
|
||||
-- This file: On-chip RAM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity ram_2c_2r_2w is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end ram_2c_2r_2w;
|
||||
|
||||
architecture Behavioral of ram_2c_2r_2w is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,150 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for embedded cpu with rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
|
||||
ENTITY tb_j1 IS
|
||||
END tb_j1;
|
||||
|
||||
ARCHITECTURE behavior OF tb_j1 IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
-- Inputs
|
||||
signal sys_clk_i : std_logic := '0';
|
||||
signal sys_rst_i : std_logic := '1';
|
||||
signal io_din : unsigned(15 downto 0) := (others => '0');
|
||||
signal inst_din : unsigned(15 downto 0) := (others => '0');
|
||||
signal data_din : unsigned(15 downto 0) := (others => '0');
|
||||
|
||||
-- Outputs
|
||||
signal io_rd : std_logic;
|
||||
signal io_wr : std_logic;
|
||||
signal io_addr : unsigned(15 downto 0);
|
||||
signal io_dout : unsigned(15 downto 0);
|
||||
signal data_dout : unsigned(15 downto 0);
|
||||
signal inst_addr : unsigned(12 downto 0);
|
||||
signal data_addr : unsigned(12 downto 0);
|
||||
signal data_we : std_logic;
|
||||
signal data_en : std_logic;
|
||||
|
||||
type rom_t is array (integer range <>) of unsigned(15 downto 0);
|
||||
|
||||
signal rom : rom_t(0 to 15) :=
|
||||
(
|
||||
X"8123", -- 0000
|
||||
X"0002", -- 0001
|
||||
X"0005", -- 0002
|
||||
X"8456", -- 0003
|
||||
X"4008", -- 0004
|
||||
X"0003", -- 0005
|
||||
X"0000", -- 0006
|
||||
X"0000", -- 0007
|
||||
X"8456", -- 0008
|
||||
X"8451", -- 0009
|
||||
X"7000", -- 000A
|
||||
X"0000", -- 000B
|
||||
X"0000", -- 000C
|
||||
X"0000", -- 000D
|
||||
X"0000", -- 000E
|
||||
X"0000" -- 000F
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instruction rom
|
||||
process(sys_clk_i)
|
||||
begin
|
||||
if rising_edge(sys_clk_i) then
|
||||
inst_din <= rom(to_integer(inst_addr(3 downto 0)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
uut: entity work.j1
|
||||
PORT MAP
|
||||
(
|
||||
sys_clk_i => sys_clk_i,
|
||||
sys_rst_i => sys_rst_i,
|
||||
io_din => io_din,
|
||||
io_rd => io_rd,
|
||||
io_wr => io_wr,
|
||||
io_addr => io_addr,
|
||||
inst_din => inst_din,
|
||||
inst_addr => inst_addr,
|
||||
data_addr => data_addr,
|
||||
data_we => data_we,
|
||||
data_en => data_en,
|
||||
data_din => data_din,
|
||||
data_dout => data_dout
|
||||
);
|
||||
|
||||
inst_ram: entity work.ram_2c_2r_2w
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 13,
|
||||
data_width => 16
|
||||
)
|
||||
PORT MAP(
|
||||
clka => sys_clk_i,
|
||||
clkb => sys_clk_i,
|
||||
en_a => '1',
|
||||
en_b => data_en,
|
||||
we_a => '0',
|
||||
we_b => data_we,
|
||||
addr_a => (others => '0'), --inst_addr
|
||||
addr_b => data_addr,
|
||||
din_a => (others => '0'),
|
||||
din_b => data_dout,
|
||||
dout_a => open, -- inst_din
|
||||
dout_b => data_din
|
||||
);
|
||||
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_i <= not sys_clk_i;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
sys_rst_i <= '0';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
|
||||
wait for 1000*CLK_PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -1,17 +0,0 @@
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
TOOL_PATH := $(VHDL_HOME)/tools/jcpu
|
||||
|
||||
.PHONY: install uninstall
|
||||
all: install
|
||||
|
||||
$(TOOL_PATH):
|
||||
mkdir -p $@
|
||||
|
||||
install: $(TOOL_PATH)
|
||||
cp -r tools/* $(TOOL_PATH)
|
||||
chmod +x $(TOOL_PATH)/*.rb
|
||||
|
||||
uninstall:
|
||||
rm -rf $(TOOL_PATH)
|
||||
|
||||
|
||||
@@ -1,56 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; PROJECT "dctest"
|
||||
; -------------------------------------------------
|
||||
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
xmem
|
||||
org 4
|
||||
konst: dc 0x01, 0x12,"A"
|
||||
gap1: db 16
|
||||
mesg: dc "Hallo", 13,0x0A, 0
|
||||
name: dc "Jens",0
|
||||
msg1: dc "Welcome to JASM CPU",0
|
||||
msg2: dc "Ready",0
|
||||
msg3: dc "Testing",0
|
||||
msg4: dc "Passed",0
|
||||
msg5: dc "Error",0
|
||||
crlf: dc 0x0D, 0x0A
|
||||
|
||||
org 0x00
|
||||
shit: db 4
|
||||
|
||||
cmem 0
|
||||
org 8
|
||||
cram1: db 16
|
||||
cram2: db 6
|
||||
cram3: db 4
|
||||
|
||||
cmem 1
|
||||
cram4: db 8
|
||||
cram5: db 8
|
||||
org 0x20
|
||||
cram6: db 8
|
||||
cram7: db 4
|
||||
|
||||
reg_revision: equ 0x00
|
||||
reg_testid: equ 0x01
|
||||
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
int_vec: jmp isr
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x010
|
||||
|
||||
start: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
isr: reti
|
||||
|
||||
@@ -1,212 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from dctest.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x010
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
|
||||
|
||||
# 0x001: JMP 0x011
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
|
||||
|
||||
# 0x002:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
|
||||
|
||||
# 0x003:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
|
||||
|
||||
# 0x004:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
|
||||
|
||||
# 0x005:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
|
||||
|
||||
# 0x006:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
|
||||
|
||||
# 0x007:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
|
||||
|
||||
# 0x008:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
|
||||
|
||||
# 0x009:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
|
||||
|
||||
# 0x00A:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
|
||||
|
||||
# 0x00B:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
|
||||
|
||||
# 0x00C:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
|
||||
|
||||
# 0x00D:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
|
||||
|
||||
# 0x00E:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
|
||||
|
||||
# 0x00F:
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
|
||||
|
||||
# 0x010: JMP 0x010
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
|
||||
|
||||
# 0x011: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
|
||||
|
||||
# Assembled from dctest.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,74 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
crlf: dc 13, 10, 0
|
||||
msg_txt1: dc "J-CPU V1.", 0
|
||||
msg_txt2: dc "Ready.", 13, 10, 0
|
||||
msg_txt3: dc "Mimi ist eine liebe Katze !!!", 13, 10, 0
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
; nop
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: xin R0, (cpu_status)
|
||||
call bin2hex
|
||||
|
||||
call uart_putchar
|
||||
mov R0, R1
|
||||
call uart_putchar
|
||||
mov R1, crlf
|
||||
call uart_puts
|
||||
|
||||
loop:
|
||||
; Print line 0
|
||||
mov R1, msg_txt1
|
||||
call uart_puts
|
||||
cin R0, (cpu_revision)
|
||||
add R0, 0x30
|
||||
call uart_putchar
|
||||
mov R1, crlf
|
||||
call uart_puts
|
||||
|
||||
; Print line 1
|
||||
mov R1, msg_txt2
|
||||
call uart_puts
|
||||
|
||||
; Print line 3
|
||||
mov R1, msg_txt3
|
||||
call uart_puts
|
||||
|
||||
mov R15, 160
|
||||
fill_lp: tst R15
|
||||
jz ex_fill
|
||||
dec R15
|
||||
mov R1, 48
|
||||
ct_loop: cmp R1, 58
|
||||
jeq ex_ct
|
||||
mov R0, R1
|
||||
inc R1
|
||||
call uart_putchar
|
||||
jmp ct_loop
|
||||
ex_ct: jmp fill_lp
|
||||
ex_fill: mov R1, crlf
|
||||
call uart_puts
|
||||
jmp loop
|
||||
|
||||
; -------------------------------------------------
|
||||
include "./xregs.inc.jsm"
|
||||
include "../../../../tools/jcpu/lib/cregs.inc.jsm"
|
||||
include "../../../../tools/jcpu/lib/utils.inc.jsm"
|
||||
include "../../../../tools/jcpu/lib/uart.inc.jsm"
|
||||
include "../../../../tools/jcpu/lib/delays.inc.jsm"
|
||||
|
||||
|
||||
@@ -1,502 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from hallo_welt_uart.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: XIN R00, (0x02)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00228020"
|
||||
|
||||
# 0x003: CALL 0x029
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B029"
|
||||
|
||||
# 0x004: CALL 0x039
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0043B039"
|
||||
|
||||
# 0x005: MOV R00, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00502010"
|
||||
|
||||
# 0x006: CALL 0x039
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063B039"
|
||||
|
||||
# 0x007: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00703001"
|
||||
|
||||
# 0x008: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B030"
|
||||
|
||||
# 0x009: MOV R01, 0x03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903031"
|
||||
|
||||
# 0x00A: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3B030"
|
||||
|
||||
# 0x00B: CIN R00, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B29000"
|
||||
|
||||
# 0x00C: ADD R00, 0x30
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C11300"
|
||||
|
||||
# 0x00D: CALL 0x039
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D3B039"
|
||||
|
||||
# 0x00E: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E03001"
|
||||
|
||||
# 0x00F: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F3B030"
|
||||
|
||||
# 0x010: MOV R01, 0x0D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "010030D1"
|
||||
|
||||
# 0x011: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113B030"
|
||||
|
||||
# 0x012: MOV R01, 0x16
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01203161"
|
||||
|
||||
# 0x013: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B030"
|
||||
|
||||
# 0x014: MOV R15, 0xA0
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403A0F"
|
||||
|
||||
# 0x015: TST R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0150F00F"
|
||||
|
||||
# 0x016: JZ 0x020
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01631020"
|
||||
|
||||
# 0x017: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0171501F"
|
||||
|
||||
# 0x018: MOV R01, 0x30
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01803301"
|
||||
|
||||
# 0x019: CMP R01, 0x3A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0190F3A1"
|
||||
|
||||
# 0x01A: JEQ 0x01F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3901F"
|
||||
|
||||
# 0x01B: MOV R00, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B02010"
|
||||
|
||||
# 0x01C: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C11011"
|
||||
|
||||
# 0x01D: CALL 0x039
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D3B039"
|
||||
|
||||
# 0x01E: JMP 0x019
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E30019"
|
||||
|
||||
# 0x01F: JMP 0x015
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F30015"
|
||||
|
||||
# 0x020: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003001"
|
||||
|
||||
# 0x021: CALL 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0213B030"
|
||||
|
||||
# 0x022: JMP 0x009
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02230009"
|
||||
|
||||
# 0x023: AND R00, 0x0F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "023190F0"
|
||||
|
||||
# 0x024: CMP R00, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0240F0A0"
|
||||
|
||||
# 0x025: JLT 0x027
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02535027"
|
||||
|
||||
# 0x026: ADD R00, 0x07
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02611070"
|
||||
|
||||
# 0x027: ADD R00, 0x30
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02711300"
|
||||
|
||||
# 0x028: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283E000"
|
||||
|
||||
# 0x029: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0293C000"
|
||||
|
||||
# 0x02A: CALL 0x023
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A3B023"
|
||||
|
||||
# 0x02B: MOV R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B02001"
|
||||
|
||||
# 0x02C: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C3D000"
|
||||
|
||||
# 0x02D: SWAP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D2A000"
|
||||
|
||||
# 0x02E: CALL 0x023
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B023"
|
||||
|
||||
# 0x02F: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F3E000"
|
||||
|
||||
# 0x030: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0303C000"
|
||||
|
||||
# 0x031: MOVX R00, (R01)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03104010"
|
||||
|
||||
# 0x032: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03211011"
|
||||
|
||||
# 0x033: TST R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0330F000"
|
||||
|
||||
# 0x034: JZ 0x037
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03431037"
|
||||
|
||||
# 0x035: CALL 0x039
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0353B039"
|
||||
|
||||
# 0x036: JMP 0x031
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03630031"
|
||||
|
||||
# 0x037: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373D000"
|
||||
|
||||
# 0x038: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0383E000"
|
||||
|
||||
# 0x039: JMP 0x03A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0393003A"
|
||||
|
||||
# 0x03A: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A3C001"
|
||||
|
||||
# 0x03B: XIN R01, (0x06)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B28061"
|
||||
|
||||
# 0x03C: AND R01, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C19021"
|
||||
|
||||
# 0x03D: JNZ 0x03B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D3203B"
|
||||
|
||||
# 0x03E: XOUT (0x02), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E24020"
|
||||
|
||||
# 0x03F: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F3D001"
|
||||
|
||||
# 0x040: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0403E000"
|
||||
|
||||
# 0x041: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0413C001"
|
||||
|
||||
# 0x042: XIN R01, (0x06)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04228061"
|
||||
|
||||
# 0x043: AND R01, 0x10
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04319101"
|
||||
|
||||
# 0x044: JNZ 0x042
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04432042"
|
||||
|
||||
# 0x045: XIN R00, (0x02)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04528020"
|
||||
|
||||
# 0x046: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0463D001"
|
||||
|
||||
# 0x047: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0473E000"
|
||||
|
||||
# 0x048: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0483C00F"
|
||||
|
||||
# 0x049: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "049030AF"
|
||||
|
||||
# 0x04A: CALL 0x04F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A3B04F"
|
||||
|
||||
# 0x04B: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B1501F"
|
||||
|
||||
# 0x04C: JNZ 0x04A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C3204A"
|
||||
|
||||
# 0x04D: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D3D00F"
|
||||
|
||||
# 0x04E: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3E000"
|
||||
|
||||
# 0x04F: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F3C00F"
|
||||
|
||||
# 0x050: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "050030AF"
|
||||
|
||||
# 0x051: CALL 0x056
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0513B056"
|
||||
|
||||
# 0x052: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0521501F"
|
||||
|
||||
# 0x053: JNZ 0x051
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05332051"
|
||||
|
||||
# 0x054: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0543D00F"
|
||||
|
||||
# 0x055: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0553E000"
|
||||
|
||||
# 0x056: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563C00F"
|
||||
|
||||
# 0x057: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "057030AF"
|
||||
|
||||
# 0x058: CALL 0x05D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0583B05D"
|
||||
|
||||
# 0x059: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0591501F"
|
||||
|
||||
# 0x05A: JNZ 0x058
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A32058"
|
||||
|
||||
# 0x05B: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B3D00F"
|
||||
|
||||
# 0x05C: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C3E000"
|
||||
|
||||
# 0x05D: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D3C00F"
|
||||
|
||||
# 0x05E: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E030AF"
|
||||
|
||||
# 0x05F: CALL 0x064
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F3B064"
|
||||
|
||||
# 0x060: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0601501F"
|
||||
|
||||
# 0x061: JNZ 0x05F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0613205F"
|
||||
|
||||
# 0x062: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623D00F"
|
||||
|
||||
# 0x063: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0633E000"
|
||||
|
||||
# 0x064: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0643C00F"
|
||||
|
||||
# 0x065: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "065030AF"
|
||||
|
||||
# 0x066: CALL 0x06B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663B06B"
|
||||
|
||||
# 0x067: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0671501F"
|
||||
|
||||
# 0x068: JNZ 0x066
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06832066"
|
||||
|
||||
# 0x069: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0693D00F"
|
||||
|
||||
# 0x06A: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3E000"
|
||||
|
||||
# 0x06B: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B3C00F"
|
||||
|
||||
# 0x06C: MOV R15, 0x63
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C0363F"
|
||||
|
||||
# 0x06D: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D00000"
|
||||
|
||||
# 0x06E: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E00000"
|
||||
|
||||
# 0x06F: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F00000"
|
||||
|
||||
# 0x070: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0701501F"
|
||||
|
||||
# 0x071: JNZ 0x06D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0713206D"
|
||||
|
||||
# 0x072: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723D00F"
|
||||
|
||||
# 0x073: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0733E000"
|
||||
|
||||
# 0x074: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0743C00F"
|
||||
|
||||
# 0x075: MOV R15, 0x09
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750309F"
|
||||
|
||||
# 0x076: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07600000"
|
||||
|
||||
# 0x077: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07700000"
|
||||
|
||||
# 0x078: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07800000"
|
||||
|
||||
# 0x079: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0791501F"
|
||||
|
||||
# 0x07A: JNZ 0x076
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A32076"
|
||||
|
||||
# 0x07B: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B3D00F"
|
||||
|
||||
# 0x07C: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C3E000"
|
||||
|
||||
# Assembled from hallo_welt_uart.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "000D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "010A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "034A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "042D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0543"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0650"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0755"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0820"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0956"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A31"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B2E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D52"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1064"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1179"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "122E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "130D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "140A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "164D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1769"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "186D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1969"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B69"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C73"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D74"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2069"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2265"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2320"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "246C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2569"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2665"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2762"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2865"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2920"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A4B"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D7A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3021"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3121"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3221"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "330D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "340A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,858 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; PROJECT "itest"
|
||||
; -------------------------------------------------
|
||||
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
xmem
|
||||
msg: dc "Hallo", 0
|
||||
xram: db 256
|
||||
|
||||
cmem 0
|
||||
cram: db 256
|
||||
|
||||
reg_revision: equ 0x00
|
||||
reg_testid: equ 0x01
|
||||
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
int_vec: jmp isr
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x010
|
||||
|
||||
start: call init
|
||||
cin R0, (cpu_revision)
|
||||
xout (reg_revision), R0
|
||||
|
||||
; Test 0
|
||||
call test0
|
||||
|
||||
; Test 1
|
||||
mov R0, 1
|
||||
xout (reg_testid), R0
|
||||
call test1
|
||||
|
||||
; Test 2
|
||||
mov R0, 2
|
||||
xout (reg_testid), R0
|
||||
call test2
|
||||
|
||||
; Test 3
|
||||
mov R0, 3
|
||||
xout (reg_testid), R0
|
||||
call test3
|
||||
|
||||
; Test 4
|
||||
mov R0, 4
|
||||
xout (reg_testid), R0
|
||||
call test4
|
||||
|
||||
; Test 5
|
||||
mov R0, 5
|
||||
xout (reg_testid), R0
|
||||
call test5
|
||||
|
||||
; Test 6
|
||||
mov R0, 6
|
||||
xout (reg_testid), R0
|
||||
call test6
|
||||
|
||||
; Test 7
|
||||
mov R0, 7
|
||||
xout (reg_testid), R0
|
||||
call test7
|
||||
|
||||
; Test 8
|
||||
mov R0, 8
|
||||
xout (reg_testid), R0
|
||||
call test8
|
||||
|
||||
; Test 9
|
||||
mov R0, 9
|
||||
xout (reg_testid), R0
|
||||
call test9
|
||||
|
||||
; Test 10
|
||||
mov R0, 10
|
||||
xout (reg_testid), R0
|
||||
call test10
|
||||
|
||||
; Test 11
|
||||
mov R0, 11
|
||||
xout (reg_testid), R0
|
||||
call test11
|
||||
|
||||
; Test 12
|
||||
mov R0, 12
|
||||
xout (reg_testid), R0
|
||||
call test12
|
||||
|
||||
; End of test
|
||||
mov R0, 0xFF
|
||||
xout (reg_testid), R0
|
||||
|
||||
jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
mov R3, 0
|
||||
mov R4, 0
|
||||
mov R5, 0
|
||||
mov R6, 0
|
||||
mov R7, 0
|
||||
mov R8, 0
|
||||
mov R9, 0
|
||||
mov R10, 0
|
||||
mov R11, 0
|
||||
mov R12, 0
|
||||
mov R13, 0
|
||||
mov R14, 0
|
||||
mov R15, 0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOV|R|K
|
||||
; MOV|R|R
|
||||
test0: mov R0, 0x10
|
||||
cmp R0, 0x10
|
||||
jne error
|
||||
add R0, 1
|
||||
|
||||
mov R1, R0
|
||||
cmp R1, 0x11
|
||||
jne error
|
||||
add R1, 1
|
||||
|
||||
mov R2, R1
|
||||
cmp R2, 0x12
|
||||
jne error
|
||||
add R2, 1
|
||||
|
||||
mov R3, R2
|
||||
cmp R3, 0x13
|
||||
jne error
|
||||
add R3, 1
|
||||
|
||||
mov R4, R3
|
||||
cmp R4, 0x14
|
||||
jne error
|
||||
add R4, 1
|
||||
|
||||
mov R5, R4
|
||||
cmp R5, 0x15
|
||||
jne error
|
||||
add R5, 1
|
||||
|
||||
mov R6, R5
|
||||
cmp R6, 0x16
|
||||
jne error
|
||||
add R6, 1
|
||||
|
||||
mov R7, R6
|
||||
cmp R7, 0x17
|
||||
jne error
|
||||
add R7, 1
|
||||
|
||||
mov R8, R7
|
||||
cmp R8, 0x18
|
||||
jne error
|
||||
add R8, 1
|
||||
|
||||
mov R9, R8
|
||||
cmp R9, 0x19
|
||||
jne error
|
||||
add R9, 1
|
||||
|
||||
mov R10, R9
|
||||
cmp R10, 0x1A
|
||||
jne error
|
||||
add R10, 1
|
||||
|
||||
mov R11, R10
|
||||
cmp R11, 0x1B
|
||||
jne error
|
||||
add R11, 1
|
||||
|
||||
mov R12, R11
|
||||
cmp R12, 0x1C
|
||||
jne error
|
||||
add R12, 1
|
||||
|
||||
mov R13, R12
|
||||
cmp R13, 0x1D
|
||||
jne error
|
||||
add R13, 1
|
||||
|
||||
mov R14, R13
|
||||
cmp R14, 0x1E
|
||||
jne error
|
||||
add R14, 1
|
||||
|
||||
mov R15, R14
|
||||
cmp R15, 0x1F
|
||||
jne error
|
||||
add R15, 1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Instruction test
|
||||
; TST|R
|
||||
; CMP|R|K
|
||||
; JNZ|K
|
||||
; JC|K
|
||||
; JNE|K
|
||||
; JLT|K
|
||||
; JGT|K
|
||||
; JLE|K
|
||||
; JGE|K
|
||||
; JMP|K
|
||||
test1: mov R0, 0 ; R0 <= 0
|
||||
tst R0
|
||||
jnz error
|
||||
jc error
|
||||
cmp R0, 0
|
||||
jne error
|
||||
jlt error
|
||||
jgt error
|
||||
jle t1_ok10
|
||||
jmp error
|
||||
|
||||
t1_ok10: jeq t1_ok20
|
||||
jmp error
|
||||
|
||||
t1_ok20: jge t1_ok30
|
||||
jmp error
|
||||
|
||||
t1_ok30: cmp R0, 0x55
|
||||
jeq error
|
||||
jlt t1_ok40
|
||||
jmp error
|
||||
|
||||
t1_ok40: jle t1_ok50
|
||||
jmp error
|
||||
|
||||
t1_ok50: jge error
|
||||
jgt error
|
||||
|
||||
mov R0, 0x55 ; R0 <= 0xAA
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0xAA
|
||||
jeq error
|
||||
jne t1_ok60
|
||||
jmp error
|
||||
|
||||
t1_ok60: jlt t1_ok70
|
||||
jmp error
|
||||
|
||||
t1_ok70: jle t1_ok80
|
||||
jmp error
|
||||
|
||||
t1_ok80: jgt error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq t1_ok90
|
||||
jmp error
|
||||
|
||||
t1_ok90: jne error
|
||||
jlt error
|
||||
|
||||
jle t1_ok100
|
||||
jmp error
|
||||
|
||||
t1_ok100: jgt error
|
||||
jge t1_ok110
|
||||
jmp error
|
||||
|
||||
t1_ok110: mov R0, 0xAA ; R0 <= 0x55
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq error
|
||||
jne t1_ok120
|
||||
jmp error
|
||||
|
||||
t1_ok120: jgt t1_ok130
|
||||
jmp error
|
||||
|
||||
t1_ok130: jge t1_ok140
|
||||
jmp error
|
||||
|
||||
t1_ok140: jlt error
|
||||
jle error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; ADD|R|K
|
||||
; ADDC|R|K
|
||||
; ToDo: ADD|R|R
|
||||
; ToDo: ADDC|R|R
|
||||
; CMP|R|R
|
||||
test2: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t2_loop: add R0, 0x01
|
||||
addc R1, 0x00
|
||||
add R2, 1
|
||||
cmp R2, 0
|
||||
jne t2_L1
|
||||
add R3, 1
|
||||
cmp R3, 0x02
|
||||
t2_L1: jne t2_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; SUB|R|K
|
||||
; SUBC|R|K
|
||||
; ToDo: SUB|R|R
|
||||
; ToDo: SUBC|R|R
|
||||
; CMP|R|R
|
||||
test3: mov R0, 0x00
|
||||
mov R1, 0x03
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t3_loop: sub R0, 0x01
|
||||
subc R1, 0x00
|
||||
sub R2, 1
|
||||
cmp R2, 0xFF
|
||||
jne t3_L1
|
||||
sub R3, 1
|
||||
cmp R3, 0x00
|
||||
t3_L1: jne t3_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
; -------------------------------------------------
|
||||
; SUB|K|R
|
||||
; SUB|R|R
|
||||
; SUBC|R|R
|
||||
; SUBC|K|R
|
||||
; CMP|R|R
|
||||
test4: mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub 0x05, R0
|
||||
sub R1, 0x03
|
||||
cmp R0, R1
|
||||
jne error
|
||||
mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub R0, R1
|
||||
subc 0, R0
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
add R0, 0
|
||||
subc R1, R0
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVC|R|Ri
|
||||
; MOVC|R|Ki
|
||||
; MOVC|Ri|R
|
||||
; MOVC|Ri|K
|
||||
; MOVC|Ki|R
|
||||
test5: mov R0, 1
|
||||
movc (cram+0x5A), R0
|
||||
dec R0
|
||||
movc (cram+0), R0
|
||||
movc R1, (cram+0x5A)
|
||||
movc (R1), 0xA5
|
||||
movc R0, (R1)
|
||||
movc R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movc R0, (R1)
|
||||
t5_loop1: movc (R0), R0
|
||||
movc R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movc (R2), R1
|
||||
movc R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t5_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVX|R|Ri
|
||||
; MOVX|R|Ki
|
||||
; MOVX|Ri|R
|
||||
; MOVX|Ri|K
|
||||
; MOVX|Ki|R
|
||||
test6: mov R0, 1
|
||||
movx (xram+0x5A), R0
|
||||
dec R0
|
||||
movx (xram+0), R0
|
||||
movx R1, (xram+0x5A)
|
||||
movx (R1), 0xA5
|
||||
movx R0, (R1)
|
||||
movx R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movx R0, (R1)
|
||||
t6_loop1: movx (R0), R0
|
||||
movx R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movx (R2), R1
|
||||
movx R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t6_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PUSH|R
|
||||
; POP|R
|
||||
test7: mov R0, 0xAA
|
||||
mov R1, 0
|
||||
t7_loop1: push R0
|
||||
inc R0
|
||||
dec R1
|
||||
jnz t7_loop1
|
||||
t7_loop2: pop R0
|
||||
dec R1
|
||||
jnz t7_loop2
|
||||
cmp R0, 0xAA
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; JMP|K
|
||||
; CALL|K
|
||||
; RET
|
||||
test8: mov R0, 0x55
|
||||
push R0
|
||||
mov R0, 0
|
||||
mov R1, 0xFF
|
||||
call t8_rec
|
||||
pop R0
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
; Stack manipulations 1
|
||||
mov R0, return1'high
|
||||
mov R1, return1'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
ret
|
||||
|
||||
; Stack manipulations 2
|
||||
return1: mov R0, return2'high
|
||||
mov R1, return2'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
return2: ret
|
||||
|
||||
t8_rec: cmp R0, R1
|
||||
jeq ex_t8_rec
|
||||
inc R0
|
||||
jmp t8_rstub
|
||||
ex_t8_rec: dec R0
|
||||
dec R1
|
||||
ret
|
||||
|
||||
t8_rstub: call t8_rec
|
||||
jmp ex_t8_rec
|
||||
|
||||
; -------------------------------------------------
|
||||
; SWAP|R
|
||||
; SHL|R
|
||||
; SHR|R
|
||||
; ROL|R
|
||||
; ROR|R
|
||||
; ROLC|R
|
||||
; RORC|R
|
||||
test9: mov R0, 0xA5 ; SWAP test
|
||||
mov R1, 0x5A
|
||||
swap R0
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
swap R0
|
||||
cmp R0, 0xA5
|
||||
jne error
|
||||
mov R0, 0xD2
|
||||
swap R0
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
swap R1
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
cmp R1, 0xA5
|
||||
jne error
|
||||
|
||||
mov R0, 0x2D
|
||||
shl R0 ; SHL test
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xB4
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x68
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xD0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xA0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x40
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x80
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x00
|
||||
jne error
|
||||
|
||||
mov R1, 0x84
|
||||
shr R1 ; SHR test
|
||||
cmp R1, 0x42
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x21
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x10
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x08
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x02
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x01
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x00
|
||||
jne error
|
||||
|
||||
mov R0, 0xC5 ; ROL test
|
||||
rol R0
|
||||
cmp R0, 0x8B
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x17
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x2E
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x5C
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xB8
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x71
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xE2
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xC5
|
||||
jne error
|
||||
|
||||
mov R1, 0x63 ; ROR test
|
||||
ror R1
|
||||
cmp R1, 0xB1
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xD8
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x6C
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x36
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x1B
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x8D
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x63
|
||||
jne error
|
||||
|
||||
|
||||
xor R0, R0 ; ROLC generate
|
||||
mov R0, 0xC5
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
|
||||
cmp R0, 0xC5 ; ROLC verify
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x62
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xB1
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x58
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xAC
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x56
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x2B
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x15
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x8A
|
||||
jne error
|
||||
|
||||
xor R1, R1 ; RORC generate
|
||||
mov R1, 0x63
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
|
||||
cmp R1, 0x63 ; RORC verify
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x8C
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x19
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x33
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x66
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xCC
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x98
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x31
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; AND|R|R
|
||||
; AND|R|K
|
||||
; OR|R|R
|
||||
; OR|R|K
|
||||
; XOR|R|R
|
||||
; XOR|R|K
|
||||
test10: mov R0, 0xA5 ; AND
|
||||
swap R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
jne error
|
||||
pop R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
pop R1
|
||||
jne error
|
||||
swap R1
|
||||
mov R2, 0x0F
|
||||
and R1, R2
|
||||
cmp R1, 0x05
|
||||
jne error
|
||||
|
||||
mov R0, 0x05 ; OR
|
||||
mov R2, 0xA0
|
||||
swap R0
|
||||
or R2, R0
|
||||
cmp R2, 0xF0
|
||||
jne error
|
||||
swap R0
|
||||
or R0, 0x50
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
mov R1, 0x01
|
||||
mov R0, 0x01
|
||||
xor R0, 0x01
|
||||
jnz error
|
||||
xor R0, R1
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
test11:
|
||||
mov R0, 0x03
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
xin R0, (2)
|
||||
or R0, 1
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
xin R0, (2)
|
||||
and R0, 0xFE
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Tests clrc, setc
|
||||
test12: sub R0, 0
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
sub R0, 0
|
||||
jc error
|
||||
|
||||
mov R0, 0
|
||||
clrc
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
clrc
|
||||
jc error
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
isr: inc R14
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x3FF
|
||||
error: jmp error
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x2FF
|
||||
ok: jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,50 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=$VHDL_HOME/tools/jcpu
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -1,29 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp init
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x45
|
||||
mov R1, 0xF5
|
||||
|
||||
call mul8x8
|
||||
stop: jmp stop
|
||||
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../jasm/mul8x8.inc.jsm"
|
||||
|
||||
|
||||
|
||||
@@ -1,154 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x001
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
|
||||
|
||||
# 0x001: MOV R00, 0x45
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
|
||||
|
||||
# 0x002: MOV R01, 0xF5
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
|
||||
|
||||
# 0x003: CALL 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
|
||||
|
||||
# 0x004: JMP 0x004
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
|
||||
|
||||
# 0x005: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
|
||||
|
||||
# 0x006: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
|
||||
|
||||
# 0x007: PUSH R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
|
||||
|
||||
# 0x008: MOV R04, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
|
||||
|
||||
# 0x009: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
|
||||
|
||||
# 0x00A: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
|
||||
|
||||
# 0x00B: MOV R03, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
|
||||
|
||||
# 0x00C: CMP R04, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
|
||||
|
||||
# 0x00D: JEQ 0x015
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
|
||||
|
||||
# 0x00E: SHR R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
|
||||
|
||||
# 0x00F: JNC 0x012
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
|
||||
|
||||
# 0x010: ADD R02, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
|
||||
|
||||
# 0x011: ADDC R03, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
|
||||
|
||||
# 0x012: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
|
||||
|
||||
# 0x013: ROLC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
|
||||
|
||||
# 0x014: JMP 0x00C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
|
||||
|
||||
# 0x015: ADD R00, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
|
||||
|
||||
# 0x016: ADDC R01, R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
|
||||
|
||||
# 0x017: POP R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
|
||||
|
||||
# 0x01A: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
|
||||
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,64 +0,0 @@
|
||||
0 NOP
|
||||
1 HALT
|
||||
2 MOV|R|R
|
||||
3 MOV|R|K
|
||||
4 MOVX|R|Ri
|
||||
5 MOVX|R|Ki
|
||||
6 MOVX|Ri|R
|
||||
7 MOVX|Ri|K
|
||||
8 MOVX|Ki|R
|
||||
9 MOVC|R|Ri
|
||||
10 MOVC|R|Ki
|
||||
11 MOVC|Ri|R
|
||||
12 MOVC|Ri|K
|
||||
13 MOVC|Ki|R
|
||||
14 CMP|R|R
|
||||
15 CMP|R|K
|
||||
16 ADD|R|R
|
||||
17 ADD|R|K
|
||||
18 ADDC|R|R
|
||||
19 ADDC|R|K
|
||||
20 SUB|R|R
|
||||
21 SUB|R|K
|
||||
22 SUBC|R|R
|
||||
23 SUBC|R|K
|
||||
24 AND|R|R
|
||||
25 AND|R|K
|
||||
26 OR|R|R
|
||||
27 OR|R|K
|
||||
28 XOR|R|R
|
||||
29 XOR|R|K
|
||||
30 SHL|R
|
||||
31 SHR|R
|
||||
32 ROL|R
|
||||
33 ROR|R
|
||||
34 ROLC|R
|
||||
35 RORC|R
|
||||
36 XOUT|Ki|R
|
||||
37 XOUT|Ri|K
|
||||
38 COUT|Ki|R
|
||||
39 COUT|Ri|K
|
||||
40 XIN|R|Ki
|
||||
41 CIN|R|Ki
|
||||
42 SWAP|R
|
||||
43 SETC
|
||||
44 UNDEF
|
||||
45 UNDEF
|
||||
46 SUB|K|R
|
||||
47 SUBC|K|R
|
||||
48 JMP|K
|
||||
49 JZ|K
|
||||
50 JNZ|K
|
||||
51 JC|K
|
||||
52 JNC|K
|
||||
53 JLT|K
|
||||
54 JGT|K
|
||||
55 JLE|K
|
||||
56 JGE|K
|
||||
57 JEQ|K
|
||||
58 JNE|K
|
||||
59 CALL|K
|
||||
60 PUSH|R
|
||||
61 POP|R
|
||||
62 RET
|
||||
63 RETI
|
||||
@@ -1,50 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
cpu_revision: equ 0x00 ; RO
|
||||
cpu_control: equ 0x01 ; R/W
|
||||
cpu_status: equ 0x02 ; RO
|
||||
cpu_int_ctrl: equ 0x03 ; R/W
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
; nop
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x05
|
||||
cout (cpu_int_ctrl), R0
|
||||
mov R0, 0x00
|
||||
loop: nop
|
||||
inc R0
|
||||
nop
|
||||
call subr
|
||||
nop
|
||||
push R3
|
||||
nop
|
||||
push R2
|
||||
nop
|
||||
push R1
|
||||
nop
|
||||
push R0
|
||||
nop
|
||||
pop R0
|
||||
nop
|
||||
pop R1
|
||||
nop
|
||||
pop R2
|
||||
nop
|
||||
pop R3
|
||||
nop
|
||||
jmp loop
|
||||
|
||||
subr: ret
|
||||
@@ -1,157 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: MOV R00, 0x05
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
|
||||
|
||||
# 0x003: COUT (0x03), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
|
||||
|
||||
# 0x004: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
|
||||
|
||||
# 0x005: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
|
||||
|
||||
# 0x006: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
|
||||
|
||||
# 0x007: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
|
||||
|
||||
# 0x008: CALL 0x01B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
|
||||
|
||||
# 0x009: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
|
||||
|
||||
# 0x00A: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
|
||||
|
||||
# 0x00B: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
|
||||
|
||||
# 0x00C: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
|
||||
|
||||
# 0x00D: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
|
||||
|
||||
# 0x00E: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
|
||||
|
||||
# 0x00F: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
|
||||
|
||||
# 0x010: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
|
||||
|
||||
# 0x011: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
|
||||
|
||||
# 0x012: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
|
||||
|
||||
# 0x013: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
|
||||
|
||||
# 0x014: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
|
||||
|
||||
# 0x015: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
|
||||
|
||||
# 0x016: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
|
||||
|
||||
# 0x017: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
|
||||
|
||||
# 0x01A: JMP 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
|
||||
|
||||
# 0x01B: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
|
||||
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,41 +0,0 @@
|
||||
; External registers
|
||||
btn_port: equ 0x00 ; RO
|
||||
led_port: equ 0x01 ; R/W
|
||||
uart_data: equ 0x02 ; R/W
|
||||
lcd_port: equ 0x03 ; R/W
|
||||
ctrl_reg: equ 0x04 ; R/W
|
||||
CTRL_VGA_ENABLE: equ 0x04
|
||||
CTRL_TIMER_ENABLE: equ 0x02
|
||||
dip_port: equ 0x05 ; RO
|
||||
uart_status: equ 0x06 ; RO
|
||||
sdram_reg: equ 0x07 ; R/W
|
||||
FIFO_CTRL_IS_CMD: equ 0x04
|
||||
FIFO_CTRL_IS_WRITE: equ 0x10
|
||||
FIFO_CTRL_IS_READ: equ 0x20
|
||||
FIFO_STAT_CMD_FULL: equ 0x01
|
||||
FIFO_STAT_CMD_EMPTY: equ 0x02
|
||||
FIFO_STAT_WRITE_DATA_FULL: equ 0x04
|
||||
FIFO_STAT_WRITE_DATA_EMPTY: equ 0x08
|
||||
FIFO_STAT_READ_DATA_FULL: equ 0x10
|
||||
FIFO_STAT_READ_DATA_EMPTY: equ 0x20
|
||||
sdram_addr: equ 0x08 ; R/W
|
||||
sdram_addr0: equ 0x08 ; R/W
|
||||
sdram_addr1: equ 0x09 ; R/W
|
||||
sdram_addr2: equ 0x0A ; R/W
|
||||
reg_cg_char_addr: equ 0x0B ; RW
|
||||
reg_cg_line_addr: equ 0x0C ; RW
|
||||
reg_cg_data: equ 0x0D ; RW
|
||||
reg_cg_ctrl: equ 0x0E ; WO
|
||||
reg_hwstat: equ 0x0E ; RO
|
||||
reg_color_red: equ 0x10 ; RW
|
||||
reg_color_grn: equ 0x11 ; RW
|
||||
reg_color_blu: equ 0x12 ; RW
|
||||
uart_baudrate: equ 0x13 ; R/W
|
||||
vga_read_addr: equ 0x14 ; R/W
|
||||
vga_read_addr0: equ 0x14 ; R/W
|
||||
vga_read_addr1: equ 0x15 ; R/W
|
||||
vga_read_addr2: equ 0x16 ; R/W
|
||||
timer_reload: equ 0x17 ; R/W
|
||||
timer_reload0: equ 0x17 ; R/W
|
||||
timer_reload1: equ 0x18 ; R/W
|
||||
timer_reload2: equ 0x19 ; R/W
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 7.8 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 3.5 KiB |
@@ -1,24 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Sun Mar 21 20:24:10 2021
|
||||
[*]
|
||||
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_embedded/cpu_embedded.ghw"
|
||||
[dumpfile_mtime] "Sun Mar 21 20:24:02 2021"
|
||||
[dumpfile_size] 23928
|
||||
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_embedded/cpu_embedded.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1000 600
|
||||
[pos] -1 -1
|
||||
*-28.221537 367000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.tb_cpu_embedded.
|
||||
[sst_width] 233
|
||||
[signals_width] 78
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 144
|
||||
@28
|
||||
top.tb_cpu_embedded.uut.clk
|
||||
@29
|
||||
top.tb_cpu_embedded.uut.rst
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@@ -1,16 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
include jcpu_core.inc
|
||||
|
||||
SRCS += $(JCPU_CORE_SRCS)
|
||||
SRCS += ../src/itest_irom.vhdl
|
||||
SRCS += ../src/cpu_embedded.vhd
|
||||
SRCS += ../src/tb_cpu_embedded.vhd
|
||||
|
||||
# Compile
|
||||
TARGET := cpu_embedded
|
||||
ENTITY := tb_cpu_embedded
|
||||
|
||||
include $(VHDL_HOME)/make/ghdl.mk
|
||||
|
||||
@@ -1,20 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
|
||||
include jcpu_core.inc
|
||||
|
||||
SRCS += $(UART_SIM_SRCS)
|
||||
SRCS += $(JCPU_CORE_SRCS)
|
||||
SRCS += ../src/hallo_welt_uart_irom.vhdl
|
||||
SRCS += ../src/hallo_welt_uart_xrom.vhdl
|
||||
SRCS += ../src/cpu_embedded_with_uart.vhd
|
||||
SRCS += ../src/tb_cpu_embedded_with_uart.vhd
|
||||
|
||||
# Compile
|
||||
TARGET := tb_cpu_embedded_with_uart
|
||||
ENTITY := tb_cpu_embedded_with_uart
|
||||
RUN_TIME := 100us
|
||||
|
||||
include $(VHDL_HOME)/make/ghdl.mk
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Sun Mar 21 20:23:20 2021
|
||||
[*]
|
||||
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_itest/cpu_itest.ghw"
|
||||
[dumpfile_mtime] "Sun Mar 21 20:23:14 2021"
|
||||
[dumpfile_size] 23880
|
||||
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_itest/cpu_itest.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1000 600
|
||||
[pos] -1 -1
|
||||
*-28.353857 33340 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.tb_cpu.
|
||||
[treeopen] top.tb_cpu.uut.
|
||||
[treeopen] top.tb_cpu.uut.inst_pc.
|
||||
[sst_width] 233
|
||||
[signals_width] 134
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 144
|
||||
@22
|
||||
#{top.tb_cpu.xmem_din[7:0]} top.tb_cpu.xmem_din[7] top.tb_cpu.xmem_din[6] top.tb_cpu.xmem_din[5] top.tb_cpu.xmem_din[4] top.tb_cpu.xmem_din[3] top.tb_cpu.xmem_din[2] top.tb_cpu.xmem_din[1] top.tb_cpu.xmem_din[0]
|
||||
@23
|
||||
#{top.tb_cpu.uut.inst_pc.pc_next[11:0]} top.tb_cpu.uut.inst_pc.pc_next[11] top.tb_cpu.uut.inst_pc.pc_next[10] top.tb_cpu.uut.inst_pc.pc_next[9] top.tb_cpu.uut.inst_pc.pc_next[8] top.tb_cpu.uut.inst_pc.pc_next[7] top.tb_cpu.uut.inst_pc.pc_next[6] top.tb_cpu.uut.inst_pc.pc_next[5] top.tb_cpu.uut.inst_pc.pc_next[4] top.tb_cpu.uut.inst_pc.pc_next[3] top.tb_cpu.uut.inst_pc.pc_next[2] top.tb_cpu.uut.inst_pc.pc_next[1] top.tb_cpu.uut.inst_pc.pc_next[0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@@ -1,17 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
include jcpu_core.inc
|
||||
|
||||
SRCS += $(JCPU_CORE_SRCS)
|
||||
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
|
||||
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
|
||||
SRCS += ../src/itest_irom.vhdl
|
||||
SRCS += ../src/tb_cpu_itest.vhd
|
||||
|
||||
# Compile
|
||||
TARGET := cpu_itest
|
||||
ENTITY := tb_cpu
|
||||
|
||||
include $(VHDL_HOME)/make/ghdl.mk
|
||||
|
||||
@@ -1,20 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
PKG_NAME := JCPU_CORE
|
||||
|
||||
# -----------------------------------------------------------
|
||||
MOD_PATH := $(LIB_PATH)/CPUs/JCpu/src/core
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/cpu_pkg.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/cpu.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/alu.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/chipram.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/chipreg.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/dpath_ctrl.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/int_ctrl.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/pc.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/reg_dual.vhd
|
||||
$(PKG_NAME)_SRCS += $(MOD_PATH)/stack_ctrl.vhd
|
||||
|
||||
# -----------------------------------------------------------
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Mon Mar 22 20:01:47 2021
|
||||
[*]
|
||||
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/mul8x8/mul8x8.ghw"
|
||||
[dumpfile_mtime] "Mon Mar 22 20:00:48 2021"
|
||||
[dumpfile_size] 25852
|
||||
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/mul8x8/mul8x8.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1173 600
|
||||
[pos] -1 -1
|
||||
*-28.009827 724000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.tb_cpu_embedded.
|
||||
[treeopen] top.tb_cpu_embedded.uut.
|
||||
[sst_width] 233
|
||||
[signals_width] 150
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 144
|
||||
@28
|
||||
top.tb_cpu_embedded.rst
|
||||
top.tb_cpu_embedded.clk
|
||||
@22
|
||||
#{top.tb_cpu_embedded.uut.irom_addr[11:0]} top.tb_cpu_embedded.uut.irom_addr[11] top.tb_cpu_embedded.uut.irom_addr[10] top.tb_cpu_embedded.uut.irom_addr[9] top.tb_cpu_embedded.uut.irom_addr[8] top.tb_cpu_embedded.uut.irom_addr[7] top.tb_cpu_embedded.uut.irom_addr[6] top.tb_cpu_embedded.uut.irom_addr[5] top.tb_cpu_embedded.uut.irom_addr[4] top.tb_cpu_embedded.uut.irom_addr[3] top.tb_cpu_embedded.uut.irom_addr[2] top.tb_cpu_embedded.uut.irom_addr[1] top.tb_cpu_embedded.uut.irom_addr[0]
|
||||
@23
|
||||
#{top.tb_cpu_embedded.uut.irom_data[17:0]} top.tb_cpu_embedded.uut.irom_data[17] top.tb_cpu_embedded.uut.irom_data[16] top.tb_cpu_embedded.uut.irom_data[15] top.tb_cpu_embedded.uut.irom_data[14] top.tb_cpu_embedded.uut.irom_data[13] top.tb_cpu_embedded.uut.irom_data[12] top.tb_cpu_embedded.uut.irom_data[11] top.tb_cpu_embedded.uut.irom_data[10] top.tb_cpu_embedded.uut.irom_data[9] top.tb_cpu_embedded.uut.irom_data[8] top.tb_cpu_embedded.uut.irom_data[7] top.tb_cpu_embedded.uut.irom_data[6] top.tb_cpu_embedded.uut.irom_data[5] top.tb_cpu_embedded.uut.irom_data[4] top.tb_cpu_embedded.uut.irom_data[3] top.tb_cpu_embedded.uut.irom_data[2] top.tb_cpu_embedded.uut.irom_data[1] top.tb_cpu_embedded.uut.irom_data[0]
|
||||
@22
|
||||
#{top.tb_cpu_embedded.xmem_addr[7:0]} top.tb_cpu_embedded.xmem_addr[7] top.tb_cpu_embedded.xmem_addr[6] top.tb_cpu_embedded.xmem_addr[5] top.tb_cpu_embedded.xmem_addr[4] top.tb_cpu_embedded.xmem_addr[3] top.tb_cpu_embedded.xmem_addr[2] top.tb_cpu_embedded.xmem_addr[1] top.tb_cpu_embedded.xmem_addr[0]
|
||||
#{top.tb_cpu_embedded.xmem_dout[7:0]} top.tb_cpu_embedded.xmem_dout[7] top.tb_cpu_embedded.xmem_dout[6] top.tb_cpu_embedded.xmem_dout[5] top.tb_cpu_embedded.xmem_dout[4] top.tb_cpu_embedded.xmem_dout[3] top.tb_cpu_embedded.xmem_dout[2] top.tb_cpu_embedded.xmem_dout[1] top.tb_cpu_embedded.xmem_dout[0]
|
||||
#{top.tb_cpu_embedded.xmem_din[7:0]} top.tb_cpu_embedded.xmem_din[7] top.tb_cpu_embedded.xmem_din[6] top.tb_cpu_embedded.xmem_din[5] top.tb_cpu_embedded.xmem_din[4] top.tb_cpu_embedded.xmem_din[3] top.tb_cpu_embedded.xmem_din[2] top.tb_cpu_embedded.xmem_din[1] top.tb_cpu_embedded.xmem_din[0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@@ -1,16 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
include jcpu_core.inc
|
||||
|
||||
SRCS += $(JCPU_CORE_SRCS)
|
||||
SRCS += ../src/mul8x8_irom.vhdl
|
||||
SRCS += ../src/cpu_embedded.vhd
|
||||
SRCS += ../src/tb_cpu_embedded.vhd
|
||||
|
||||
# Compile
|
||||
TARGET := mul8x8
|
||||
ENTITY := tb_cpu_embedded
|
||||
|
||||
include $(VHDL_HOME)/make/ghdl.mk
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Sun Mar 21 20:25:04 2021
|
||||
[*]
|
||||
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.ghw"
|
||||
[dumpfile_mtime] "Sun Mar 21 20:25:01 2021"
|
||||
[dumpfile_size] 22085
|
||||
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1000 600
|
||||
[pos] -1 -1
|
||||
*-28.221537 563000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.tb_cpu.
|
||||
[sst_width] 233
|
||||
[signals_width] 78
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 144
|
||||
@28
|
||||
top.tb_cpu.uut.clk
|
||||
@29
|
||||
top.tb_cpu.uut.rst
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@@ -1,17 +0,0 @@
|
||||
# -----------------------------------------------------------
|
||||
include $(VHDL_HOME)/make/defs.mk
|
||||
# -----------------------------------------------------------
|
||||
include jcpu_core.inc
|
||||
|
||||
SRCS += $(JCPU_CORE_SRCS)
|
||||
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
|
||||
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
|
||||
SRCS += ../src/reti_issue_irom.vhdl
|
||||
SRCS += ../src/tb_cpu_itest.vhd
|
||||
|
||||
# Compile
|
||||
TARGET := reti_issue
|
||||
ENTITY := tb_cpu
|
||||
|
||||
include $(VHDL_HOME)/make/ghdl.mk
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Sun Apr 4 08:30:47 2021
|
||||
[*]
|
||||
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/tb_cpu_embedded_with_uart/tb_cpu_embedded_with_uart.fst"
|
||||
[dumpfile_mtime] "Sun Apr 4 08:29:53 2021"
|
||||
[dumpfile_size] 5098
|
||||
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/tb_cpu_embedded_with_uart/tb_cpu_embedded_with_uart.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1856 1136
|
||||
[pos] 1983 26
|
||||
*-27.352621 339300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[sst_width] 383
|
||||
[signals_width] 256
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 331
|
||||
@28
|
||||
uut.clk
|
||||
uut.ce
|
||||
uut.rst
|
||||
@22
|
||||
uut.irom_data[17:0]
|
||||
@28
|
||||
uut.cpu_xmem_re
|
||||
uut.cpu_xmem_we
|
||||
@22
|
||||
uut.cpu_xmem_dout[7:0]
|
||||
uut.cpu_xmem_din[7:0]
|
||||
uut.cpu_xmem_addr[7:0]
|
||||
@29
|
||||
uut.cpu_io_sel
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@@ -1,674 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
of the GPL, as needed to protect the freedom of users.
|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
software on general-purpose computers, but in those that do, we wish to
|
||||
avoid the special danger that patents applied to a free program could
|
||||
make it effectively proprietary. To prevent this, the GPL assures that
|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/itest_irom.vhdl"
|
||||
vcom -explicit -93 "../src/tb_cpu_itest.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 50us
|
||||
@@ -1,105 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/ce
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
|
||||
add wave -noupdate -format Logic /tb_cpu/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_we
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/io_sel
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -divider CPU
|
||||
add wave -noupdate -format Literal /tb_cpu/reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/status_reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/alu_status
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_we
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_save
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_restore
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
|
||||
add wave -noupdate -divider Stack
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -divider Chipram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -divider Sequencer
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
|
||||
add wave -noupdate -divider {Chip register}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
|
||||
configure wave -namecolwidth 166
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {49892711 ps} {50005647 ps}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/tb_cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/itest_irom.vhdl"
|
||||
vsim -t 1ps -lib work tb_cpu_embedded
|
||||
do {tb_cpu_embedded.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -1,26 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/rst
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/clk
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/xmem_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/xmem_din
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
|
||||
configure wave -namecolwidth 143
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {10500 ns}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/itest_irom.vhdl"
|
||||
vcom -explicit -93 "../src/tb_cpu_itest.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu_itest.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 400us
|
||||
@@ -1,122 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/ce
|
||||
add wave -noupdate -format Logic /tb_cpu/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_we
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/io_sel
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
|
||||
add wave -noupdate -divider CPU
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/status_reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/alu_status
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_we
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_save
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_restore
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
|
||||
add wave -noupdate -divider Stack
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -divider Chipram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/ram
|
||||
add wave -noupdate -divider Sequencer
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
|
||||
add wave -noupdate -divider {Chip register}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -divider {Interrup Ctrl.}
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
|
||||
add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {107309645 ps} 0}
|
||||
configure wave -namecolwidth 166
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {420 us}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/reti_issue_irom.vhdl"
|
||||
vcom -explicit -93 "../src/tb_cpu_irq.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu_reti_issue.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 50us
|
||||
@@ -1,90 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -format Literal /tb_cpu/reg
|
||||
add wave -noupdate -format Logic /tb_cpu/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/int_ack
|
||||
add wave -noupdate -format Literal /tb_cpu/xmem_din
|
||||
add wave -noupdate -format Literal /tb_cpu/xmem_dout
|
||||
add wave -noupdate -format Literal /tb_cpu/xmem_addr
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_we
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_re
|
||||
add wave -noupdate -format Logic /tb_cpu/io_sel
|
||||
add wave -noupdate -format Literal /tb_cpu/sram
|
||||
add wave -noupdate -divider {Chip RAM}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -divider {Interrupt controller}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -divider PC
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
|
||||
add wave -noupdate -divider {Stack controller}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {47421482 ps}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/tb_cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/mul8x8_irom.vhdl"
|
||||
vsim -t 1ps -lib work tb_cpu_embedded
|
||||
do {tb_mul8x8.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -1,31 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
|
||||
configure wave -namecolwidth 143
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {9002500 ps} {10052500 ps}
|
||||
@@ -1,236 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The arithmetic logic unit
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity alu is
|
||||
Generic (
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
op_en : in STD_LOGIC;
|
||||
cy_in : in STD_LOGIC;
|
||||
op1_in : in unsigned (data_width-1 downto 0);
|
||||
op2_in : in unsigned (data_width-1 downto 0);
|
||||
opsel : in alu_op_t;
|
||||
res_out : out unsigned (data_width-1 downto 0);
|
||||
stat_load : in STD_LOGIC;
|
||||
stat_in : in alu_status_t;
|
||||
stat_out : out alu_status_t
|
||||
);
|
||||
end alu;
|
||||
|
||||
architecture Behavioral of alu is
|
||||
|
||||
signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
|
||||
signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
|
||||
signal status, stat_reg : alu_status_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function test_zero(arg : unsigned) return STD_LOGIC is
|
||||
variable res : STD_LOGIC;
|
||||
begin
|
||||
res := '0';
|
||||
for i in arg'range loop
|
||||
res := res or To_X01(arg(i));
|
||||
end loop;
|
||||
|
||||
return not res;
|
||||
end test_zero;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_logic_func:
|
||||
process (op1_in, op2_in, opsel)
|
||||
begin
|
||||
|
||||
case opsel is
|
||||
when op1_and_op2 =>
|
||||
lf_res <= op1_in and op2_in;
|
||||
when op1_or_op2 =>
|
||||
lf_res <= op1_in or op2_in;
|
||||
when op1_xor_op2 =>
|
||||
lf_res <= op1_in xor op2_in;
|
||||
when others =>
|
||||
lf_res <= (others => '-');
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_shift_func:
|
||||
process (op1_in, left_shift, sh_cy_in)
|
||||
begin
|
||||
if left_shift = '1' then
|
||||
sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
|
||||
sh_cy <= op1_in(op1_in'left);
|
||||
else
|
||||
sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
|
||||
sh_cy <= op1_in(op1_in'right);
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_alu_out:
|
||||
process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
|
||||
|
||||
begin
|
||||
|
||||
case opsel is
|
||||
|
||||
when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= sum_cy;
|
||||
result <= sum_res;
|
||||
when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= stat_reg.carry;
|
||||
result <= lf_res;
|
||||
when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= sh_cy;
|
||||
result <= sh_res;
|
||||
when swap_op =>
|
||||
result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
|
||||
status <= stat_reg;
|
||||
when others =>
|
||||
result <= op2_in;
|
||||
status.zero <= stat_reg.zero;
|
||||
status.carry <= stat_reg.carry or cy_in;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_alu_in:
|
||||
process(opsel, op1_in, stat_reg)
|
||||
|
||||
begin
|
||||
|
||||
add_subn <= '-';
|
||||
sum_cy_in <= '-';
|
||||
sh_cy_in <= '-';
|
||||
left_shift <= '-';
|
||||
|
||||
case opsel is
|
||||
|
||||
when op1_add_op2 =>
|
||||
sum_cy_in <= '0';
|
||||
add_subn <= '1';
|
||||
|
||||
when op1_sub_op2 =>
|
||||
sum_cy_in <= '0';
|
||||
add_subn <= '0';
|
||||
|
||||
when op1_addc_op2 =>
|
||||
sum_cy_in <= stat_reg.carry;
|
||||
add_subn <= '1';
|
||||
|
||||
when op1_subc_op2 =>
|
||||
sum_cy_in <= stat_reg.carry;
|
||||
add_subn <= '0';
|
||||
|
||||
when shl_op =>
|
||||
sh_cy_in <= '0';
|
||||
left_shift <= '1';
|
||||
|
||||
when shr_op =>
|
||||
sh_cy_in <= '0';
|
||||
left_shift <= '0';
|
||||
|
||||
when rol_op =>
|
||||
sh_cy_in <= op1_in(op1_in'left);
|
||||
left_shift <= '1';
|
||||
|
||||
when ror_op =>
|
||||
sh_cy_in <= op1_in(op1_in'right);
|
||||
left_shift <= '0';
|
||||
|
||||
when rolc_op =>
|
||||
sh_cy_in <= stat_reg.carry;
|
||||
left_shift <= '1';
|
||||
|
||||
when rorc_op =>
|
||||
sh_cy_in <= stat_reg.carry;
|
||||
left_shift <= '0';
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_res_reg:
|
||||
process(clk, rst, op_en, stat_load, res_reg, stat_reg)
|
||||
begin
|
||||
if rst = '1' then
|
||||
res_reg <= (others => '0');
|
||||
stat_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if op_en = '1' then
|
||||
res_reg <= result;
|
||||
stat_reg <= status;
|
||||
elsif stat_load = '1' then
|
||||
stat_reg <= stat_in;
|
||||
end if;
|
||||
end if;
|
||||
res_out <= res_reg;
|
||||
stat_out <= stat_reg;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
alu_addsub:
|
||||
process(op1_in, op2_in, sum_cy_in, add_subn)
|
||||
variable sum : unsigned(data_width+1 downto 0);
|
||||
variable op1, op2 : unsigned(data_width+1 downto 0);
|
||||
begin
|
||||
if add_subn = '1' then
|
||||
op1 := '0' & op1_in & '1';
|
||||
op2 := '0' & op2_in & sum_cy_in;
|
||||
sum := op1 + op2;
|
||||
else
|
||||
op1 := '0' & op1_in & not sum_cy_in;
|
||||
op2 := '0' & op2_in & '1';
|
||||
sum := op1 - op2;
|
||||
end if;
|
||||
|
||||
-- Form sum + carry
|
||||
sum_res <= sum(data_width downto 1);
|
||||
sum_cy <= sum(sum'left);
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,85 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: On-chip RAM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity chipram is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end chipram;
|
||||
|
||||
architecture Behavioral of chipram is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,117 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: On-Chip registers
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity chipreg is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
din : in dmem_data_t;
|
||||
dout : out dmem_data_t;
|
||||
ctrl_in : in creg_ctrl_in_t;
|
||||
ctrl_out : out creg_ctrl_out_t
|
||||
);
|
||||
end chipreg;
|
||||
|
||||
architecture Behavioral of chipreg is
|
||||
|
||||
signal reg_bank_sel : bank_sel_t;
|
||||
signal reg_int_ctrl : int_ctrl_in_t;
|
||||
signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
proc_assign_ctrl_lines:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
ctrl_out.bank_sel <= reg_bank_sel;
|
||||
ctrl_out.int_ctrl <= reg_int_ctrl;
|
||||
ctrl_out.stk_high <= reg_stk_high;
|
||||
ctrl_out.cmem_high <= reg_cmem_high;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_write:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
reg_stk_high <= (others => '0');
|
||||
reg_cmem_high <= (others => '0');
|
||||
reg_bank_sel <= (others => '0');
|
||||
reg_int_ctrl.enable <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
case addr is
|
||||
when X"01" =>
|
||||
reg_bank_sel(bank_sel_t'range) <= din(bank_sel_t'range);
|
||||
when X"03" =>
|
||||
reg_int_ctrl.enable <= din(0);
|
||||
when X"04" =>
|
||||
reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
when X"05" =>
|
||||
reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_read:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case addr is
|
||||
when X"00" => -- Revison
|
||||
dout <= to_unsigned(REVISION, dmem_data_t'length);
|
||||
when X"01" => -- Control 0
|
||||
dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
|
||||
when X"02" => -- CPU status
|
||||
dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
|
||||
when X"03" => -- Interrupt control
|
||||
dout <= "0000000" & reg_int_ctrl.enable;
|
||||
when X"04" => -- Upper stack bits out
|
||||
dout <= "0000" & reg_cmem_high;
|
||||
when X"05" => -- Upper cmem bits out
|
||||
dout <= "0000" & reg_stk_high;
|
||||
when others =>
|
||||
if addr(0) = '0' then
|
||||
dout <= X"DE";
|
||||
else
|
||||
dout <= X"AD";
|
||||
end if;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,563 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: JCPU top file
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity cpu is
|
||||
Generic (
|
||||
use_instr_register : boolean := false;
|
||||
use_ctrl_rom : boolean := true
|
||||
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out std_logic
|
||||
);
|
||||
end cpu;
|
||||
|
||||
architecture rtl of cpu is
|
||||
|
||||
COMPONENT stack_ctrl
|
||||
GENERIC (
|
||||
addr_width : integer
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
push : in STD_LOGIC;
|
||||
pop : in STD_LOGIC;
|
||||
din : in inst_addr_t;
|
||||
dout : out inst_addr_t;
|
||||
mem_we : out STD_LOGIC;
|
||||
ptr_out : out unsigned (addr_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pc
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
inc : in STD_LOGIC;
|
||||
load : in STD_LOGIC;
|
||||
pc_in : in inst_addr_t;
|
||||
pc_out : out inst_addr_t;
|
||||
pc_next : out inst_addr_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dpath_ctrl
|
||||
GENERIC (
|
||||
use_rom : boolean
|
||||
);
|
||||
Port (
|
||||
inst_in : in inst_t;
|
||||
iphase_in : in iphase_t;
|
||||
status_in : in cpu_status_t;
|
||||
ctrl_out : out dpath_ctrl_out_t;
|
||||
idout : out inst_addr_t;
|
||||
ddout : out dmem_data_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT int_ctrl
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ctrl_in : in int_ctrl_in_t;
|
||||
int_in : in STD_LOGIC;
|
||||
int_exit : in STD_LOGIC;
|
||||
iphase_in : in iphase_t;
|
||||
int_ack_out : out STD_LOGIC;
|
||||
stat_save_out : out STD_LOGIC;
|
||||
stat_rest_out : out STD_LOGIC;
|
||||
pc_addr_out : out inst_addr_t;
|
||||
pc_load_out : out STD_LOGIC;
|
||||
stk_push_out : out STD_LOGIC;
|
||||
stk_pop_out : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT reg_dual
|
||||
GENERIC (
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
ptr_a : in reg_ptr_t;
|
||||
ptr_b : in reg_ptr_t;
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT chipram
|
||||
GENERIC (
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT chipreg
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
din : in dmem_data_t;
|
||||
dout : out dmem_data_t;
|
||||
ctrl_in : in creg_ctrl_in_t;
|
||||
ctrl_out : out creg_ctrl_out_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT alu
|
||||
GENERIC (
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
op_en : in STD_LOGIC;
|
||||
cy_in : in STD_LOGIC;
|
||||
op1_in : in unsigned (data_width-1 downto 0);
|
||||
op2_in : in unsigned (data_width-1 downto 0);
|
||||
opsel : in alu_op_t;
|
||||
res_out : out unsigned (data_width-1 downto 0);
|
||||
stat_load : in STD_LOGIC;
|
||||
stat_in : in alu_status_t;
|
||||
stat_out : out alu_status_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
|
||||
signal ctrl : dpath_ctrl_out_t;
|
||||
signal stk_out : inst_addr_t;
|
||||
signal stk_in : inst_addr_t;
|
||||
signal stk_reg : inst_addr_t;
|
||||
signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
|
||||
signal iphase : iphase_t;
|
||||
signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
|
||||
signal reg_din : dmem_data_t;
|
||||
signal alu_op1, alu_op2, alu_result : dmem_data_t;
|
||||
signal alu_status : alu_status_t;
|
||||
signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
|
||||
signal ctrl_inst : inst_t;
|
||||
signal ctrl_iphase : iphase_t;
|
||||
signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
|
||||
signal status_save, status_restore : STD_LOGIC;
|
||||
signal creg_dout : dmem_data_t;
|
||||
signal cmem_din, cmem_dout : inst_addr_t;
|
||||
signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
|
||||
signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
|
||||
signal creg_ctrl_out : creg_ctrl_out_t;
|
||||
signal creg_ctrl_in : creg_ctrl_in_t;
|
||||
signal xio_sel, cio_sel : std_logic;
|
||||
signal mem_data : dmem_data_t;
|
||||
signal mem_addr : dmem_data_t;
|
||||
|
||||
begin
|
||||
io_sel <= xio_sel;
|
||||
instr_addr <= pc_out;
|
||||
pc_inc <= cpu_active and ctrl.lines.pc_inc;
|
||||
stk_addr <= '0' & stk_ptr;
|
||||
cpu_status.alu <= alu_status;
|
||||
creg_ctrl_in.alu <= alu_status;
|
||||
|
||||
xmem_dout <= mem_data;
|
||||
xmem_addr <= mem_addr;
|
||||
cmem_din <= creg_ctrl_out.cmem_high & mem_data;
|
||||
cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(JMIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0);
|
||||
|
||||
--------------------------------------------------------------------
|
||||
mem_ctrl_lines:
|
||||
process(ctrl.lines)
|
||||
begin
|
||||
xio_sel <= '0';
|
||||
xmem_re <= '0';
|
||||
xmem_we <= '0';
|
||||
cio_sel <= '0';
|
||||
cmem_we <= '0';
|
||||
creg_we <= '0';
|
||||
|
||||
case ctrl.lines.mem_access is
|
||||
when xmem_access =>
|
||||
xmem_re <= ctrl.lines.mem_read;
|
||||
xmem_we <= ctrl.lines.mem_write;
|
||||
when xio_access =>
|
||||
xio_sel <= '1';
|
||||
xmem_re <= ctrl.lines.mem_read;
|
||||
xmem_we <= ctrl.lines.mem_write;
|
||||
when cmem_access =>
|
||||
cmem_we <= ctrl.lines.mem_write;
|
||||
when cio_access =>
|
||||
cio_sel <= '1';
|
||||
creg_we <= ctrl.lines.mem_write;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
iphase_counter:
|
||||
process(rst, clk, ce)
|
||||
variable pos : integer;
|
||||
begin
|
||||
if rst = '1' then
|
||||
iphase <= iphase_t'low;
|
||||
cpu_active <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
cpu_active <= '0';
|
||||
if ce = '1' then
|
||||
cpu_active <= '1';
|
||||
if iphase = iphase_t'high then
|
||||
iphase <= iphase_t'low;
|
||||
else
|
||||
iphase <= iphase + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_instr_reg:
|
||||
if use_instr_register = true generate
|
||||
|
||||
instr_reg:
|
||||
process (rst, clk, ce)
|
||||
begin
|
||||
if rst = '1' then
|
||||
ctrl_inst <= (others => '0');
|
||||
ctrl_iphase <= 0;
|
||||
elsif rising_edge(clk) and ce = '1' then
|
||||
ctrl_inst <= instr_din;
|
||||
ctrl_iphase <= iphase;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end generate;
|
||||
|
||||
gen_instr_direct:
|
||||
if use_instr_register = false generate
|
||||
|
||||
ctrl_inst <= instr_din;
|
||||
ctrl_iphase <= iphase;
|
||||
|
||||
end generate;
|
||||
|
||||
status_register:
|
||||
process(clk, status_save)
|
||||
begin
|
||||
if rising_edge(clk) and status_save = '1' then
|
||||
status_reg.alu <= alu_status;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pc_pushpop:
|
||||
process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
|
||||
begin
|
||||
pc_load <= ctrl.lines.pc_load or int_pc_load;
|
||||
stk_push <= ctrl.lines.stk_push or (int_stk_push and not was_pop2pc);
|
||||
stk_pop <= (ctrl.lines.stk_pop and not ctrl.lines.pc_load) or int_stk_pop or ((ctrl.lines.stk_pop and ctrl.lines.pc_load) and not int_pc_load);
|
||||
end process;
|
||||
|
||||
lines_delay:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
was_pcld <= ctrl.lines.pc_load;
|
||||
was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
stk_mux:
|
||||
process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
|
||||
begin
|
||||
if was_pcld = '1' and int_stk_push = '1' then
|
||||
stk_in <= idata;
|
||||
elsif ctrl.lines.stk_push = '1' and ctrl.lines.pc_load = '0' then
|
||||
stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
|
||||
else
|
||||
stk_in <= pc_next;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
pc_mux:
|
||||
process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
|
||||
begin
|
||||
|
||||
pc_in <= stk_out;
|
||||
if int_pc_load = '1' then
|
||||
if int_stk_pop = '0' then
|
||||
pc_in <= int_pc_addr;
|
||||
end if;
|
||||
elsif ctrl.lines.pc_load = '1' then
|
||||
if ctrl.lines.stk_pop = '0' then
|
||||
pc_in <= idata;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
mem_data_mux:
|
||||
process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
|
||||
begin
|
||||
case ctrl.lines.ddata_src_sel is
|
||||
when reg_a =>
|
||||
mem_data <= reg_a_dout;
|
||||
when reg_b =>
|
||||
mem_data <= reg_b_dout;
|
||||
when const =>
|
||||
mem_data <= const_data;
|
||||
when others =>
|
||||
mem_data <= const_data;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
mem_addr_mux:
|
||||
process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel)
|
||||
begin
|
||||
case ctrl.lines.daddr_src_sel is
|
||||
when reg_a =>
|
||||
mem_addr <= reg_a_dout;
|
||||
when reg_b =>
|
||||
mem_addr <= reg_b_dout;
|
||||
when const =>
|
||||
mem_addr <= const_data;
|
||||
when others =>
|
||||
mem_addr <= const_data;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
reg_in_mux:
|
||||
process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.reg_src_sel is
|
||||
when xmem_src =>
|
||||
data := xmem_din;
|
||||
when cmem_src =>
|
||||
if cio_sel = '0' then
|
||||
data := cmem_dout(dmem_data_t'range);
|
||||
else
|
||||
data := creg_dout(dmem_data_t'range);
|
||||
end if;
|
||||
when stk_src =>
|
||||
data := stk_out(dmem_data_t'range);
|
||||
when others =>
|
||||
data := alu_result;
|
||||
end case;
|
||||
|
||||
reg_din <= data;
|
||||
|
||||
end process;
|
||||
|
||||
alu_op1_mux:
|
||||
process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.alu_op1_src_sel is
|
||||
when reg_a =>
|
||||
data := reg_a_dout;
|
||||
when reg_b =>
|
||||
data := reg_b_dout;
|
||||
when others =>
|
||||
data := const_data;
|
||||
end case;
|
||||
|
||||
alu_op1 <= data;
|
||||
|
||||
end process;
|
||||
|
||||
alu_op2_mux:
|
||||
process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.alu_op2_src_sel is
|
||||
when reg_a =>
|
||||
data := reg_a_dout;
|
||||
when reg_b =>
|
||||
data := reg_b_dout;
|
||||
when others =>
|
||||
data := const_data;
|
||||
end case;
|
||||
|
||||
alu_op2 <= data;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------
|
||||
inst_stack_ctrl: stack_ctrl
|
||||
GENERIC MAP (
|
||||
addr_width => STACK_SIZE_BITS
|
||||
)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
push => stk_push,
|
||||
pop => stk_pop,
|
||||
dout => stk_reg,
|
||||
din => stk_in,
|
||||
ptr_out => stk_ptr,
|
||||
mem_we => stk_we
|
||||
);
|
||||
|
||||
inst_pc: pc
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
inc => pc_inc,
|
||||
load => pc_load,
|
||||
pc_in => pc_in,
|
||||
pc_out => pc_out,
|
||||
pc_next => pc_next
|
||||
);
|
||||
|
||||
inst_dpath_ctrl: dpath_ctrl
|
||||
GENERIC MAP (
|
||||
use_rom => use_ctrl_rom
|
||||
)
|
||||
PORT MAP(
|
||||
inst_in => ctrl_inst,
|
||||
iphase_in => ctrl_iphase,
|
||||
status_in => cpu_status,
|
||||
ctrl_out => ctrl,
|
||||
ddout => const_data,
|
||||
idout => idata
|
||||
);
|
||||
|
||||
inst_int_ctrl: int_ctrl
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ctrl_in => creg_ctrl_out.int_ctrl,
|
||||
int_in => int_in,
|
||||
int_ack_out => int_ack,
|
||||
int_exit => ctrl.lines.int_exit,
|
||||
iphase_in => ctrl_iphase,
|
||||
stat_save_out => status_save,
|
||||
stat_rest_out => status_restore,
|
||||
pc_addr_out => int_pc_addr,
|
||||
pc_load_out => int_pc_load,
|
||||
stk_push_out => int_stk_push,
|
||||
stk_pop_out => int_stk_pop
|
||||
|
||||
);
|
||||
|
||||
inst_reg_ab: reg_dual
|
||||
GENERIC MAP (
|
||||
addr_width => REG_SIZE_BITS,
|
||||
data_width => DMEM_DATA_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
we_a => ctrl.lines.reg_we,
|
||||
ptr_a => ctrl.reg_a_ptr,
|
||||
ptr_b => ctrl.reg_b_ptr,
|
||||
din_a => reg_din,
|
||||
dout_a => reg_a_dout,
|
||||
dout_b => reg_b_dout
|
||||
);
|
||||
|
||||
inst_chipram: chipram
|
||||
GENERIC MAP (
|
||||
addr_width => CHIPRAM_SIZE_BITS,
|
||||
data_width => IMEM_ADDR_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => cpu_active,
|
||||
en_b => cpu_active,
|
||||
we_a => stk_we,
|
||||
we_b => cmem_we,
|
||||
addr_a => stk_addr,
|
||||
addr_b => cmem_addr,
|
||||
din_a => stk_reg,
|
||||
din_b => cmem_din,
|
||||
dout_a => stk_out,
|
||||
dout_b => cmem_dout
|
||||
);
|
||||
|
||||
inst_chipreg: chipreg
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => creg_we,
|
||||
addr => mem_addr,
|
||||
din => mem_data,
|
||||
dout => creg_dout,
|
||||
ctrl_in => creg_ctrl_in,
|
||||
ctrl_out => creg_ctrl_out
|
||||
);
|
||||
|
||||
inst_alu: alu
|
||||
GENERIC MAP (
|
||||
data_width => DMEM_DATA_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
op_en => ctrl.lines.alu_load,
|
||||
cy_in => ctrl.lines.alu_cy_in,
|
||||
op1_in => alu_op1,
|
||||
op2_in => alu_op2,
|
||||
opsel => ctrl.lines.alu_opsel,
|
||||
res_out => alu_result,
|
||||
stat_load => status_restore,
|
||||
stat_in => status_reg.alu,
|
||||
stat_out => alu_status
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -1,852 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Types, constants and functions for JCPU
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
|
||||
package cpu_pkg is
|
||||
|
||||
-- Revision of the CPU
|
||||
constant REVISION : integer := 4;
|
||||
|
||||
-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
|
||||
constant CHIPRAM_SIZE_BITS : integer := 10;
|
||||
|
||||
-- Number of registers (16 registers fixed)
|
||||
constant REG_SIZE_BITS : integer := 4;
|
||||
|
||||
-- Instruction memory
|
||||
constant IMEM_ADDR_WIDTH : integer := 12;
|
||||
|
||||
-- Data memory
|
||||
constant DMEM_DATA_WIDTH : integer := 8;
|
||||
constant DMEM_ADDR_WIDTH : integer := 8;
|
||||
|
||||
-- Instruction format
|
||||
constant INST_OPCODE_WIDTH : integer := 6;
|
||||
constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
|
||||
|
||||
-- Microcode ROM
|
||||
constant MUCODE_ADDR_WIDTH : integer := 9;
|
||||
|
||||
-- Stack depth (uses lower half of CHIPRAM)
|
||||
constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
|
||||
|
||||
--Types
|
||||
subtype iphase_t is integer range 0 to 1;
|
||||
type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
|
||||
type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
|
||||
type alu_src_t is (reg_a, reg_b, const);
|
||||
type ddata_src_t is (reg_a, reg_b, const);
|
||||
type daddr_src_t is (reg_a, reg_b, const);
|
||||
subtype instr_name_t is string(1 to 12);
|
||||
type instr_name_array_t is array (0 to 63) of instr_name_t;
|
||||
subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
|
||||
subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype reg_ptr_t is unsigned (3 downto 0);
|
||||
type dmem_array_t is array (natural range <>) of dmem_data_t;
|
||||
type instr_addr_array is array (integer range <>) of inst_addr_t;
|
||||
subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
|
||||
|
||||
type alu_op_t is
|
||||
(
|
||||
pass_op2,
|
||||
op1_add_op2,
|
||||
op1_sub_op2,
|
||||
op1_addc_op2,
|
||||
op1_subc_op2,
|
||||
op1_and_op2,
|
||||
op1_or_op2,
|
||||
op1_xor_op2,
|
||||
swap_op,
|
||||
shl_op,
|
||||
shr_op,
|
||||
rol_op,
|
||||
ror_op,
|
||||
rolc_op,
|
||||
rorc_op
|
||||
);
|
||||
|
||||
type alu_status_t is record
|
||||
zero : STD_LOGIC;
|
||||
carry : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cpu_status_t is record
|
||||
alu : alu_status_t;
|
||||
end record;
|
||||
|
||||
type ctrl_lines_t is record
|
||||
reg_we : STD_LOGIC;
|
||||
reg_src_sel : reg_src_t;
|
||||
alu_op1_src_sel : alu_src_t;
|
||||
alu_op2_src_sel : alu_src_t;
|
||||
alu_opsel : alu_op_t;
|
||||
alu_load : STD_LOGIC;
|
||||
alu_cy_in : STD_LOGIC;
|
||||
ddata_src_sel : ddata_src_t;
|
||||
daddr_src_sel : daddr_src_t;
|
||||
pc_load : STD_LOGIC;
|
||||
pc_inc : STD_LOGIC;
|
||||
stk_push : STD_LOGIC;
|
||||
stk_pop : STD_LOGIC;
|
||||
mem_access : mem_access_t;
|
||||
mem_read : STD_LOGIC;
|
||||
mem_write : STD_LOGIC;
|
||||
int_exit : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type dpath_ctrl_out_t is record
|
||||
lines : ctrl_lines_t;
|
||||
reg_a_ptr : reg_ptr_t;
|
||||
reg_b_ptr : reg_ptr_t;
|
||||
end record;
|
||||
|
||||
type int_ctrl_in_t is record
|
||||
enable : std_logic;
|
||||
end record;
|
||||
|
||||
type creg_ctrl_out_t is record
|
||||
bank_sel : bank_sel_t;
|
||||
int_ctrl : int_ctrl_in_t;
|
||||
stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
end record;
|
||||
|
||||
type creg_ctrl_in_t is record
|
||||
alu : alu_status_t;
|
||||
end record;
|
||||
|
||||
|
||||
type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
|
||||
|
||||
constant instr_name_array : instr_name_array_t :=
|
||||
(
|
||||
"NOP ", -- 00
|
||||
"HALT ", -- 01
|
||||
"MOV|R|R ", -- 02
|
||||
"MOV|R|K ", -- 03
|
||||
"MOVX|R|Ri ", -- 04
|
||||
"MOVX|R|Ki ", -- 05
|
||||
"MOVX|Ri|R ", -- 06
|
||||
"MOVX|Ri|K ", -- 07
|
||||
"MOVX|Ki|R ", -- 08
|
||||
"MOVC|R|Ri ", -- 09
|
||||
"MOVC|R|Ki ", -- 0A
|
||||
"MOVC|Ri|R ", -- 0B
|
||||
"MOVC|Ri|K ", -- 0C
|
||||
"MOVC|Ki|R ", -- 0D
|
||||
"CMP|R|R ", -- 0E
|
||||
"CMP|R|K ", -- 0F
|
||||
"ADD|R|R ", -- 10
|
||||
"ADD|R|K ", -- 11
|
||||
"ADDC|R|R ", -- 12
|
||||
"ADDC|R|K ", -- 13
|
||||
"SUB|R|R ", -- 14
|
||||
"SUB|R|K ", -- 15
|
||||
"SUBC|R|R ", -- 16
|
||||
"SUBC|R|K ", -- 17
|
||||
"AND|R|R ", -- 18
|
||||
"AND|R|K ", -- 19
|
||||
"OR|R|R ", -- 1A
|
||||
"OR|R|K ", -- 1B
|
||||
"XOR|R|R ", -- 1C
|
||||
"XOR|R|K ", -- 1D
|
||||
"SHL|R ", -- 1E
|
||||
"SHR|R ", -- 1F
|
||||
"ROL|R ", -- 20
|
||||
"ROR|R ", -- 21
|
||||
"ROLC|R ", -- 22
|
||||
"RORC|R ", -- 23
|
||||
"XOUT|Ki|R ", -- 24
|
||||
"XOUT|Ri|K ", -- 25
|
||||
"COUT|Ki|R ", -- 26
|
||||
"COUT|Ri|K ", -- 27
|
||||
"XIN|R|Ki ", -- 28
|
||||
"CIN|R|Ki ", -- 29
|
||||
"SWAP|R ", -- 2A
|
||||
"SETC ", -- 2B
|
||||
"UNDEF ", -- 2C
|
||||
"UNDEF ", -- 2D
|
||||
"SUB|K|R ", -- 2E
|
||||
"SUBC|K|R ", -- 2F
|
||||
"JMP|K ", -- 30
|
||||
"JZ|K ", -- 31
|
||||
"JNZ|K ", -- 32
|
||||
"JC|K ", -- 33
|
||||
"JNC|K ", -- 34
|
||||
"JLT|K ", -- 35
|
||||
"JGT|K ", -- 36
|
||||
"JLE|K ", -- 37
|
||||
"JGE|K ", -- 38
|
||||
"JEQ|K ", -- 39
|
||||
"JNE|K ", -- 3A
|
||||
"CALL|K ", -- 3B
|
||||
"PUSH|R ", -- 3C
|
||||
"POP|R ", -- 3D
|
||||
"RET ", -- 3E
|
||||
"RETI " -- 3F
|
||||
);
|
||||
-- Functions
|
||||
function Instr(opcode : opcode_t) return inst_t;
|
||||
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
|
||||
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_ptr_a : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_ptr_a, reg_ptr_b : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_ptr_a, reg_ptr_b, reg_ptr_c : integer) return inst_t;
|
||||
function ctrl_lines_default return ctrl_lines_t;
|
||||
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
|
||||
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
|
||||
function gen_murom return murom_t;
|
||||
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
|
||||
function JMIN (X, Y: INTEGER) return INTEGER;
|
||||
function JMAX (X, Y: INTEGER) return INTEGER;
|
||||
|
||||
end cpu_pkg;
|
||||
|
||||
package body cpu_pkg is
|
||||
|
||||
function Instr(opcode : opcode_t) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_ptr_a : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_ptr_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_ptr_a, reg_ptr_b : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_ptr_b, reg_ptr_t'length));
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_ptr_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_ptr_a, reg_ptr_b, reg_ptr_c : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_ptr_c, reg_ptr_t'length));
|
||||
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_ptr_b, reg_ptr_t'length));
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_ptr_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function ctrl_lines_default return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
begin
|
||||
result.pc_load := '0';
|
||||
result.pc_inc := '0';
|
||||
result.stk_push := '0';
|
||||
result.stk_pop := '0';
|
||||
result.reg_we := '0';
|
||||
result.reg_src_sel := alu_src;
|
||||
result.ddata_src_sel := reg_a;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '0';
|
||||
result.alu_cy_in := '0';
|
||||
result.mem_access := cmem_access;
|
||||
result.mem_read := '0';
|
||||
result.mem_write := '0';
|
||||
result.int_exit := '0';
|
||||
return result;
|
||||
|
||||
end ctrl_lines_default;
|
||||
|
||||
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
|
||||
variable instr_name : instr_name_t;
|
||||
begin
|
||||
instr_name := instr_name_array(to_integer(opcode));
|
||||
return idecoder(instr_name, iphase, status);
|
||||
end idecoder;
|
||||
|
||||
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
variable ze, cy : STD_LOGIC;
|
||||
|
||||
begin
|
||||
ze := status.alu.zero;
|
||||
cy := status.alu.carry;
|
||||
|
||||
result := ctrl_lines_default;
|
||||
if iphase = 0 then
|
||||
result.pc_inc := '1';
|
||||
end if;
|
||||
|
||||
case instr_name is
|
||||
|
||||
when "HALT " =>
|
||||
result.pc_inc := '0';
|
||||
when "SETC " => -- carry <= 1
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
result.alu_cy_in := '1';
|
||||
when "MOV|R|R " => -- R(a) <= R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOV|R|K " => -- R(a) <= #kk
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|Ri|R " => -- [R(b)] <= R(a)
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVC|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "COUT|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := cio_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVC|R|Ri " => -- R(a) <= [R(b)]
|
||||
result.mem_access := cmem_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := reg_b;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := cmem_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CIN|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := cio_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "COUT|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := cio_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVX|Ri|R " => -- [R(b)] <= R(a)
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVX|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "XOUT|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := xio_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVX|R|Ri " => -- R(a) <= [R(b)]
|
||||
result.mem_access := xmem_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := reg_b;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
elsif iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVX|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := xmem_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
elsif iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "XIN|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := xio_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
elsif iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVX|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "XOUT|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := xio_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "ADD|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_add_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADD|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_add_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADDC|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_addc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADDC|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_addc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|K|R " => -- R(a) <= k - R(a)
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := const;
|
||||
result.alu_op2_src_sel := reg_a;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|K|R " => -- R(a) <= K - R(a)
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := const;
|
||||
result.alu_op2_src_sel := reg_a;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "AND|R|R " => -- R(a) <= R(a) and R(b)
|
||||
result.alu_opsel := op1_and_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "AND|R|K " => -- R(a) <= R(a) and k
|
||||
result.alu_opsel := op1_and_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "OR|R|R " => -- R(a) <= R(a) or R(b)
|
||||
result.alu_opsel := op1_or_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "OR|R|K " => -- R(a) <= R(a) or R(b)
|
||||
result.alu_opsel := op1_or_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "XOR|R|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.alu_opsel := op1_xor_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "XOR|R|K " => -- R(a) <= R(a) xor R(b)
|
||||
result.alu_opsel := op1_xor_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SWAP|R " => -- R(a) <= R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := swap_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SHL|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := shl_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SHR|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := shr_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROL|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rol_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROR|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := ror_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROLC|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rolc_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "RORC|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rorc_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CMP|R|R " => --
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
when "CMP|R|K " => --
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.alu_load := '1';
|
||||
when "JMP|K " => -- PC <= #addr
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
when "JZ|K " => -- PC <= #addr, zero
|
||||
if iphase = 0 then
|
||||
if ze = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNZ|K " => -- PC <= #addr, !zero
|
||||
if iphase = 0 then
|
||||
if ze = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JC|K " => -- PC <= #addr, carry
|
||||
if iphase = 0 then
|
||||
if cy = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNC|K " => -- PC <= #addr, !carry
|
||||
if iphase = 0 then
|
||||
if cy = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JLT|K " => -- PC <= #addr, !carry
|
||||
if iphase = 0 then
|
||||
if cy = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JGT|K " => --
|
||||
if iphase = 0 then
|
||||
if (cy or ze) = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JLE|K " => --
|
||||
if iphase = 0 then
|
||||
if (cy xor ze) = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JGE|K " => --
|
||||
if iphase = 0 then
|
||||
if (not cy or ze) = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JEQ|K " => --
|
||||
if iphase = 0 then
|
||||
if ze = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNE|K " => --
|
||||
if iphase = 0 then
|
||||
if ze = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "PUSH|R " => -- push
|
||||
if iphase = 0 then
|
||||
result.stk_push := '1';
|
||||
end if;
|
||||
when "POP|R " => -- pop
|
||||
result.reg_src_sel := stk_src;
|
||||
if iphase = 0 then
|
||||
result.stk_pop := '1';
|
||||
elsif iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CALL|K " => -- call
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
result.stk_push := '1';
|
||||
end if;
|
||||
when "RET " => -- return
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
result.stk_pop := '1';
|
||||
end if;
|
||||
when "RETI " => -- return
|
||||
result.pc_inc := '0';
|
||||
result.int_exit := '1';
|
||||
|
||||
when others => null; -- nop
|
||||
end case;
|
||||
|
||||
return result;
|
||||
|
||||
end idecoder;
|
||||
|
||||
function gen_murom return murom_t is
|
||||
variable result : murom_t;
|
||||
variable opcode : opcode_t;
|
||||
variable iphase : iphase_t;
|
||||
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
|
||||
variable status : cpu_status_t;
|
||||
variable pos : integer := 0;
|
||||
|
||||
begin
|
||||
for i in 0 to 2**addr'length-1 loop
|
||||
addr := to_unsigned(i, addr'length);
|
||||
opcode := addr(opcode'length-1 downto 0);
|
||||
pos := opcode'length;
|
||||
iphase := 0;
|
||||
if addr(pos) = '1' then
|
||||
iphase := 1;
|
||||
end if;
|
||||
pos := pos + 1;
|
||||
status.alu.zero := addr(pos);
|
||||
pos := pos + 1;
|
||||
status.alu.carry := addr(pos);
|
||||
|
||||
result(i) := idecoder(opcode, iphase, status);
|
||||
end loop;
|
||||
|
||||
return result;
|
||||
end gen_murom;
|
||||
|
||||
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
|
||||
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
|
||||
begin
|
||||
addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
|
||||
return addr;
|
||||
|
||||
end get_muromaddr;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function JMIN (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y < X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end JMIN;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function JMAX (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y > X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end JMAX;
|
||||
|
||||
|
||||
end cpu_pkg;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user