commit stale changes

added Mips Basic Pipe
- changed gtkw
2026-07-26 21:29:38 +02:00 · 2024-06-14 17:40:04 +02:00 · 2023-03-10 20:47:13 +01:00 · 2022-09-18 08:22:23 +02:00 · 2022-09-12 23:25:51 +02:00 · 2022-09-12 23:22:03 +02:00
105 changed files with 29987 additions and 5313 deletions
@@ -1,2 +0,0 @@
 LIB_PATH := $(VHDL_HOME)/lib
@@ -11,13 +11,14 @@ LANG_STD ?= 93c
 IEEE_STD ?= standard
 RUN_TIME ?= 1000ns
 WAVE_FORMAT ?= fst
 EXTRA_OPTS ?=
 # Build path
 BUILD_DIR ?= build/$(TARGET)
 WORK_DIR ?= $(BUILD_DIR)/$(WORK_LIB)
 # Can be pre-initialized by user
-RUN_OPTS += --stop-time=$(RUN_TIME)
+RUN_OPTS += --stop-time=$(RUN_TIME) $(EXTRA_OPTS) 
 GHDL_OPTS += --work=$(WORK_LIB) --workdir=$(WORK_DIR) --std=$(LANG_STD) --ieee=$(IEEE_STD)
 # -------------------------------------------------
@@ -49,7 +50,7 @@ SIM_FILE-fst := $(BUILD_DIR)/$(TARGET).fst
 GTK_OPTS-fst := --fst=$(SIM_FILE-fst)
 SIM_FILE-ghw := $(BUILD_DIR)/$(TARGET).ghw
-GTK_OPTS-ghw := --wave=$(SIM_FILE-ghw)
+GTK_OPTS-ghw := --wave=$(SIM_FILE-ghw) --read-wave-opt=$(TARGET).wopt
 SIM_FILE := $(SIM_FILE-$(WAVE_FORMAT))
 GTK_OPTS := $(GTK_OPTS-$(WAVE_FORMAT))
@@ -93,16 +94,20 @@ run_wave: analyze
 synth: analyze
 	$(GHDL) --synth $(GHDL_OPTS) $(ENTITY)
 tree: analyze
 	$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS) --no-run --disp-tree=inst
 genwopt: analyze
 	rm -rf $(TARGET).wopt.templ
 	$(GHDL) -r $(GHDL_OPTS) $(ENTITY) --stop-time=0ps --write-wave-opt=$(TARGET).wopt.templ --wave=$(BUILD_DIR)/$(TARGET).ghw
 wave: run_wave
 	exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
 result:
 	exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
-tree: analyze
+
 	$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS) --no-run --disp-tree=inst
 .PHONY: list
 INSTR = $(foreach number,$(SRCS),echo $(number);)
 list:
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include package_other.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include package1.inc
 include package2.inc
@@ -0,0 +1,2 @@
 LIB_PATH := $(VHDL_HOME)/lib
 VHDL_MAKE_HOME := $(VHDL_HOME)/Common/make
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 TOOL_PATH := $(VHDL_HOME)/tools/jcpu
 .PHONY: install uninstall
@@ -1,4 +1,4 @@
 .gitignore
 build/
-.gitignore
+*.wopt
-build/
+
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := JCPU_CORE
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
@@ -1,31 +1,37 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Sat Jul  2 11:01:23 2022
+[*] Mon Sep 12 21:25:14 2022
 [*]
-[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/build/tb_cpu_embedded/tb_cpu_embedded.fst"
+[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/build/tb_cpu_embedded/tb_cpu_embedded.ghw"
-[dumpfile_mtime] "Sat Jul  2 11:00:48 2022"
+[dumpfile_mtime] "Mon Sep 12 21:24:27 2022"
-[dumpfile_size] 3297
+[dumpfile_size] 23396
 [savefile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/tb_cpu_embedded.gtkw"
 [timestart] 0
 [size] 1854 1136
-[pos] -51 -51
+[pos] -1 -1
 *-28.221537 367000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.tb_cpu_embedded.
 [treeopen] top.tb_cpu_embedded.uut.
 [sst_width] 233
 [signals_width] 242
 [sst_expanded] 1
 [sst_vpaned_height] 330
@28
-uut.clk
+top.tb_cpu_embedded.uut.rst
-uut.rst
+top.tb_cpu_embedded.uut.clk
@22
-uut.irom_addr[11:0]
+#{top.tb_cpu_embedded.uut.irom_data[17:0]} top.tb_cpu_embedded.uut.irom_data[17] top.tb_cpu_embedded.uut.irom_data[16] top.tb_cpu_embedded.uut.irom_data[15] top.tb_cpu_embedded.uut.irom_data[14] top.tb_cpu_embedded.uut.irom_data[13] top.tb_cpu_embedded.uut.irom_data[12] top.tb_cpu_embedded.uut.irom_data[11] top.tb_cpu_embedded.uut.irom_data[10] top.tb_cpu_embedded.uut.irom_data[9] top.tb_cpu_embedded.uut.irom_data[8] top.tb_cpu_embedded.uut.irom_data[7] top.tb_cpu_embedded.uut.irom_data[6] top.tb_cpu_embedded.uut.irom_data[5] top.tb_cpu_embedded.uut.irom_data[4] top.tb_cpu_embedded.uut.irom_data[3] top.tb_cpu_embedded.uut.irom_data[2] top.tb_cpu_embedded.uut.irom_data[1] top.tb_cpu_embedded.uut.irom_data[0]
-uut.irom_data[17:0]
+#{top.tb_cpu_embedded.uut.irom_addr[11:0]} top.tb_cpu_embedded.uut.irom_addr[11] top.tb_cpu_embedded.uut.irom_addr[10] top.tb_cpu_embedded.uut.irom_addr[9] top.tb_cpu_embedded.uut.irom_addr[8] top.tb_cpu_embedded.uut.irom_addr[7] top.tb_cpu_embedded.uut.irom_addr[6] top.tb_cpu_embedded.uut.irom_addr[5] top.tb_cpu_embedded.uut.irom_addr[4] top.tb_cpu_embedded.uut.irom_addr[3] top.tb_cpu_embedded.uut.irom_addr[2] top.tb_cpu_embedded.uut.irom_addr[1] top.tb_cpu_embedded.uut.irom_addr[0]
-uut.xmem_addr[7:0]
+#{top.tb_cpu_embedded.uut.xmem_addr[7:0]} top.tb_cpu_embedded.uut.xmem_addr[7] top.tb_cpu_embedded.uut.xmem_addr[6] top.tb_cpu_embedded.uut.xmem_addr[5] top.tb_cpu_embedded.uut.xmem_addr[4] top.tb_cpu_embedded.uut.xmem_addr[3] top.tb_cpu_embedded.uut.xmem_addr[2] top.tb_cpu_embedded.uut.xmem_addr[1] top.tb_cpu_embedded.uut.xmem_addr[0]
-uut.xmem_din[7:0]
+#{top.tb_cpu_embedded.uut.xmem_dout[7:0]} top.tb_cpu_embedded.uut.xmem_dout[7] top.tb_cpu_embedded.uut.xmem_dout[6] top.tb_cpu_embedded.uut.xmem_dout[5] top.tb_cpu_embedded.uut.xmem_dout[4] top.tb_cpu_embedded.uut.xmem_dout[3] top.tb_cpu_embedded.uut.xmem_dout[2] top.tb_cpu_embedded.uut.xmem_dout[1] top.tb_cpu_embedded.uut.xmem_dout[0]
-uut.xmem_dout[7:0]
+#{top.tb_cpu_embedded.uut.xmem_din[7:0]} top.tb_cpu_embedded.uut.xmem_din[7] top.tb_cpu_embedded.uut.xmem_din[6] top.tb_cpu_embedded.uut.xmem_din[5] top.tb_cpu_embedded.uut.xmem_din[4] top.tb_cpu_embedded.uut.xmem_din[3] top.tb_cpu_embedded.uut.xmem_din[2] top.tb_cpu_embedded.uut.xmem_din[1] top.tb_cpu_embedded.uut.xmem_din[0]
@28
-uut.xmem_we
+top.tb_cpu_embedded.uut.xmem_re
 top.tb_cpu_embedded.uut.xmem_we
 top.tb_cpu_embedded.uut.io_sel
 top.tb_cpu_embedded.uut.int_ack
@29
-uut.xmem_re
+top.tb_cpu_embedded.uut.int_in
 [pattern_trace] 1
 [pattern_trace] 0
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include jcpu_core.inc
@@ -11,6 +11,7 @@ SRCS += ../src/tb_cpu_embedded.vhd
 # Compile
 TARGET := tb_cpu_embedded
 ENTITY := tb_cpu_embedded
 WAVE_FORMAT := ghw
 include $(VHDL_MAKE_HOME)/ghdl.mk
@@ -0,0 +1,199 @@
 $ version 1.1
 # Signals in packages :
 # Signals in entities :
 /tb_cpu_embedded/rst
 /tb_cpu_embedded/clk
 /tb_cpu_embedded/ce
 /tb_cpu_embedded/int_in
 /tb_cpu_embedded/int_ack
 /tb_cpu_embedded/xmem_din
 /tb_cpu_embedded/xmem_dout
 /tb_cpu_embedded/xmem_addr
 /tb_cpu_embedded/xmem_we
 /tb_cpu_embedded/xmem_re
 /tb_cpu_embedded/io_sel
 /tb_cpu_embedded/sram
 /tb_cpu_embedded/uut/rst
 /tb_cpu_embedded/uut/clk
 /tb_cpu_embedded/uut/ce
 /tb_cpu_embedded/uut/int_in
 /tb_cpu_embedded/uut/int_ack
 /tb_cpu_embedded/uut/xmem_we
 /tb_cpu_embedded/uut/xmem_re
 /tb_cpu_embedded/uut/xmem_din
 /tb_cpu_embedded/uut/xmem_dout
 /tb_cpu_embedded/uut/xmem_addr
 /tb_cpu_embedded/uut/io_sel
 /tb_cpu_embedded/uut/irom_data
 /tb_cpu_embedded/uut/irom_addr
 /tb_cpu_embedded/uut/inst_cpu/rst
 /tb_cpu_embedded/uut/inst_cpu/clk
 /tb_cpu_embedded/uut/inst_cpu/ce
 /tb_cpu_embedded/uut/inst_cpu/int_in
 /tb_cpu_embedded/uut/inst_cpu/int_ack
 /tb_cpu_embedded/uut/inst_cpu/xmem_we
 /tb_cpu_embedded/uut/inst_cpu/xmem_re
 /tb_cpu_embedded/uut/inst_cpu/instr_din
 /tb_cpu_embedded/uut/inst_cpu/instr_addr
 /tb_cpu_embedded/uut/inst_cpu/xmem_din
 /tb_cpu_embedded/uut/inst_cpu/xmem_dout
 /tb_cpu_embedded/uut/inst_cpu/xmem_addr
 /tb_cpu_embedded/uut/inst_cpu/io_sel
 /tb_cpu_embedded/uut/inst_cpu/cpu_status
 /tb_cpu_embedded/uut/inst_cpu/status_reg
 /tb_cpu_embedded/uut/inst_cpu/ctrl
 /tb_cpu_embedded/uut/inst_cpu/stk_out
 /tb_cpu_embedded/uut/inst_cpu/stk_in
 /tb_cpu_embedded/uut/inst_cpu/stk_reg
 /tb_cpu_embedded/uut/inst_cpu/pc_in
 /tb_cpu_embedded/uut/inst_cpu/pc_out
 /tb_cpu_embedded/uut/inst_cpu/pc_next
 /tb_cpu_embedded/uut/inst_cpu/idata
 /tb_cpu_embedded/uut/inst_cpu/int_pc_addr
 /tb_cpu_embedded/uut/inst_cpu/iphase
 /tb_cpu_embedded/uut/inst_cpu/const_data
 /tb_cpu_embedded/uut/inst_cpu/reg_a_dout
 /tb_cpu_embedded/uut/inst_cpu/reg_b_dout
 /tb_cpu_embedded/uut/inst_cpu/reg_din
 /tb_cpu_embedded/uut/inst_cpu/alu_op1
 /tb_cpu_embedded/uut/inst_cpu/alu_op2
 /tb_cpu_embedded/uut/inst_cpu/alu_result
 /tb_cpu_embedded/uut/inst_cpu/alu_status
 /tb_cpu_embedded/uut/inst_cpu/pc_inc
 /tb_cpu_embedded/uut/inst_cpu/pc_load
 /tb_cpu_embedded/uut/inst_cpu/cpu_active
 /tb_cpu_embedded/uut/inst_cpu/stk_we
 /tb_cpu_embedded/uut/inst_cpu/cmem_we
 /tb_cpu_embedded/uut/inst_cpu/creg_we
 /tb_cpu_embedded/uut/inst_cpu/ctrl_inst
 /tb_cpu_embedded/uut/inst_cpu/ctrl_iphase
 /tb_cpu_embedded/uut/inst_cpu/was_pcld
 /tb_cpu_embedded/uut/inst_cpu/was_pop2pc
 /tb_cpu_embedded/uut/inst_cpu/int_pc_load
 /tb_cpu_embedded/uut/inst_cpu/int_stk_push
 /tb_cpu_embedded/uut/inst_cpu/int_stk_pop
 /tb_cpu_embedded/uut/inst_cpu/stk_push
 /tb_cpu_embedded/uut/inst_cpu/stk_pop
 /tb_cpu_embedded/uut/inst_cpu/status_save
 /tb_cpu_embedded/uut/inst_cpu/status_restore
 /tb_cpu_embedded/uut/inst_cpu/creg_dout
 /tb_cpu_embedded/uut/inst_cpu/cmem_din
 /tb_cpu_embedded/uut/inst_cpu/cmem_dout
 /tb_cpu_embedded/uut/inst_cpu/stk_addr
 /tb_cpu_embedded/uut/inst_cpu/cmem_addr
 /tb_cpu_embedded/uut/inst_cpu/stk_ptr
 /tb_cpu_embedded/uut/inst_cpu/creg_ctrl_out
 /tb_cpu_embedded/uut/inst_cpu/creg_ctrl_in
 /tb_cpu_embedded/uut/inst_cpu/xio_sel
 /tb_cpu_embedded/uut/inst_cpu/cio_sel
 /tb_cpu_embedded/uut/inst_cpu/mem_data
 /tb_cpu_embedded/uut/inst_cpu/mem_addr
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/rst
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/push
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/pop
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/ptr_out
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/din
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/dout
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/mem_we
 /tb_cpu_embedded/uut/inst_cpu/inst_stack_ctrl/ptr
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/rst
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/inc
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/load
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_in
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_out
 /tb_cpu_embedded/uut/inst_cpu/inst_pc/pc_next
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/inst_in
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/iphase_in
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/status_in
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ctrl_out
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/idout
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ddout
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/opcode
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/ctrl_lines
 /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/rst
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/ctrl_in
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_in
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_exit
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/iphase_in
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_addr_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_ack_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stat_save_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stat_rest_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_load_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_push_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_pop_out
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_state
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_state_next
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/pc_load
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_ack
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_push
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/stk_pop
 /tb_cpu_embedded/uut/inst_cpu/inst_int_ctrl/int_request
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/we_a
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/ptr_a
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/ptr_b
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/din_a
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/dout_a
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/dout_b
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/addr_a
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/addr_b
 /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/clka
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/clkb
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/en_a
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/en_b
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/we_a
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/we_b
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/addr_a
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/addr_b
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/din_a
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/din_b
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/dout_a
 /tb_cpu_embedded/uut/inst_cpu/inst_chipram/dout_b
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/rst
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/we
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/addr
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/din
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/dout
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/ctrl_in
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/ctrl_out
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_bank_sel
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_int_ctrl
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_stk_high
 /tb_cpu_embedded/uut/inst_cpu/inst_chipreg/reg_cmem_high
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/rst
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/clk
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/op_en
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/cy_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/op1_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/op2_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/opsel
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/res_out
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_load
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_out
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_cy
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_cy
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_cy_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_cy_in
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/left_shift
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/add_subn
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/result
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sum_res
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/lf_res
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/sh_res
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/res_reg
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/status
 /tb_cpu_embedded/uut/inst_cpu/inst_alu/stat_reg
 /tb_cpu_embedded/uut/inst_irom/clk
 /tb_cpu_embedded/uut/inst_irom/ce
 /tb_cpu_embedded/uut/inst_irom/addr
 /tb_cpu_embedded/uut/inst_irom/dout
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
 include jcpu_core.inc
@@ -0,0 +1 @@
 <mxfile host="app.diagrams.net" modified="2022-09-11T17:00:05.394Z" agent="5.0 (X11)" etag="ULt_GwP94m2c2vBAbY-Z" version="20.3.0" type="device"><diagram id="XI_-d3d4CUWLWsZJCx82" name="Seite-1">7VxNj9owEP01HLsidkLCcZfttmpVqRKHtqcqIl6w1sTImAL99XWITWIbmizN1ya9IDzEjjPvjT0znjCCs/XhAws3qy80QmQExtFhBB9HAEyhJz4TwTEVeME0FSwZjlKRkwnm+DeSwrGU7nCEttqFnFLC8UYXLmgcowXXZCFjdK9f9kyJftdNuESWYL4IiS39hiO+SqUB8DP5R4SXK3VnZyKfbx2qi+WTbFdhRPc5EXw/gjNGKU+/rQ8zRBLdKb2k/Z6u/HqeGEMxL9PhZffpeYp/ftzsHZ89LcE8+EzeyVF+hWQnH1hOlh+VBhjdxRFKBhmP4MN+hTmab8JF8uteQC5kK74mouWIr3I4xDg6XJ2nc356wRpE14izo7hEdXCkBiVjHKXAfaZ/V4pWedVPpDCUkC/PQ2daEV+kYl6hJLd7SoKdU5JfrCQxijBb0XgQtrBJhAtCd1EjCgOmwlyvlMJgXfoKSugrju6TJeykqHC7xQtdLTrphCLY8XvSuPMcXwl+nASO6yrB4yF//eMx3/qKGBZPh5gUpjNCkbVEGloXa3LIlogX0cNGJ6d974L2lYwhEnL8S5/GJUjkHb5SLCaYgQ918AMD1C3dsQWSnfJLqDEOnOjjWOxI1WANdCLI+alv58y0Ps7ofAFeEV0OmKdcC3xPttOuqpV1TBr5frezLMWpeBEqZKPbKht9g0XurXQExpo2bZaOykerZQ1zJjolvbKUdDQ6ggI+/tuyV0jIt7E8TlydR35VhDQHqpuQtjs754mDD8ZiIuMZZ8QiqHApuE7JLWf0Bc0ooQkhYhonHsszJsQQhQQv44TXghUJdx4SBwWL0OFe/rDGUZTc5qJ7oxO/Cg9nrCvfsz3CSZMOjgNKgDHGcX8RcTzDHGDbkMAh20fn0CgRV+a2T6nVq3tn2V2rrV3GjOtv9sIdw5sHZkxb9y7jDQu3InWXxs0rIEDduE0GhZuZIro96m3b3sqklnqEW1X2Btu2txpTXHps6BfFhmUxLxGptcqNqjIHjhErnOfXFDXsTJZwRE/9xhZHeuOBmvaoNqS2HFB1ZvCGDPTt5+zMXdkcqGbLAxdTJKd+jgV+byyve6ZnJ0f+ZnpFPs1WsIari6kYVMmeMNEP0bprYmacAUFV8WHDfg+wsyxDxxbC4C6oBl17qMbxHVbexq/ILL1pwUB1w2anbWbkpb97nrnlqcPB1ra8MumXFitE3K5ViIDX5T06VSJSGEYrNnRmmXMrqhHxWq4RAY1lXbpQJFJ4AN89nlUVSXrmetVwWlad9Q+k+uPtrWhm/tciSGmmtVzWoVbQC8fWQik9P7Z2O1bWAa/X2GRg9Lqsw7KrtgsJoJ1MGpB9dA6NEumfpl8XsHyF1l8XgMNKopgA3B5etHwYD4dV/FKo7tK4tXwYD6stfulDUtqrLiltD9U4vjUmi3p2lmua4u1x0bTdCBzaqR5ORVs5fzYDeuP1WRhe8PqCRr2+yrMhXTcjvyIrst73bdiKlN+bQ+6Z0XXOjtRbPH00JDO1c8GOpk3akVvijfT/+1gasNWVSW66Jsm9mL849evxFmYmLmqsSRLN7H8mUtSyP+uA7/8A</diagram></mxfile>
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,26 +1,136 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Mar 23 20:38:28 2021
+[*] Tue Sep 13 09:25:38 2022
 [*]
-[timestart] 0
+[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/build/tb_mips_top/tb_mips_top.ghw"
-[size] 1856 1136
+[dumpfile_mtime] "Tue Sep 13 05:37:30 2022"
-[pos] -51 -51
+[dumpfile_size] 284165098
-*-37.625370 355000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/MIPS/ghdl/tb_mips_top.gtkw"
-[treeopen] tb_mips_top.
+[timestart] 1624938400000
-[treeopen] tb_mips_top.inst_uart.
+[size] 1920 1163
-[sst_width] 233
+[pos] -1987 -28
-[signals_width] 288
+*-24.584558 1625004800000 1624975000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.tb_mips_top.
 [treeopen] top.tb_mips_top.uut.
 [treeopen] top.tb_mips_top.uut.inst_biu.inst_icache.
 [treeopen] top.tb_mips_top.uut.inst_cop.
 [treeopen] top.tb_mips_top.uut.inst_cop.ctrl_in.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.c0_ctrl_in.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.c0_ctrl_out.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.ex_stage.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.id_stage.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.mem_stage.
 [treeopen] top.tb_mips_top.uut.inst_pipeline.wb_stage.
 [sst_width] 358
 [signals_width] 296
 [sst_expanded] 1
-[sst_vpaned_height] 330
+[sst_vpaned_height] 667
@200
 -MIPS_R13
@28
-clk
+top.tb_mips_top.uut.cpu_clk
-rst
+top.tb_mips_top.uut.clk_i
 top.tb_mips_top.uut.stb_o
@22
-flash_a[16:0]
+#{top.tb_mips_top.uut.addr_o[31:0]} top.tb_mips_top.uut.addr_o[31] top.tb_mips_top.uut.addr_o[30] top.tb_mips_top.uut.addr_o[29] top.tb_mips_top.uut.addr_o[28] top.tb_mips_top.uut.addr_o[27] top.tb_mips_top.uut.addr_o[26] top.tb_mips_top.uut.addr_o[25] top.tb_mips_top.uut.addr_o[24] top.tb_mips_top.uut.addr_o[23] top.tb_mips_top.uut.addr_o[22] top.tb_mips_top.uut.addr_o[21] top.tb_mips_top.uut.addr_o[20] top.tb_mips_top.uut.addr_o[19] top.tb_mips_top.uut.addr_o[18] top.tb_mips_top.uut.addr_o[17] top.tb_mips_top.uut.addr_o[16] top.tb_mips_top.uut.addr_o[15] top.tb_mips_top.uut.addr_o[14] top.tb_mips_top.uut.addr_o[13] top.tb_mips_top.uut.addr_o[12] top.tb_mips_top.uut.addr_o[11] top.tb_mips_top.uut.addr_o[10] top.tb_mips_top.uut.addr_o[9] top.tb_mips_top.uut.addr_o[8] top.tb_mips_top.uut.addr_o[7] top.tb_mips_top.uut.addr_o[6] top.tb_mips_top.uut.addr_o[5] top.tb_mips_top.uut.addr_o[4] top.tb_mips_top.uut.addr_o[3] top.tb_mips_top.uut.addr_o[2] top.tb_mips_top.uut.addr_o[1] top.tb_mips_top.uut.addr_o[0]
-flash_d[31:0]
+#{top.tb_mips_top.uut.dat_o[31:0]} top.tb_mips_top.uut.dat_o[31] top.tb_mips_top.uut.dat_o[30] top.tb_mips_top.uut.dat_o[29] top.tb_mips_top.uut.dat_o[28] top.tb_mips_top.uut.dat_o[27] top.tb_mips_top.uut.dat_o[26] top.tb_mips_top.uut.dat_o[25] top.tb_mips_top.uut.dat_o[24] top.tb_mips_top.uut.dat_o[23] top.tb_mips_top.uut.dat_o[22] top.tb_mips_top.uut.dat_o[21] top.tb_mips_top.uut.dat_o[20] top.tb_mips_top.uut.dat_o[19] top.tb_mips_top.uut.dat_o[18] top.tb_mips_top.uut.dat_o[17] top.tb_mips_top.uut.dat_o[16] top.tb_mips_top.uut.dat_o[15] top.tb_mips_top.uut.dat_o[14] top.tb_mips_top.uut.dat_o[13] top.tb_mips_top.uut.dat_o[12] top.tb_mips_top.uut.dat_o[11] top.tb_mips_top.uut.dat_o[10] top.tb_mips_top.uut.dat_o[9] top.tb_mips_top.uut.dat_o[8] top.tb_mips_top.uut.dat_o[7] top.tb_mips_top.uut.dat_o[6] top.tb_mips_top.uut.dat_o[5] top.tb_mips_top.uut.dat_o[4] top.tb_mips_top.uut.dat_o[3] top.tb_mips_top.uut.dat_o[2] top.tb_mips_top.uut.dat_o[1] top.tb_mips_top.uut.dat_o[0]
-gpi_0[31:0]
+#{top.tb_mips_top.uut.dat_i[31:0]} top.tb_mips_top.uut.dat_i[31] top.tb_mips_top.uut.dat_i[30] top.tb_mips_top.uut.dat_i[29] top.tb_mips_top.uut.dat_i[28] top.tb_mips_top.uut.dat_i[27] top.tb_mips_top.uut.dat_i[26] top.tb_mips_top.uut.dat_i[25] top.tb_mips_top.uut.dat_i[24] top.tb_mips_top.uut.dat_i[23] top.tb_mips_top.uut.dat_i[22] top.tb_mips_top.uut.dat_i[21] top.tb_mips_top.uut.dat_i[20] top.tb_mips_top.uut.dat_i[19] top.tb_mips_top.uut.dat_i[18] top.tb_mips_top.uut.dat_i[17] top.tb_mips_top.uut.dat_i[16] top.tb_mips_top.uut.dat_i[15] top.tb_mips_top.uut.dat_i[14] top.tb_mips_top.uut.dat_i[13] top.tb_mips_top.uut.dat_i[12] top.tb_mips_top.uut.dat_i[11] top.tb_mips_top.uut.dat_i[10] top.tb_mips_top.uut.dat_i[9] top.tb_mips_top.uut.dat_i[8] top.tb_mips_top.uut.dat_i[7] top.tb_mips_top.uut.dat_i[6] top.tb_mips_top.uut.dat_i[5] top.tb_mips_top.uut.dat_i[4] top.tb_mips_top.uut.dat_i[3] top.tb_mips_top.uut.dat_i[2] top.tb_mips_top.uut.dat_i[1] top.tb_mips_top.uut.dat_i[0]
-gpo_0[31:0]
+@200
-@23
+-PC
-inst_uart.reg_uart_tx[7:0]
+@28
 top.tb_mips_top.uut.inst_pipeline.pc.branch_take
@22
 #{top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[31] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[30] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[29] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[28] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[27] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[26] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[25] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[24] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[23] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[22] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[21] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[20] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[19] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[18] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[17] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[16] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[15] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[14] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[13] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[12] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[11] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[10] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[9] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[8] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[7] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[6] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[5] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[4] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[3] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[2] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[1] top.tb_mips_top.uut.inst_pipeline.pc.pc_branch[0]
 #{top.tb_mips_top.uut.inst_pipeline.pc.nxt[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.nxt[31] top.tb_mips_top.uut.inst_pipeline.pc.nxt[30] top.tb_mips_top.uut.inst_pipeline.pc.nxt[29] top.tb_mips_top.uut.inst_pipeline.pc.nxt[28] top.tb_mips_top.uut.inst_pipeline.pc.nxt[27] top.tb_mips_top.uut.inst_pipeline.pc.nxt[26] top.tb_mips_top.uut.inst_pipeline.pc.nxt[25] top.tb_mips_top.uut.inst_pipeline.pc.nxt[24] top.tb_mips_top.uut.inst_pipeline.pc.nxt[23] top.tb_mips_top.uut.inst_pipeline.pc.nxt[22] top.tb_mips_top.uut.inst_pipeline.pc.nxt[21] top.tb_mips_top.uut.inst_pipeline.pc.nxt[20] top.tb_mips_top.uut.inst_pipeline.pc.nxt[19] top.tb_mips_top.uut.inst_pipeline.pc.nxt[18] top.tb_mips_top.uut.inst_pipeline.pc.nxt[17] top.tb_mips_top.uut.inst_pipeline.pc.nxt[16] top.tb_mips_top.uut.inst_pipeline.pc.nxt[15] top.tb_mips_top.uut.inst_pipeline.pc.nxt[14] top.tb_mips_top.uut.inst_pipeline.pc.nxt[13] top.tb_mips_top.uut.inst_pipeline.pc.nxt[12] top.tb_mips_top.uut.inst_pipeline.pc.nxt[11] top.tb_mips_top.uut.inst_pipeline.pc.nxt[10] top.tb_mips_top.uut.inst_pipeline.pc.nxt[9] top.tb_mips_top.uut.inst_pipeline.pc.nxt[8] top.tb_mips_top.uut.inst_pipeline.pc.nxt[7] top.tb_mips_top.uut.inst_pipeline.pc.nxt[6] top.tb_mips_top.uut.inst_pipeline.pc.nxt[5] top.tb_mips_top.uut.inst_pipeline.pc.nxt[4] top.tb_mips_top.uut.inst_pipeline.pc.nxt[3] top.tb_mips_top.uut.inst_pipeline.pc.nxt[2] top.tb_mips_top.uut.inst_pipeline.pc.nxt[1] top.tb_mips_top.uut.inst_pipeline.pc.nxt[0]
 #{top.tb_mips_top.uut.inst_pipeline.pc.last[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.last[31] top.tb_mips_top.uut.inst_pipeline.pc.last[30] top.tb_mips_top.uut.inst_pipeline.pc.last[29] top.tb_mips_top.uut.inst_pipeline.pc.last[28] top.tb_mips_top.uut.inst_pipeline.pc.last[27] top.tb_mips_top.uut.inst_pipeline.pc.last[26] top.tb_mips_top.uut.inst_pipeline.pc.last[25] top.tb_mips_top.uut.inst_pipeline.pc.last[24] top.tb_mips_top.uut.inst_pipeline.pc.last[23] top.tb_mips_top.uut.inst_pipeline.pc.last[22] top.tb_mips_top.uut.inst_pipeline.pc.last[21] top.tb_mips_top.uut.inst_pipeline.pc.last[20] top.tb_mips_top.uut.inst_pipeline.pc.last[19] top.tb_mips_top.uut.inst_pipeline.pc.last[18] top.tb_mips_top.uut.inst_pipeline.pc.last[17] top.tb_mips_top.uut.inst_pipeline.pc.last[16] top.tb_mips_top.uut.inst_pipeline.pc.last[15] top.tb_mips_top.uut.inst_pipeline.pc.last[14] top.tb_mips_top.uut.inst_pipeline.pc.last[13] top.tb_mips_top.uut.inst_pipeline.pc.last[12] top.tb_mips_top.uut.inst_pipeline.pc.last[11] top.tb_mips_top.uut.inst_pipeline.pc.last[10] top.tb_mips_top.uut.inst_pipeline.pc.last[9] top.tb_mips_top.uut.inst_pipeline.pc.last[8] top.tb_mips_top.uut.inst_pipeline.pc.last[7] top.tb_mips_top.uut.inst_pipeline.pc.last[6] top.tb_mips_top.uut.inst_pipeline.pc.last[5] top.tb_mips_top.uut.inst_pipeline.pc.last[4] top.tb_mips_top.uut.inst_pipeline.pc.last[3] top.tb_mips_top.uut.inst_pipeline.pc.last[2] top.tb_mips_top.uut.inst_pipeline.pc.last[1] top.tb_mips_top.uut.inst_pipeline.pc.last[0]
 #{top.tb_mips_top.uut.inst_pipeline.pc.curr[31:0]} top.tb_mips_top.uut.inst_pipeline.pc.curr[31] top.tb_mips_top.uut.inst_pipeline.pc.curr[30] top.tb_mips_top.uut.inst_pipeline.pc.curr[29] top.tb_mips_top.uut.inst_pipeline.pc.curr[28] top.tb_mips_top.uut.inst_pipeline.pc.curr[27] top.tb_mips_top.uut.inst_pipeline.pc.curr[26] top.tb_mips_top.uut.inst_pipeline.pc.curr[25] top.tb_mips_top.uut.inst_pipeline.pc.curr[24] top.tb_mips_top.uut.inst_pipeline.pc.curr[23] top.tb_mips_top.uut.inst_pipeline.pc.curr[22] top.tb_mips_top.uut.inst_pipeline.pc.curr[21] top.tb_mips_top.uut.inst_pipeline.pc.curr[20] top.tb_mips_top.uut.inst_pipeline.pc.curr[19] top.tb_mips_top.uut.inst_pipeline.pc.curr[18] top.tb_mips_top.uut.inst_pipeline.pc.curr[17] top.tb_mips_top.uut.inst_pipeline.pc.curr[16] top.tb_mips_top.uut.inst_pipeline.pc.curr[15] top.tb_mips_top.uut.inst_pipeline.pc.curr[14] top.tb_mips_top.uut.inst_pipeline.pc.curr[13] top.tb_mips_top.uut.inst_pipeline.pc.curr[12] top.tb_mips_top.uut.inst_pipeline.pc.curr[11] top.tb_mips_top.uut.inst_pipeline.pc.curr[10] top.tb_mips_top.uut.inst_pipeline.pc.curr[9] top.tb_mips_top.uut.inst_pipeline.pc.curr[8] top.tb_mips_top.uut.inst_pipeline.pc.curr[7] top.tb_mips_top.uut.inst_pipeline.pc.curr[6] top.tb_mips_top.uut.inst_pipeline.pc.curr[5] top.tb_mips_top.uut.inst_pipeline.pc.curr[4] top.tb_mips_top.uut.inst_pipeline.pc.curr[3] top.tb_mips_top.uut.inst_pipeline.pc.curr[2] top.tb_mips_top.uut.inst_pipeline.pc.curr[1] top.tb_mips_top.uut.inst_pipeline.pc.curr[0]
@200
 -REG
@22
 #{top.tb_mips_top.uut.inst_pipeline.reg_a[31:0]} top.tb_mips_top.uut.inst_pipeline.reg_a[31] top.tb_mips_top.uut.inst_pipeline.reg_a[30] top.tb_mips_top.uut.inst_pipeline.reg_a[29] top.tb_mips_top.uut.inst_pipeline.reg_a[28] top.tb_mips_top.uut.inst_pipeline.reg_a[27] top.tb_mips_top.uut.inst_pipeline.reg_a[26] top.tb_mips_top.uut.inst_pipeline.reg_a[25] top.tb_mips_top.uut.inst_pipeline.reg_a[24] top.tb_mips_top.uut.inst_pipeline.reg_a[23] top.tb_mips_top.uut.inst_pipeline.reg_a[22] top.tb_mips_top.uut.inst_pipeline.reg_a[21] top.tb_mips_top.uut.inst_pipeline.reg_a[20] top.tb_mips_top.uut.inst_pipeline.reg_a[19] top.tb_mips_top.uut.inst_pipeline.reg_a[18] top.tb_mips_top.uut.inst_pipeline.reg_a[17] top.tb_mips_top.uut.inst_pipeline.reg_a[16] top.tb_mips_top.uut.inst_pipeline.reg_a[15] top.tb_mips_top.uut.inst_pipeline.reg_a[14] top.tb_mips_top.uut.inst_pipeline.reg_a[13] top.tb_mips_top.uut.inst_pipeline.reg_a[12] top.tb_mips_top.uut.inst_pipeline.reg_a[11] top.tb_mips_top.uut.inst_pipeline.reg_a[10] top.tb_mips_top.uut.inst_pipeline.reg_a[9] top.tb_mips_top.uut.inst_pipeline.reg_a[8] top.tb_mips_top.uut.inst_pipeline.reg_a[7] top.tb_mips_top.uut.inst_pipeline.reg_a[6] top.tb_mips_top.uut.inst_pipeline.reg_a[5] top.tb_mips_top.uut.inst_pipeline.reg_a[4] top.tb_mips_top.uut.inst_pipeline.reg_a[3] top.tb_mips_top.uut.inst_pipeline.reg_a[2] top.tb_mips_top.uut.inst_pipeline.reg_a[1] top.tb_mips_top.uut.inst_pipeline.reg_a[0]
 #{top.tb_mips_top.uut.inst_pipeline.reg_b[31:0]} top.tb_mips_top.uut.inst_pipeline.reg_b[31] top.tb_mips_top.uut.inst_pipeline.reg_b[30] top.tb_mips_top.uut.inst_pipeline.reg_b[29] top.tb_mips_top.uut.inst_pipeline.reg_b[28] top.tb_mips_top.uut.inst_pipeline.reg_b[27] top.tb_mips_top.uut.inst_pipeline.reg_b[26] top.tb_mips_top.uut.inst_pipeline.reg_b[25] top.tb_mips_top.uut.inst_pipeline.reg_b[24] top.tb_mips_top.uut.inst_pipeline.reg_b[23] top.tb_mips_top.uut.inst_pipeline.reg_b[22] top.tb_mips_top.uut.inst_pipeline.reg_b[21] top.tb_mips_top.uut.inst_pipeline.reg_b[20] top.tb_mips_top.uut.inst_pipeline.reg_b[19] top.tb_mips_top.uut.inst_pipeline.reg_b[18] top.tb_mips_top.uut.inst_pipeline.reg_b[17] top.tb_mips_top.uut.inst_pipeline.reg_b[16] top.tb_mips_top.uut.inst_pipeline.reg_b[15] top.tb_mips_top.uut.inst_pipeline.reg_b[14] top.tb_mips_top.uut.inst_pipeline.reg_b[13] top.tb_mips_top.uut.inst_pipeline.reg_b[12] top.tb_mips_top.uut.inst_pipeline.reg_b[11] top.tb_mips_top.uut.inst_pipeline.reg_b[10] top.tb_mips_top.uut.inst_pipeline.reg_b[9] top.tb_mips_top.uut.inst_pipeline.reg_b[8] top.tb_mips_top.uut.inst_pipeline.reg_b[7] top.tb_mips_top.uut.inst_pipeline.reg_b[6] top.tb_mips_top.uut.inst_pipeline.reg_b[5] top.tb_mips_top.uut.inst_pipeline.reg_b[4] top.tb_mips_top.uut.inst_pipeline.reg_b[3] top.tb_mips_top.uut.inst_pipeline.reg_b[2] top.tb_mips_top.uut.inst_pipeline.reg_b[1] top.tb_mips_top.uut.inst_pipeline.reg_b[0]
@200
 -ID
@22
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[0]
@28
 top.tb_mips_top.uut.inst_pipeline.id_stage.nop
@420
 top.tb_mips_top.uut.inst_pipeline.id_stage.op
@28
 top.tb_mips_top.uut.inst_pipeline.id_stage.exc
 top.tb_mips_top.uut.inst_pipeline.sdu.dmem_dep
 top.tb_mips_top.uut.inst_pipeline.sdu.imem_dep
@22
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.ir[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.ir[31] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[30] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[29] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[28] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[27] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[26] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[25] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[24] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[23] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[22] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[21] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[20] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[19] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[18] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[17] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[16] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[15] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[14] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[13] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[12] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[11] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[10] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[9] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[8] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[7] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[6] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[5] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[4] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[3] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[2] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[1] top.tb_mips_top.uut.inst_pipeline.id_stage.ir[0]
@28
 top.tb_mips_top.uut.inst_pipeline.id_stage.reg_write
@22
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[31] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[30] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[29] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[28] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[27] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[26] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[25] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[24] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[23] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[22] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[21] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[20] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[19] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[18] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[17] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[16] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[15] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[14] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[13] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[12] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[11] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[10] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[9] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[8] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[7] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[6] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[5] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[4] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[3] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[2] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[1] top.tb_mips_top.uut.inst_pipeline.id_stage.pcn[0]
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.id_stage.epc[0]
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[4:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a_rptr[0]
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[31] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[30] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[29] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[28] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[27] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[26] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[25] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[24] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[23] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[22] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[21] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[20] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[19] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[18] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[17] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[16] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[15] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[14] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[13] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[12] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[11] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[10] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[9] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[8] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[7] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[6] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[5] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_a[0]
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[4:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b_rptr[0]
 #{top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[31:0]} top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[31] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[30] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[29] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[28] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[27] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[26] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[25] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[24] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[23] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[22] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[21] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[20] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[19] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[18] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[17] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[16] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[15] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[14] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[13] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[12] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[11] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[10] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[9] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[8] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[7] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[6] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[5] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[4] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[3] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[2] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[1] top.tb_mips_top.uut.inst_pipeline.id_stage.reg_b[0]
@200
 -EX
@22
 #{top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.ex_stage.epc[0]
@28
 top.tb_mips_top.uut.inst_pipeline.ex_stage.nop
@420
 top.tb_mips_top.uut.inst_pipeline.ex_stage.op
@28
 top.tb_mips_top.uut.inst_pipeline.ex_stage.exc
 top.tb_mips_top.uut.inst_pipeline.ex_stage.reg_write
 top.tb_mips_top.uut.inst_pipeline.ex_stage.wreg_we
@200
 -MEM
@22
 #{top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[31:0]} top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[31] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[30] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[29] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[28] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[27] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[26] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[25] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[24] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[23] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[22] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[21] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[20] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[19] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[18] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[17] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[16] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[15] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[14] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[13] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[12] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[11] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[10] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[9] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[8] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[7] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[6] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[5] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[4] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[3] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[2] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[1] top.tb_mips_top.uut.inst_pipeline.mem_stage.epc[0]
@28
 top.tb_mips_top.uut.inst_pipeline.mem_stage.nop
@420
 top.tb_mips_top.uut.inst_pipeline.mem_stage.op
@28
 top.tb_mips_top.uut.inst_pipeline.mem_stage.exc
 top.tb_mips_top.uut.inst_pipeline.mem_stage.events.int
@200
 -WB
@28
 top.tb_mips_top.uut.inst_pipeline.wb_stage.nop
@420
 top.tb_mips_top.uut.inst_pipeline.wb_stage.op
@28
 top.tb_mips_top.uut.inst_pipeline.wb_stage.exc
 top.tb_mips_top.uut.inst_pipeline.wb_stage.events.int
 top.tb_mips_top.uut.inst_pipeline.wb_stage.bd
 top.tb_mips_top.uut.inst_pipeline.wb_stage.events.int
@200
 -COP
@421
 top.tb_mips_top.uut.inst_cop.exc_state
@22
 #{top.tb_mips_top.uut.inst_cop.epc[31:0]} top.tb_mips_top.uut.inst_cop.epc[31] top.tb_mips_top.uut.inst_cop.epc[30] top.tb_mips_top.uut.inst_cop.epc[29] top.tb_mips_top.uut.inst_cop.epc[28] top.tb_mips_top.uut.inst_cop.epc[27] top.tb_mips_top.uut.inst_cop.epc[26] top.tb_mips_top.uut.inst_cop.epc[25] top.tb_mips_top.uut.inst_cop.epc[24] top.tb_mips_top.uut.inst_cop.epc[23] top.tb_mips_top.uut.inst_cop.epc[22] top.tb_mips_top.uut.inst_cop.epc[21] top.tb_mips_top.uut.inst_cop.epc[20] top.tb_mips_top.uut.inst_cop.epc[19] top.tb_mips_top.uut.inst_cop.epc[18] top.tb_mips_top.uut.inst_cop.epc[17] top.tb_mips_top.uut.inst_cop.epc[16] top.tb_mips_top.uut.inst_cop.epc[15] top.tb_mips_top.uut.inst_cop.epc[14] top.tb_mips_top.uut.inst_cop.epc[13] top.tb_mips_top.uut.inst_cop.epc[12] top.tb_mips_top.uut.inst_cop.epc[11] top.tb_mips_top.uut.inst_cop.epc[10] top.tb_mips_top.uut.inst_cop.epc[9] top.tb_mips_top.uut.inst_cop.epc[8] top.tb_mips_top.uut.inst_cop.epc[7] top.tb_mips_top.uut.inst_cop.epc[6] top.tb_mips_top.uut.inst_cop.epc[5] top.tb_mips_top.uut.inst_cop.epc[4] top.tb_mips_top.uut.inst_cop.epc[3] top.tb_mips_top.uut.inst_cop.epc[2] top.tb_mips_top.uut.inst_cop.epc[1] top.tb_mips_top.uut.inst_cop.epc[0]
 #{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
 #{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_wb[0]
@200
 -I-Cache
@420
 top.tb_mips_top.uut.inst_biu.inst_icache.s
@22
 #{top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[31:0]} top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[31] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[30] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[29] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[28] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[27] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[26] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[25] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[24] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[23] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[22] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[21] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[20] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[19] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[18] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[17] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[16] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[15] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[14] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[13] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[12] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[11] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[10] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[9] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[8] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[7] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[6] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[5] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[4] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[3] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[2] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[1] top.tb_mips_top.uut.inst_biu.inst_icache.cpu_addr[0]
@28
 top.tb_mips_top.uut.inst_biu.inst_icache.cpu_busy
 top.tb_mips_top.uut.inst_biu.inst_icache.cpu_en
 top.tb_mips_top.uut.inst_biu.inst_icache.tag_match
 top.tb_mips_top.uut.inst_biu.inst_icache.cache_hit
 top.tb_mips_top.uut.inst_biu.inst_icache.cache_busy
 top.tb_mips_top.uut.inst_biu.inst_icache.cache_ack
 top.tb_mips_top.uut.inst_biu.inst_icache.cache_req
@22
 #{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
 #{top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31:0]} top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[31] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[30] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[29] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[28] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[27] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[26] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[25] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[24] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[23] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[22] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[21] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[20] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[19] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[18] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[17] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[16] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[15] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[14] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[13] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[12] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[11] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[10] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[9] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[8] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[7] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[6] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[5] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[4] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[3] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[2] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[1] top.tb_mips_top.uut.inst_cop.ctrl_in.epc_mem[0]
 [pattern_trace] 1
 [pattern_trace] 0
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include mips_core.inc
@@ -32,7 +32,8 @@ SRCS += ../src/tb_mips_top.vhd
 # Compile
 TARGET := tb_mips_top
 ENTITY := tb_mips_top
-RUN_TIME ?= 1500us
+RUN_TIME ?= 250us
 WAVE_FORMAT ?= ghw
 include $(VHDL_MAKE_HOME)/ghdl.mk
@@ -585,6 +585,9 @@ package body mips_types is
 		elsif word2_en = '1' then
 			sign	:= signed and x(15);
 			result := (31 downto 16 => sign) & x(15 downto 0);
 		elsif word4_en = '1' then
 			sign	:= signed and x(7);
 			result := (31 downto 8 => sign) & x(7 downto 0);
 		else
 			sign	:= signed and x(7);
 			result := (31 downto 8 => sign) & x(7 downto 0);
@@ -33,6 +33,11 @@ use work.async_types.all;
 use work.async_defs.all;
 ENTITY tb_mips_top IS
 	Generic
 	(
 		app	: string := "apps/hello.elf.flash.bin"
 	);
 END tb_mips_top;
 ARCHITECTURE behavior OF tb_mips_top IS 
@@ -113,8 +118,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	signal mem_area : mem_area_t;
 	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
-	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
+	signal sram_memory_content : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
-	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
+	signal flash_memory_content : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
 BEGIN
@@ -356,16 +361,16 @@ SRAM_READ:
 		if sram_oe_n = '0' then
 			if sram_cs_n = '0' then
 				if sram_be_n(0) = '0' then
-					sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
+					sram_d(7 downto 0) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
 				end if;	
 				if sram_be_n(1) = '0' then
-					sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
+					sram_d(15 downto 8) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
 				end if;	
 				if sram_be_n(2) = '0' then
-					sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
+					sram_d(23 downto 16) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
 				end if;	
 				if sram_be_n(3) = '0' then
-					sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
+					sram_d(31 downto 24) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
 				end if;	
 			end if;				
 		end if;	
@@ -377,16 +382,16 @@ SRAM_WRITE:
 		if rising_edge(sram_wr_n) then
 			if sram_cs_n = '0' then
 				if sram_be_n(0) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
 				end if;		
 				if sram_be_n(1) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
 				end if;				
 				if sram_be_n(2) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
 				end if;				
 				if sram_be_n(3) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
+					sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
 				end if;				
 			end if;	
 		end if;	
@@ -396,7 +401,7 @@ SRAM_WRITE:
 FLASH_READ:
 	process(rst, flash_cs_n, flash_oe_n, flash_a)
 	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "hello.elf.flash.bin";
+	file load_flash : file_t open read_mode is app;
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);
@@ -407,7 +412,7 @@ FLASH_READ:
 			while not endfile(load_flash) loop
 				read(load_flash, instr);
 				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
+				flash_memory_content(index) <= unsigned(temp);
 				index := index + 1;
 			end loop;
 		else
@@ -416,16 +421,16 @@ FLASH_READ:
 			if flash_oe_n = '0' then
 				if flash_cs_n = '0' then
 					if flash_be_n(0) = '0' then
-						flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
+						flash_d(7 downto 0) <= flash_memory_content(index)(7 downto 0) after tpd;
 					end if;	
 					if flash_be_n(1) = '0' then
-						flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
+						flash_d(15 downto 8) <= flash_memory_content(index)(15 downto 8) after tpd;
 					end if;	
 					if flash_be_n(2) = '0' then
-						flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
+						flash_d(23 downto 16) <= flash_memory_content(index)(23 downto 16) after tpd;
 					end if;	
 					if flash_be_n(3) = '0' then
-						flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
+						flash_d(31 downto 24) <= flash_memory_content(index)(31 downto 24) after tpd;
 					end if;	
 				end if;				
 			end if;	
@@ -1,3 +1,4 @@
 include $(VHDL_HOME)/defs.mk
 PRJDIR := ./project
 PRJ := mips_top
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIFO_ASYNC
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIFO_SYNC
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fifo_async.inc
 ROOT_PATH := ../../..
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fifo_sync.inc
 ROOT_PATH := ../../..
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd
 SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd
 SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
 # -----------------------------------------------------------
 PKG_NAME := BUSMASTER_ASYNC
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 # -----------------------------------------------------------
 PKG_NAME := BUSMASTER_SYNC
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/JBUS/busmaster/ghdl/busmaster_async.inc
 SRCS += $(BUSMASTER_ASYNC_SRCS)
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/JBUS/busmaster/ghdl/busmaster_sync.inc
 SRCS += $(BUSMASTER_SYNC_SRCS)
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 MOD_PATH := $(LIB_PATH)/JBUS
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include vga_frontend_jb32.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include vga_frontend_jb64.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := VGA_BACKEND
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include vga_backend.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/emac/ghdl/emac_tx.inc
 include $(LIB_PATH)/emac/ghdl/emac_rx.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include emac_jbus.inc
 SRCS := $(EMAC_JBUS_SRCS)
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIR_ITERATIVE
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIR_PARALLEL
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := FIR_SEMI_PARALLEL
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fir_iterative.inc
 ROOT_PATH := ../../..
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fir_parallel.inc
 ROOT_PATH := ../../..
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include fir_semi_parallel.inc
 ROOT_PATH := ../../..
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
 SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
 SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 MOD_PATH := $(VHDL_HOME)/lib/ps2_port
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := CORDIC_ITERATIVE
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := CORDIC_PIPE
@@ -1,5 +1,5 @@
 # -------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include cordic_iterative.inc
 # -------------------------------------------------
@@ -1,5 +1,5 @@
 # -------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include cordic_pipe.inc
 # -------------------------------------------------
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/filter/ghdl/fir_semi_parallel.inc
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
 include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := CIC_DECIM_PIPE
@@ -1,4 +1,4 @@
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include cic_decim_pipe.inc
 SRCS += $(CIC_DECIM_PIPE_SRCS)
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/radio/cordic/ghdl/cordic_pipe.inc
 # -----------------------------------------------------------
 PKG_NAME := MIX_CORDIC_PIPE
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := NCO_LUT
@@ -1,5 +1,5 @@
 # -------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc
 # -------------------------------------------------
@@ -1,5 +1,5 @@
 # -------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc
 # -------------------------------------------------
@@ -1,5 +1,5 @@
 # -------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 include $(LIB_PATH)/radio/nco/ghdl/nco_lut.inc
 # -------------------------------------------------
@@ -49,18 +49,18 @@ end dpram_1w1r1c_ra;
 architecture Behavioral of dpram_1w1r1c_ra is
-TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
+TYPE memory_type IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
-SIGNAL ram_block: MEM;
+SIGNAL memory_content: memory_type;
 BEGIN
 	PROCESS (clk)
 	BEGIN
 	IF (clk'event AND clk = '1') THEN
 		IF (we_a = '1') THEN
-			ram_block(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		END IF;
 		IF (re_b = '1') THEN
-			dout_b <= ram_block(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		END IF;
 		-- VHDL semantics imply that q doesn't get data
 		-- in this clock cycle
@@ -50,10 +50,10 @@ architecture Behavioral of dpram_1w1r2c_ra is
 	-- Build a 2-D array type for the RAM
 	subtype word_t is unsigned((data_width-1) downto 0);
-	type memory_t is array(2**addr_width-1 downto 0) of word_t;
+	type memory_type is array(2**addr_width-1 downto 0) of word_t;
 	-- Declare the RAM signal.	
-	signal ram : memory_t;
+	signal memory_content : memory_type;
 begin
@@ -61,7 +61,7 @@ begin
 	begin
 	if(rising_edge(clk_a)) then 
 		if(we_a = '1') then
-			ram(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		end if;
 	end if;
 	end process;
@@ -70,7 +70,7 @@ begin
 	begin
 	if(rising_edge(clk_b)) then 
 		if(re_b = '1') then
-			dout_b <= ram(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		end if;
 	end if;
 	end process;
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
 architecture Behavioral of dpram_1w1r2c_ro is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 begin
@@ -59,7 +59,7 @@ process (clk_a)
 	begin
 	if clk_a'event and clk_a = '1' then
 		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		end if;
 	end if;
 end process;
@@ -68,7 +68,7 @@ process (clk_b)
 	begin
 	if clk_b'event and clk_b = '1' then
 		if re_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		end if;
 	end if;
 end process;
@@ -55,8 +55,8 @@ architecture Behavioral of dpram_2w2r2c_ra is
 	constant depth : integer := 2**addr_width;
 	subtype word_t is unsigned (data_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of word_t;
+	type memory_type is array (0 to depth-1) of word_t;
-	shared variable RAM : RAMtype;
+	shared variable memory_content : memory_type;
 begin
@@ -64,10 +64,10 @@ process (clk_a)
 begin
 if rising_edge(clk_a) then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) := din_a;
+		memory_content(to_integer(addr_a)) := din_a;
 	end if;
 	if re_a = '1' then
-		dout_a <= RAM(to_integer(addr_a));
+		dout_a <= memory_content(to_integer(addr_a));
 	end if;
 end if;
 end process;
@@ -77,10 +77,10 @@ process (clk_b)
 begin
 if rising_edge(clk_b) then
 	if we_b = '1' then
-		RAM(to_integer(addr_b)) := din_b;
+		memory_content(to_integer(addr_b)) := din_b;
 	end if;
 	if re_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
+		dout_b <= memory_content(to_integer(addr_b));
 	end if;
 end if;
 end process;
@@ -49,18 +49,18 @@ end dpram_1w1r1c_ra;
 architecture Behavioral of dpram_1w1r1c_ra is
-TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
+TYPE memory_type IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
-SIGNAL ram_block: MEM;
+SIGNAL memory_content: memory_type;
 BEGIN
 	PROCESS (clk)
 	BEGIN
 	IF (clk'event AND clk = '1') THEN
 		IF (we_a = '1') THEN
-			ram_block(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		END IF;
 		IF (re_b = '1') THEN
-			dout_b <= ram_block(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		END IF;
 		-- VHDL semantics imply that q doesn't get data
 		-- in this clock cycle
@@ -48,19 +48,19 @@ end dpram_1w1r2c_ra;
 architecture Behavioral of dpram_1w1r2c_ra is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 	signal addr_b_r : unsigned (addr_width-1 downto 0);
 begin
-	dout_b <= RAM(to_integer(addr_b_r));
+	dout_b <= memory_content(to_integer(addr_b_r));
 process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
+		memory_content(to_integer(addr_a)) <= din_a;
 	end if;
 end if;
 end process;
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
 architecture Behavioral of dpram_1w1r2c_ro is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 begin
@@ -59,7 +59,7 @@ process (clk_a)
 	begin
 	if clk_a'event and clk_a = '1' then
 		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		end if;
 	end if;
 end process;
@@ -68,7 +68,7 @@ process (clk_b)
 	begin
 	if clk_b'event and clk_b = '1' then
 		if re_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		end if;
 	end if;
 end process;
@@ -56,20 +56,20 @@ architecture Behavioral of dpram_2w2r2c_ra is
 	constant depth : integer := 2**addr_width;
 	signal addr_a_r : unsigned (addr_width-1 downto 0);
 	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 begin
-	dout_a <= RAM(to_integer(addr_a_r));
+	dout_a <= memory_content(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
+	dout_b <= memory_content(to_integer(addr_b_r));
 process (clk_a, clk_b)
 begin
 	if clk_a'event and clk_a = '1' and we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
+		memory_content(to_integer(addr_a)) <= din_a;
 	elsif clk_b'event and clk_b = '1' and we_b = '1' then
-		RAM(to_integer(addr_b)) <= din_b;
+		memory_content(to_integer(addr_b)) <= din_b;
 	end if;
 end process;
@@ -54,8 +54,8 @@ end dpram_2w2r2c_ro;
 architecture Behavioral of dpram_2w2r2c_ro is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
+	shared variable memory_content : memory_type;
 begin
@@ -63,10 +63,10 @@ process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) := din_a;
+		memory_content(to_integer(addr_a)) := din_a;
 	end if;
 	if re_a = '1' then
-		dout_a <= RAM(to_integer(addr_a));
+		dout_a <= memory_content(to_integer(addr_a));
 	end if;
 end if;
 end process;
@@ -75,10 +75,10 @@ process (clk_b)
 begin
 if clk_b'event and clk_b = '1' then
 	if we_b = '1' then
-		RAM(to_integer(addr_b)) := din_b;
+		memory_content(to_integer(addr_b)) := din_b;
 	end if;
 	if re_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
+		dout_b <= memory_content(to_integer(addr_b));
 	end if;
 end if;
 end process;
@@ -48,19 +48,19 @@ end dpram_1w1r2c_ra;
 architecture Behavioral of dpram_1w1r2c_ra is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 	signal addr_b_r : unsigned (addr_width-1 downto 0);
 begin
-	dout_b <= RAM(to_integer(addr_b_r));
+	dout_b <= memory_content(to_integer(addr_b_r));
 process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
+		memory_content(to_integer(addr_a)) <= din_a;
 	end if;
 end if;
 end process;
@@ -50,8 +50,8 @@ end dpram_1w1r2c_ro;
 architecture Behavioral of dpram_1w1r2c_ro is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	signal memory_content : memory_type;
 begin
@@ -59,7 +59,7 @@ process (clk_a)
 	begin
 	if clk_a'event and clk_a = '1' then
 		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
+			memory_content(to_integer(addr_a)) <= din_a;
 		end if;
 	end if;
 end process;
@@ -68,7 +68,7 @@ process (clk_b)
 	begin
 	if clk_b'event and clk_b = '1' then
 		if re_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
+			dout_b <= memory_content(to_integer(addr_b));
 		end if;
 	end if;
 end process;
@@ -56,19 +56,19 @@ architecture Behavioral of dpram_2w2r2c_ra is
 	constant depth : integer := 2**addr_width;
 	signal addr_a_r : unsigned (addr_width-1 downto 0);
 	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
+	shared variable memory_content : memory_type;
 begin
-	dout_a <= RAM(to_integer(addr_a_r));
+	dout_a <= memory_content(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
+	dout_b <= memory_content(to_integer(addr_b_r));
 process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) := din_a;
+		memory_content(to_integer(addr_a)) := din_a;
 	end if;
 --	if re_a = '1' then
 		addr_a_r	<= addr_a;
@@ -81,7 +81,7 @@ process (clk_b)
 begin
 if clk_b'event and clk_b = '1' then
 	if we_b = '1' then
-		RAM(to_integer(addr_b)) := din_b;
+		memory_content(to_integer(addr_b)) := din_b;
 	end if;
 --	if re_b = '1' then
 		addr_b_r	<= addr_b;
@@ -54,8 +54,8 @@ end dpram_2w2r2c_ro;
 architecture Behavioral of dpram_2w2r2c_ro is
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
+	shared variable memory_content : memory_type;
 begin
@@ -63,10 +63,10 @@ process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) := din_a;
+		memory_content(to_integer(addr_a)) := din_a;
 	end if;
 	if re_a = '1' then
-		dout_a <= RAM(to_integer(addr_a));
+		dout_a <= memory_content(to_integer(addr_a));
 	end if;
 end if;
 end process;
@@ -75,10 +75,10 @@ process (clk_b)
 begin
 if clk_b'event and clk_b = '1' then
 	if we_b = '1' then
-		RAM(to_integer(addr_b)) := din_b;
+		memory_content(to_integer(addr_b)) := din_b;
 	end if;
 	if re_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
+		dout_b <= memory_content(to_integer(addr_b));
 	end if;
 end if;
 end process;
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(VHDL_HOME)/lib/uart/ghdl/uart_generic.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := UART_GENERIC
@@ -1,5 +1,5 @@
 # -----------------------------------------------------------
-include $(VHDL_MAKE_HOME)/defs.mk
+include $(VHDL_HOME)/defs.mk
 # -----------------------------------------------------------
 PKG_NAME := UART_SIM
@@ -81,7 +81,7 @@ set_global_assignment -name DEVICE EP4CE22F17C6
 set_global_assignment -name TOP_LEVEL_ENTITY mips_sys
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:21:44  MAY 14, 2015"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -320,4 +320,5 @@ set_location_assignment PIN_R8 -to clk_brd
 set_location_assignment PIN_J15 -to rst_brd_n
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_brd
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_brd_n
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
jens	4d94de761b	commit stale changes	2026-07-26 21:29:38 +02:00
jens	13513060ce	added Mips Basic Pipe	2024-06-14 17:40:04 +02:00
jens	5277a86a38	- changed gtkw	2023-03-10 20:47:13 +01:00
jens	f8a1b31a04	include defs.mk	2022-09-18 08:22:23 +02:00
jens	d811f79d76	Improved GTKW	2022-09-12 23:25:51 +02:00
jens	777fb14cef	- use ghw - updated .gitignore.templ	2022-09-12 23:22:03 +02:00
jens	d9609c9c86	- updated tb_mips_top.gtkw	2022-09-10 14:14:43 +02:00
jens	aef8406ae8	Improved templ	2022-09-10 10:40:58 +02:00
jens	c2ce21f67c	Improved templ	2022-09-10 10:35:01 +02:00
jens	103e04d35f	Improved templ	2022-09-10 10:16:18 +02:00
jens	e75e17f72e	- organize apps in separate folder	2022-09-10 08:32:25 +02:00
jens	63edf40cdc	Updated sim apps	2022-09-10 08:26:00 +02:00
jens	1f52aee5d9	Pass EXTRA_OPTS to GHDL	2022-09-10 08:25:14 +02:00
jens	cac6fc9540	- made WAE_FORMAT and RUN_TIME settable from caller	2022-09-10 06:55:34 +02:00
jens	cf6a2905a2	- fixed Make path	2022-09-09 19:52:47 +02:00
jens	e7f8b05383	Short test	2022-09-09 15:34:34 +02:00
jens	c80258eefe	- fixed problems	2022-09-09 15:29:25 +02:00
jens	11c980bc09	- run for 2.5ms - updated gtkw	2022-09-08 16:06:49 +02:00
jens	b8c4d9699a	Updated bootloader.dis	2022-09-08 12:11:03 +02:00
jens	ff11b70169	Updated tb_mips_top.wopt.templ	2022-09-08 11:29:02 +02:00
jens	ae6738c0bd	Unified RAM memory content signals	2022-09-08 11:27:10 +02:00
jens	1966db95f1	Added genwopt target	2022-09-08 10:47:09 +02:00
jens	ec06838c3e	Use genwopt	2022-09-08 10:46:03 +02:00
jens	96280bb78a	Reafctored defs.mk	2022-09-08 09:10:32 +02:00
		`@@ -0,0 +1,2 @@`
							`LIB_PATH := $(VHDL_HOME)/lib`
							`VHDL_MAKE_HOME := $(VHDL_HOME)/Common/make`
		`@@ -0,0 +1 @@`
							<mxfile host="app.diagrams.net" modified="2022-09-11T17:00:05.394Z" agent="5.0 (X11)" etag="ULt_GwP94m2c2vBAbY-Z" version="20.3.0" type="device"><diagram id="XI_-d3d4CUWLWsZJCx82" name="Seite-1">7VxNj9owEP01HLsidkLCcZfttmpVqRKHtqcqIl6w1sTImAL99XWITWIbmizN1ya9IDzEjjPvjT0znjCCs/XhAws3qy80QmQExtFhBB9HAEyhJz4TwTEVeME0FSwZjlKRkwnm+DeSwrGU7nCEttqFnFLC8UYXLmgcowXXZCFjdK9f9kyJftdNuESWYL4IiS39hiO+SqUB8DP5R4SXK3VnZyKfbx2qi+WTbFdhRPc5EXw/gjNGKU+/rQ8zRBLdKb2k/Z6u/HqeGEMxL9PhZffpeYp/ftzsHZ89LcE8+EzeyVF+hWQnH1hOlh+VBhjdxRFKBhmP4MN+hTmab8JF8uteQC5kK74mouWIr3I4xDg6XJ2nc356wRpE14izo7hEdXCkBiVjHKXAfaZ/V4pWedVPpDCUkC/PQ2daEV+kYl6hJLd7SoKdU5JfrCQxijBb0XgQtrBJhAtCd1EjCgOmwlyvlMJgXfoKSugrju6TJeykqHC7xQtdLTrphCLY8XvSuPMcXwl+nASO6yrB4yF//eMx3/qKGBZPh5gUpjNCkbVEGloXa3LIlogX0cNGJ6d974L2lYwhEnL8S5/GJUjkHb5SLCaYgQ918AMD1C3dsQWSnfJLqDEOnOjjWOxI1WANdCLI+alv58y0Ps7ofAFeEV0OmKdcC3xPttOuqpV1TBr5frezLMWpeBEqZKPbKht9g0XurXQExpo2bZaOykerZQ1zJjolvbKUdDQ6ggI+/tuyV0jIt7E8TlydR35VhDQHqpuQtjs754mDD8ZiIuMZZ8QiqHApuE7JLWf0Bc0ooQkhYhonHsszJsQQhQQv44TXghUJdx4SBwWL0OFe/rDGUZTc5qJ7oxO/Cg9nrCvfsz3CSZMOjgNKgDHGcX8RcTzDHGDbkMAh20fn0CgRV+a2T6nVq3tn2V2rrV3GjOtv9sIdw5sHZkxb9y7jDQu3InWXxs0rIEDduE0GhZuZIro96m3b3sqklnqEW1X2Btu2txpTXHps6BfFhmUxLxGptcqNqjIHjhErnOfXFDXsTJZwRE/9xhZHeuOBmvaoNqS2HFB1ZvCGDPTt5+zMXdkcqGbLAxdTJKd+jgV+byyve6ZnJ0f+ZnpFPs1WsIari6kYVMmeMNEP0bprYmacAUFV8WHDfg+wsyxDxxbC4C6oBl17qMbxHVbexq/ILL1pwUB1w2anbWbkpb97nrnlqcPB1ra8MumXFitE3K5ViIDX5T06VSJSGEYrNnRmmXMrqhHxWq4RAY1lXbpQJFJ4AN89nlUVSXrmetVwWlad9Q+k+uPtrWhm/tciSGmmtVzWoVbQC8fWQik9P7Z2O1bWAa/X2GRg9Lqsw7KrtgsJoJ1MGpB9dA6NEumfpl8XsHyF1l8XgMNKopgA3B5etHwYD4dV/FKo7tK4tXwYD6stfulDUtqrLiltD9U4vjUmi3p2lmua4u1x0bTdCBzaqR5ORVs5fzYDeuP1WRhe8PqCRr2+yrMhXTcjvyIrst73bdiKlN+bQ+6Z0XXOjtRbPH00JDO1c8GOpk3akVvijfT/+1gasNWVSW66Jsm9mL849evxFmYmLmqsSRLN7H8mUtSyP+uA7/8A</diagram></mxfile>
`@@ -1,4 +1,4 @@`
	`include $(VHDL_MAKE_HOME)/defs.mk`	`include $(VHDL_HOME)/defs.mk`

	`MOD_PATH := $(LIB_PATH)/JBUS/memory`	`MOD_PATH := $(LIB_PATH)/JBUS/memory`