This commit was manufactured by cvs2svn to create tag 'R5'.

git-svn-id: http://moon:8086/svn/vhdl/tags/R5@69 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -14,23 +14,22 @@ ENTITY dcache IS
 	);
 	Port
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
-		cpu_r_wn	: in  STD_LOGIC;
-		cpu_we		: in  unsigned(3 downto 0);
+		cpu_we		: in  STD_LOGIC;
+		cpu_be		: in  unsigned(3 downto 0);
 		cpu_addr	: in  word_t;
 		cpu_din		: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 END dcache;
 
@@ -131,12 +130,11 @@ END COMPONENT;
 		return result;
 	end to_tram_data;
 
-	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache);
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
 	signal s, sn : cache_state_t;
 	
 	signal	cache_busy			: std_logic;
-	signal	cache_read_miss		: std_logic;
-	signal	cache_write_miss	: std_logic;
+	signal	cache_hit			: std_logic;
 	signal	tag_match			: std_logic;
 	signal  word_index_reg		: unsigned(word_index_width-1 downto 0);
 	signal  cache_index_reg		: unsigned(cache_index_width-1 downto 0);
@@ -148,15 +146,16 @@ END COMPONENT;
 	signal  cpu_dram_dout		: word_t;
 	signal  cpu_dram_din		: word_t;
 	signal  cpu_data_reg		: word_t;
-	signal  cpu_we_reg			: unsigned(3 downto 0);
-	signal  ctrl_force_we		: unsigned(3 downto 0);
-	signal  cpu_was_write		: std_logic;
+	signal  cpu_be_reg			: unsigned(3 downto 0);
+	signal  cpu_we_reg			: std_logic;
+	signal	ctrl_dram_en		: std_logic;
 	signal  ctrl_dram_addr		: unsigned(lg2(cache_size)-1 downto 0);
 	signal  ctrl_dram_din		: word_t;
 	signal	ctrl_dram_we		: unsigned(3 downto 0);
 	signal	cpu_dram_we			: unsigned(3 downto 0);
-	signal	dram_en				: std_logic;
-	signal	cpu_was_en			: std_logic;
+	signal	cpu_dram_en			: std_logic;
+	signal	cpu_en2				: std_logic;
+	signal	cpu_we2				: std_logic;
 
 	signal  tram_addr_rd		: unsigned(cache_index_width-1 downto 0);
 	signal  tram_dout			: tram_data_t;
@@ -175,52 +174,72 @@ END COMPONENT;
 	signal	cpu_reg_en				: std_logic;
 	signal	was_miss				: std_logic;
 	signal	data_write				: std_logic;
-	signal	cpu_we2					: std_logic;
+	signal	cpu_hit_we				: std_logic;
+	signal	instant_raw				: std_logic;
 
 begin
 
+	cpu_hit_we	<= cpu_we2 and cache_hit;
 	
-cpu_index_reg:
-	process(clk)
+cpu_index_register:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
-				cpu_was_write	<= '0';
-			elsif cpu_reg_en = '1' and en = '1' then
+			elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
 				word_index_reg	<= cpu_word_index;
 				cache_index_reg	<= cpu_cache_index;
 				tag_index_reg	<= cpu_tag;
-				cpu_data_reg	<= cpu_din;
-				cpu_we_reg		<= cpu_we;
-				cpu_was_write	<= not cpu_r_wn;
 			end if;
 		end if;
 	end process;	
 
-cpu_was_wr_reg:
-	process(clk)
+cpu_data_register:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			cpu_was_en	<= '0';
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_we_reg	<= '0';
+			elsif cpu_reg_en = '1' and en = '1' then
+				cpu_data_reg	<= cpu_din;
+				cpu_be_reg		<= cpu_be;
+				cpu_we_reg		<= cpu_we;
+			end if;
+		end if;
+	end process;	
+
+cpu_was_wr_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cpu_en2	<= '0';
 			cpu_we2		<= '0';
 			if cpu_en = '1' and en = '1' then
-				cpu_we2		<= not cpu_r_wn;
-				cpu_was_en	<= '1';
+				cpu_we2			<= cpu_we;
+				cpu_en2			<= '1';
 				cpu_dram_din	<= cpu_din;
 			end if;
 		end if;
 	end process;	
 
+instant_raw_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			instant_raw	<= cpu_hit_we and cpu_en and en and not cpu_we;
+		end if;
+	end process;	
+
 inst_tag_ram : dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> tram_addr_width,
 		data_width	=> tram_data_width
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> tram_re,
 		we_a	=> tram_we,
@@ -240,10 +259,10 @@ gen_data_ram:
 			data_width	=> word_t'length/4
 		)
 		PORT MAP (
-			clk_a	=> clk,
-			clk_b	=> clk,
-			en_a	=> '1',
-			en_b	=> dram_en,
+			clk_a	=> CLK_I,
+			clk_b	=> CLK_I,
+			en_a	=> ctrl_dram_en,
+			en_b	=> '1',
 			we_a	=> ctrl_dram_we(i),
 			we_b	=> cpu_dram_we(i),
 			addr_a	=> ctrl_dram_addr,
@@ -256,10 +275,10 @@ gen_data_ram:
 	end generate;	
 	
 cache_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
 			else
 				s	<= sn;
@@ -267,24 +286,24 @@ cache_state_next:
 		end if;
 	end process;	
 
-	cpu_busy			<= cache_busy;
+	cpu_busy			<= cache_busy or instant_raw;
 	cpu_dout			<= cpu_dram_dout;
 	
 	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
-	cache_read_miss		<= not (tag_match and cache_entry_out.valid) and not cpu_was_write;
-	cache_write_miss	<= not (tag_match and cache_entry_out.valid and cpu_was_write);
+	cache_hit			<= tag_match and cache_entry_out.valid;
 	tram_din			<= to_tram_data(cache_entry_in);
 	tram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_dcache_entry(tram_dout);
-	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
-	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
+	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
 	ctrl_dram_addr		<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
-	ctrl_dram_din		<= mem_din;
-	ctrl_dram_we		<= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we;
-	cpu_dram_we			<= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
+	ctrl_dram_din		<= DAT_I;
+	ctrl_dram_we		<= (others => '1');
+	ctrl_dram_en		<= data_write and ACK_I;
+	cpu_dram_we			<= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
 	
 cache_state:
-	process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg)
+	process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
@@ -293,9 +312,8 @@ cache_state:
 		ram_index_count_rst		<= '0';
 		mem_index_count_en		<= '0';
 		mem_index_count_rst		<= '0';
-		mem_req					<= '0';
-		mem_en					<= '0';
-		dram_en					<= '0';
+		CYC_O					<= '0';
+		STB_O					<= '0';
 		tram_re					<= '0';
 		was_miss				<= '0';
 		data_write				<= '0';
@@ -304,7 +322,6 @@ cache_state:
 		cache_entry_in.tag		<= tag_index_reg;
 		cache_entry_in.valid	<= '0';
 		cache_entry_in.dirty	<= '0';
-		ctrl_force_we			<= (others => '0');
 		sn	<= s;
 		
 		case s is
@@ -313,13 +330,13 @@ cache_state:
 		when ready =>
 			cache_busy 		<= '0';
 			cpu_reg_en		<= '1';
-			dram_en			<= cpu_en or cpu_was_en;
 			tram_re			<= cpu_en;
-			if cpu_was_en = '1' then
-				if cache_read_miss = '1' then
+			if cpu_en2 = '1' then
+				if cache_hit = '0' and cpu_we_reg = '0' then
 					sn						<= mem_request;
 					cpu_reg_en				<= '0';
 					cache_busy 				<= '1';
+					CYC_O					<= '1';
 				end if;	
 			end if;	
 		when flush =>
@@ -332,65 +349,53 @@ cache_state:
 				sn	<= ready;
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
-					dram_en			<= '1';
 					tram_re				<= '1';
 				end if;
 			end if;
 		when mem_request =>
 			ram_index_count_rst		<= '1';
 			mem_index_count_rst		<= '1';
-			mem_req		<= '1';
-			if mem_gnt = '1' then
+			CYC_O		<= '1';
+			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
 			data_write			<= '1';
-			mem_req		<= '1';
-			if mem_rdy = '1' then
 			mem_index_count_en	<= '1';
-				mem_en				<= '1';
+			CYC_O				<= '1';
+			STB_O				<= '1';
 			if mem_index_count = 2**word_index_width-1 then
+				if SRDY_I = '1' then
 					sn <= mem_data;
 				end if;	
 			end if;	
 		when mem_data =>
-			mem_req		<= '1';
+			CYC_O		<= '1';
 			data_write	<= '1';
 			if ram_index_count = 2**word_index_width-1 then
-				if mem_valid = '1' then
+				if ACK_I = '1' then
 					sn			<= upd_cache;
 				end if;	
 			end if;	
 		when upd_cache =>
-			mem_req					<= '1';
 			tram_addr_wr			<= cache_index_reg;
 			tram_we					<= '1';
 			cache_entry_in.valid	<= '1';
-			if cpu_was_write = '1' then
-				sn					<= wr_cache;
-			else	
 			sn						<= rd_cache;
-			end if;	
-			
 		when rd_cache =>
 			tram_re					<= '1';
-			dram_en					<= '1';
 			was_miss				<= '1';
 			sn	<= ready;
 
-		when wr_cache =>
-			tram_re					<= '1';
-			ctrl_force_we			<= cpu_we_reg;
-			sn	<= ready;
 		when others => 
 			sn	<= ready;
 		end case;
 	end process;
 
 cache_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if cache_index_count_en = '0' then
 				cache_index_count	<= 2**cache_index_width-1;
 			elsif cache_index_count /= 0 then
@@ -400,12 +405,12 @@ cache_index_counter:
 	end process;	
 		
 ram_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if ram_index_count_rst = '1' then
 				ram_index_count	<= 0;
-			elsif data_write = '1' and mem_valid = '1' then
+			elsif data_write = '1' and ACK_I = '1' then
 				if ram_index_count /= 2**word_index_width-1 then
 					ram_index_count 	<= ram_index_count + 1;
 				end if;
@@ -414,12 +419,12 @@ ram_index_counter:
 	end process;	
 
 mem_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if mem_index_count_rst = '1' then
 				mem_index_count	<= 0;
-			elsif mem_index_count_en = '1' then
+			elsif mem_index_count_en = '1' and SRDY_I = '1' then
 				if mem_index_count /= 2**word_index_width-1 then
 					mem_index_count 	<= mem_index_count + 1;
 				end if;

lib/CPUs/MIPS/src/core/icache.vhd

@@ -14,20 +14,19 @@ ENTITY icache IS
 	);
 	Port
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
 		cpu_addr	: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 END icache;
 
@@ -143,10 +142,10 @@ begin
 
 	
 cpu_index_reg:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
 			elsif cpu_reg_en = '1' then
@@ -163,8 +162,8 @@ inst_tag_ram : dpram_1w1r
 		data_width	=> tag_ram_data_width
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> tag_ram_re,
 		we_a	=> tag_ram_we,
@@ -180,8 +179,8 @@ inst_data_ram : dpram_1w1r
 		data_width	=> word_t'length
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> data_ram_re,
 		we_a	=> data_ram_we,
@@ -193,10 +192,10 @@ inst_data_ram : dpram_1w1r
 	
 	
 cache_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
 			else
 				s	<= sn;
@@ -213,13 +212,13 @@ cache_state_next:
 	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_icache_entry(tag_ram_data_rd);
 	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
-	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
 	data_ram_addr_wr	<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
-	data_ram_data_wr	<= mem_din;
-	data_ram_we			<= data_write and mem_valid;
+	data_ram_data_wr	<= DAT_I;
+	data_ram_we			<= data_write and ACK_I;
 
 cache_state:
-	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en)
+	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
@@ -228,8 +227,8 @@ cache_state:
 		ram_index_count_rst		<= '0';
 		mem_index_count_en		<= '0';
 		mem_index_count_rst		<= '0';
-		mem_req					<= '0';
-		mem_en					<= '0';
+		CYC_O					<= '0';
+		STB_O					<= '0';
 		data_ram_re				<= '0';
 		tag_ram_re				<= '0';
 		was_miss				<= '0';
@@ -250,6 +249,7 @@ cache_state:
 					sn						<= mem_request;
 					cpu_reg_en				<= '0';
 					cache_busy 				<= '1';
+					CYC_O					<= '1';
 				elsif cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
@@ -273,37 +273,35 @@ cache_state:
 		when mem_request =>
 			ram_index_count_rst		<= '1';
 			mem_index_count_rst		<= '1';
-			mem_req		<= '1';
-			if mem_gnt = '1' then
+			CYC_O		<= '1';
+			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
-			data_write	<= '1';
-			mem_req		<= '1';
-			if mem_rdy = '1' then
 			mem_index_count_en	<= '1';
-				mem_en				<= '1';
+			data_write	<= '1';
+			CYC_O		<= '1';
+			STB_O		<= '1';
 			if mem_index_count = 2**word_index_width-1 then
+				if SRDY_I = '1' then
 					sn			<= mem_data;
 				end if;	
 			end if;	
 		when mem_data =>
-			mem_req		<= '1';
+			CYC_O		<= '1';
 			data_write	<= '1';
 			if ram_index_count = 2**word_index_width-1 then
-				if mem_valid = '1' then
+				if ACK_I = '1' then
 					sn			<= upd_cache;
 				end if;	
 			end if;	
 		when upd_cache =>
-			mem_req					<= '1';
 			tag_ram_addr_wr			<= cache_index_reg;
 			tag_ram_we				<= '1';
 			cache_entry_in.valid	<= '1';
 			sn						<= rd_cache;
 			
 		when rd_cache =>
---			mem_req					<= '1';
 			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';
@@ -314,9 +312,9 @@ cache_state:
 	end process;
 
 cache_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if cache_index_count_en = '0' then
 				cache_index_count	<= 2**cache_index_width-1;
 			elsif cache_index_count /= 0 then
@@ -326,12 +324,12 @@ cache_index_counter:
 	end process;	
 		
 ram_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if ram_index_count_rst = '1' then
 				ram_index_count	<= 0;
-			elsif data_write = '1' and mem_valid = '1' then
+			elsif data_write = '1' and ACK_I = '1' then
 				if ram_index_count /= 2**word_index_width-1 then
 					ram_index_count 	<= ram_index_count + 1;
 				end if;
@@ -340,12 +338,12 @@ ram_index_counter:
 	end process;	
 
 mem_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if mem_index_count_rst = '1' then
 				mem_index_count	<= 0;
-			elsif mem_index_count_en = '1' then
+			elsif mem_index_count_en = '1' and SRDY_I = '1' then
 				if mem_index_count /= 2**word_index_width-1 then
 					mem_index_count 	<= mem_index_count + 1;
 				end if;

lib/CPUs/MIPS/src/core/mips_bui.vhd

@@ -31,31 +31,32 @@ use work.mips_types.all;
 entity bui is
 	Port
 	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ce				: in  STD_LOGIC;
-		cpu_wait		: out STD_LOGIC;
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		ADDR_O			: out word_t;
+		DAT_I			: in  word_t;
+		DAT_O			: out word_t;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		cpu_imem_err	: out STD_LOGIC;
 		cpu_imem_rdy	: out STD_LOGIC;
 		cpu_imem_en		: in  STD_LOGIC;
 		cpu_imem_addr	: in  word_t;
 		cpu_imem_din	: out word_t;
+		cpu_dmem_err	: out STD_LOGIC;
 		cpu_dmem_rdy	: out STD_LOGIC;
 		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_re		: in  STD_LOGIC;
-		cpu_dmem_we		: in  unsigned(3 downto 0);
+		cpu_dmem_we		: in  STD_LOGIC;
+		cpu_dmem_be		: in  unsigned(3 downto 0);
 		cpu_dmem_dout	: in  word_t;
 		cpu_dmem_din	: out word_t;
-		cpu_dmem_addr	: in  word_t;
-		mem_valid		: in  STD_LOGIC;
-		mem_rdy			: in  STD_LOGIC;
-		mem_addr		: out word_t;
-		mem_din			: in  word_t;
-		mem_dout		: out word_t;
-		mem_re			: out STD_LOGIC;
-		mem_we			: out unsigned(3 downto 0);
-		mem_ce			: out STD_LOGIC
+		cpu_dmem_addr	: in  word_t
 	);
-	
 end bui;
 
 architecture behavior of bui is
@@ -68,20 +69,19 @@ COMPONENT icache
 	);
 	PORT
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
 		cpu_addr	: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 	END COMPONENT;
 
@@ -93,64 +93,126 @@ COMPONENT dcache
 	);
 	PORT
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
-		cpu_r_wn	: in  STD_LOGIC;
-		cpu_we		: in  unsigned(3 downto 0);
+		cpu_we		: in  STD_LOGIC;
+		cpu_be		: in  unsigned(3 downto 0);
 		cpu_addr	: in  word_t;
 		cpu_din		: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 	END COMPONENT;
 
-	type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish);
+	type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
 	
 	signal s, sn 			: bus_state_t;
-	signal dmem_re			: std_logic;
-	signal dmem_we			: unsigned(3 downto 0);
+	signal bus_idle			: std_logic;
+	signal busy				: std_logic;
+	signal dmem_be			: unsigned(3 downto 0);
 	signal dcache_dout		: word_t;
-	signal dmem_dout		: word_t;
-	signal dmem_din			: word_t;
-	signal dmem_addr		: word_t;
-	signal imem_addr		: word_t;
-	signal imem_mem_out_en	: std_logic;
-	signal dmem_mem_out_en 	: std_logic;
-	signal dmem_ack			: std_logic;
-	signal dcache_busy1		: std_logic;
-	signal dcache_busy2		: std_logic;
-	signal icache_busy 		: std_logic;
-	signal bus_req	 		: std_logic;
-	signal icache_mem_en	: std_logic;
-	signal icache_mem_req	: std_logic;
-	signal icache_mem_gnt	: std_logic;
-	signal icache_mem_addr	: word_t;
-	signal dcache_mem_en	: std_logic;
-	signal dcache_mem_req	: std_logic;
 	signal dcache_mem_gnt	: std_logic;
-	signal dcache_mem_addr	: word_t;
+	signal icache_mem_gnt 	: std_logic;
+	signal dmem_mem_wr_gnt	: std_logic;
+	signal dmem_mem_rd_gnt	: std_logic;
+	signal dcache_busy		: std_logic;
+	signal icache_busy 		: std_logic;
+	signal CYC_O_icache		: std_logic;
+	signal CYC_O_dcache		: std_logic;
+	signal CYC_O_dmem_rd	: std_logic;
+	signal CYC_O_dmem_wr	: std_logic;
+	signal SRDY_I_icache	: std_logic;
+	signal SRDY_I_dcache	: std_logic;
+	signal ADDR_O_icache	: word_t;
+	signal ADDR_O_dcache	: word_t;
+	signal ADDR_O_dmem_rd	: word_t;
+	signal ADDR_O_dmem_wr	: word_t;
+	signal STB_O_icache		: std_logic;
+	signal STB_O_dcache		: std_logic;
+	signal STB_O_dmem_rd	: std_logic;
+	signal STB_O_dmem_wr	: std_logic;
+	signal DAT_I_dmem_rd	: word_t;
+	signal DAT_O_dmem_wr	: word_t;
+	signal SEL_O_dmem_wr	: unsigned(3 downto 0);
 	signal dcached			: std_logic;
-	signal duncached_access	: std_logic;
 	signal dcache_en		: std_logic;
+	signal uncached_access	: std_logic;
+	
+	type timeout_cnt_t is range 0 to 1E5-1;	
+	signal bus_timeout_cnt	: timeout_cnt_t;
+	signal bus_timeout		: std_logic;
+	
+	signal bout_fifo_din	: unsigned(68 downto 0);
+	signal bout_fifo_dout	: unsigned(68 downto 0);
+	signal bout_fifo_re		: std_logic;
+	signal bout_fifo_we		: std_logic;
+	signal bout_fifo_full	: std_logic;
+	signal bout_fifo_empty	: std_logic;
+	signal bout_rdy			: std_logic;
+
+	alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
+	alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
+	alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
+	alias bout_fifo_we_in is bout_fifo_din(68);
+	alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
+	alias bout_fifo_data_out is bout_fifo_dout(63 downto 32);
+	alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64);
+	alias bout_fifo_we_out is bout_fifo_dout(68);
+
+	signal write_fifo_din	: unsigned(67 downto 0);
+	signal write_fifo_dout	: unsigned(67 downto 0);
+	signal write_fifo_re	: std_logic;
+	signal write_fifo_we	: std_logic;
+	signal write_fifo_full	: std_logic;
+	signal write_fifo_empty	: std_logic;
+	signal write_busy		: std_logic;
+
+	alias write_fifo_addr_in is write_fifo_din(31 downto 0);
+	alias write_fifo_data_in is write_fifo_din(63 downto 32);
+	alias write_fifo_sel_in is write_fifo_din(67 downto 64);
+	alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
+	alias write_fifo_data_out is write_fifo_dout(63 downto 32);
+	alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
+
+	signal read_cycle	: std_logic;
 
 begin
 
-	mem_ce 			<= mem_rdy and bus_req;
+
+	MRDY_O			<= '1';
+
+read_cyc_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				read_cycle		<= '0';
+			else
+				read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) 
+								or (dcache_mem_gnt and CYC_O_dcache) 
+								or (icache_mem_gnt and CYC_O_icache);
+			end if;
+		end if;
+	end process;	
+					
+	CYC_O			<= not bout_fifo_empty or read_cycle;
+	STB_O			<= not bout_fifo_empty;
+	ADDR_O			<= bout_fifo_addr_out;
+	DAT_O			<= bout_fifo_data_out;
+	SEL_O			<= bout_fifo_sel_out;
+	WE_O			<= bout_fifo_we_out;
 
 	cpu_imem_rdy	<= not icache_busy after 4.5 ns;
---	cpu_imem_din	<= imem_din;
---	cpu_wait		<= busy after 5.5 ns;
-	cpu_wait		<= '0';
-	cpu_dmem_rdy	<= not (dcache_busy1 or dcache_busy2) after 4.5 ns;
+	busy			<= CYC_O_dmem_rd or dcache_busy or (write_busy);
+	cpu_dmem_rdy	<= not busy after 4.5 ns;
 	
 inst_icache : icache
 	GENERIC MAP
@@ -160,22 +222,23 @@ inst_icache : icache
 	)	
 	PORT MAP
 	(
-		clk			=> clk,
-		rst			=> rst,
+		CLK_I		=> CLK_I,
+		RST_I		=> RST_I,
+		STB_O		=> STB_O_icache,
+		CYC_O		=> CYC_O_icache,
+		ADDR_O		=> ADDR_O_icache,
+		DAT_I		=> DAT_I,
+		ACK_I		=> ACK_I,
+		SRDY_I		=> SRDY_I_icache,
 		en			=> '1',
 		cpu_en		=> cpu_imem_en,
 		cpu_addr	=> cpu_imem_addr,
 		cpu_dout	=> cpu_imem_din,
-		cpu_busy	=> icache_busy,
-		mem_en		=> icache_mem_en,
-		mem_req		=> icache_mem_req,
-		mem_gnt		=> icache_mem_gnt,
-		mem_addr	=> icache_mem_addr,
-		mem_din		=> mem_din,
-		mem_valid	=> mem_valid,
-		mem_rdy		=> mem_rdy
+		cpu_busy	=> icache_busy
 	);
 
+	SRDY_I_icache	<= bout_rdy and icache_mem_gnt;
+
 inst_dcache : dcache
 	GENERIC MAP
 	(
@@ -184,147 +247,211 @@ inst_dcache : dcache
 	)
 	PORT MAP
 	(
-		clk			=> clk,
-		rst			=> rst,
+		CLK_I		=> CLK_I,
+		RST_I		=> RST_I,
+		CYC_O		=> CYC_O_dcache,
+		STB_O		=> STB_O_dcache,
+		ADDR_O		=> ADDR_O_dcache,
+		DAT_I		=> DAT_I,
+		ACK_I		=> ACK_I,
+		SRDY_I		=> SRDY_I_dcache,
 		en			=> dcached,
 		cpu_en		=> dcache_en,
-		cpu_r_wn	=> cpu_dmem_re,
 		cpu_we		=> cpu_dmem_we,
+		cpu_be		=> cpu_dmem_be,
 		cpu_addr	=> cpu_dmem_addr,
 		cpu_din		=> cpu_dmem_dout,
 		cpu_dout	=> dcache_dout,
-		cpu_busy	=> dcache_busy2,
-		mem_req		=> dcache_mem_req,
-		mem_gnt		=> dcache_mem_gnt,
-		mem_en		=> dcache_mem_en,
-		mem_addr	=> dcache_mem_addr,
-		mem_din		=> mem_din,
-		mem_valid	=> mem_valid,
-		mem_rdy		=> mem_rdy
+		cpu_busy	=> dcache_busy
 	);
 
+	SRDY_I_dcache	<= bout_rdy and dcache_mem_gnt;
+
 	dcached			<= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
-	cpu_dmem_din	<= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns;
-	dcache_en		<= cpu_dmem_en and not dcache_busy1;
+	cpu_dmem_din	<= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
+	dcache_en		<= cpu_dmem_en and not busy;
 	
-dcache_flags:
-	process(clk)
+-- Instantiate synchronous FIFO
+inst_bout_fifo: entity work.fifo_sync_dist
+	GENERIC MAP
+	(
+		addr_width	=> 4,
+		data_width	=> 69
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	bout_fifo_we,
+		re			=>	bout_fifo_re,
+		fifo_full	=>	bout_fifo_full,
+		fifo_empty	=>	bout_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  bout_fifo_din,
+		data_r		=>  bout_fifo_dout
+	);
+	bout_rdy			<= not bout_fifo_full;
+	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
+	
+	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
+-- 	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+-- 						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
+-- 						   STB_O_dcache when dcache_mem_gnt = '1' else
+-- 						   STB_O_icache when icache_mem_gnt = '1' else '0';
+						   
+
+	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
+	
+	bout_fifo_addr_in	<= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+						   ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else
+						   ADDR_O_dcache when dcache_mem_gnt = '1' else
+						   ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
+
+	bout_fifo_sel_in	<= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
+	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
+
+-- Instantiate synchronous FIFO
+inst_write_fifo: entity work.fifo_sync_dist
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> 68
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	write_fifo_we,
+		re			=>	write_fifo_re,
+		fifo_full	=>	write_busy,
+		fifo_empty	=>	write_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  write_fifo_din,
+		data_r		=>  write_fifo_dout
+	);
+
+	CYC_O_dmem_wr	<= not write_fifo_empty;
+	DAT_O_dmem_wr	<= write_fifo_data_out;
+	ADDR_O_dmem_wr	<= write_fifo_addr_out;
+	SEL_O_dmem_wr	<= write_fifo_sel_out;
+
+	write_fifo_data_in	<= cpu_dmem_dout;
+	write_fifo_addr_in	<= cpu_dmem_addr;
+	write_fifo_sel_in	<= cpu_dmem_be;
+	write_fifo_re		<= STB_O_dmem_wr;
+	write_fifo_we		<= cpu_dmem_en and not busy and cpu_dmem_we;
+	
+dmem_rd_flags:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				dcache_busy1		<= '0';
+		if rising_edge(CLK_I) then
+			uncached_access	<= '0';
+			if RST_I = '1' then
+				CYC_O_dmem_rd		<= '0';
 			else	
-				duncached_access <= '0';
-				if dmem_ack = '1' then
-					duncached_access <= '1';
-					if dmem_re = '1' then
-						if mem_valid = '1' then
-							dcache_busy1		<= '0';
+				if ACK_I = '1' and dmem_mem_rd_gnt = '1' then
+					uncached_access		<= '1';
+					CYC_O_dmem_rd		<= '0';
 				end if;	
-					else
-						dcache_busy1		<= '0';
-					end if;	
-				end if;	
-				if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
-					dcache_busy1		<= '1';
-					if dcached = '1' and cpu_dmem_re = '1' then
-						dcache_busy1	<= '0';
+				if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
+					if dcached = '0' then
+						CYC_O_dmem_rd	<= '1';
 					end if;	
 				end if;
 			end if;
 		end if;
 	end process;	
 	
-dcache_regs:
-	process(clk)
+dmem_rd_data:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
-				dmem_dout		<= cpu_dmem_dout;
-				dmem_addr		<= cpu_dmem_addr;
-				dmem_re			<= cpu_dmem_re;
-				dmem_we			<= cpu_dmem_we;
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				DAT_I_dmem_rd		<= (others => '0');
+			elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then
+				DAT_I_dmem_rd		<= DAT_I;
 			end if;
 		end if;
 	end process;	
 	
-dcache_data:
-	process(clk)
+dmem_rd_regs:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				dmem_din		<= (others => '0');
-			elsif dcache_busy1 = '1' and mem_valid = '1' then
-				dmem_din		<= mem_din;
+		if rising_edge(CLK_I) then
+			if cpu_dmem_en = '1' and busy = '0' then
+				ADDR_O_dmem_rd		<= cpu_dmem_addr;
 			end if;
 		end if;
 	end process;	
 	
 bus_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
-			elsif ce = '1' then
+			else
 				s	<= sn;
 			end if;
 		end if;
 	end process;	
 	
 bus_state:
-	process(s, icache_mem_en, icache_mem_req, dcache_busy1, dcache_mem_req, dcache_mem_en, dmem_re, mem_rdy, mem_valid)
+	process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I)
 	begin
 		
-		imem_mem_out_en	<= '0';
-		dmem_mem_out_en	<= '0';
 		icache_mem_gnt		<= '0';
 		dcache_mem_gnt		<= '0';
-		dmem_ack		<= '0';
-		
+		dmem_mem_rd_gnt		<= '0';	
+		dmem_mem_wr_gnt		<= '0';	
+		STB_O_dmem_rd		<= '0';
+		STB_O_dmem_wr		<= '0';
+		bus_idle			<= '0';
 		sn					<= s;
 		case s is
 		when init =>
-			if mem_rdy = '1' then
 			sn		<= ready;
-			end if;	
 		when ready =>
-			if dcache_busy1 = '1' then
-				if mem_rdy = '1' then
-					dmem_mem_out_en	<= '1';
-					if dmem_re = '0' then
-						sn			<= d_bus_finish;
-					else
-						sn			<= d_bus_access;
+			bus_idle	<= '1';
+			if CYC_O_dmem_wr = '1' then
+				sn			<= write_bus;
+			elsif CYC_O_dmem_rd = '1' then
+				sn			<= read_bus;
+			elsif CYC_O_icache = '1' then
+				sn			<= icache_bus_access;
+			elsif CYC_O_dcache = '1' then
+				sn			<= dcache_bus_access;
 			end if;
-				end if;
-			elsif icache_mem_req = '1' then
-				sn				<= i_cache_bus_access;
-			elsif dcache_mem_req = '1' then
-				sn				<= d_cache_bus_access;
-			end if;
-		when i_cache_bus_access =>
+		when icache_bus_access =>
 			icache_mem_gnt	<= '1';
-			if icache_mem_en = '1' then
-				imem_mem_out_en	<= '1';
-			elsif icache_mem_req = '0' then
+			if CYC_O_icache = '0' then
 				sn			<= ready;
 			end if;	
-		when d_cache_bus_access =>
+		when dcache_bus_access =>
 			dcache_mem_gnt	<= '1';
-			if dcache_mem_en = '1' then
-				dmem_mem_out_en	<= '1';
-			elsif dcache_mem_req = '0' then
+			if CYC_O_dcache = '0' then
 				sn			<= ready;
 			end if;	
-		when d_bus_access =>
-			if mem_valid = '1' then
-				dmem_ack	<= '1';
+		when write_bus =>
+			dmem_mem_wr_gnt	<= '1';	
+			if CYC_O_dmem_wr = '1' then
+				if bout_rdy = '1' then
+					STB_O_dmem_wr	<= '1';
+				end if;
+			else
 				sn			<= ready;
 			end if;	
-		when d_bus_finish =>
-			if mem_rdy = '1' then
-				dmem_ack	<= '1';
+		when read_bus =>
+			dmem_mem_rd_gnt	<= '1';	
+			if bout_rdy = '1' then
+				STB_O_dmem_rd	<= '1';
+				sn				<= read_finish;
+			end if;	
+		when read_finish =>
+			dmem_mem_rd_gnt	<= '1';	
+			if ACK_I = '1' then
 				sn			<= ready;
 			end if;
 		when others =>
@@ -333,44 +460,33 @@ bus_state:
 				
 	end process;	
 
-bus_request:
-	process(clk)
+bus_timeout_counter:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				bus_req 	<= '0';
-			elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then
-				bus_req		<= '1';
-			elsif mem_rdy = '1' then
-				bus_req 	<= '0';
+		if rising_edge(CLK_I) then
+			if bus_idle = '0' then
+				if bus_timeout_cnt /= 0 then
+					bus_timeout_cnt	<= bus_timeout_cnt - 1;
+				else
+					bus_timeout	<= '1';
+				end if;	
+			else
+				bus_timeout_cnt	<= timeout_cnt_t'high;
+				bus_timeout		<= '0';
 			end if;
 		end if;
 	end process;	
 
-bus_out:
-	process(clk)
+bus_err:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				mem_dout	<= (others => '0');
-				mem_addr	<= (others => '0');
-				mem_re		<= '0';
-				mem_we		<= (others => '0');
-			elsif dmem_mem_out_en = '1' then
-				if dcache_mem_gnt = '1' then
-					mem_addr	<= dcache_mem_addr;
-					mem_re		<= '1';
-					mem_we		<= (others => '0');
-				else
-					mem_dout	<= dmem_dout;
-					mem_addr	<= dmem_addr;
-					mem_re		<= dmem_re;
-					mem_we		<= dmem_we;
-				end if;
-			elsif imem_mem_out_en = '1' then
-				mem_addr	<= icache_mem_addr;
-				mem_re		<= '1';
-				mem_we		<= (others => '0');
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_imem_err	<= '0';
+				cpu_dmem_err	<= '0';
+			elsif bus_timeout = '1' then
+				cpu_imem_err	<= icache_mem_gnt;
+				cpu_dmem_err	<= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt;
 			end if;
 		end if;
 	end process;	

lib/CPUs/MIPS/src/core/mips_cop.vhd

@@ -82,12 +82,12 @@ architecture Behavioral of cop is
 	signal cop_pipe_ID : cop_pipe_t;
 	signal cop_pipe_EX : cop_pipe_t;
 	
-	function eval_int(ip, im : unsigned) return STD_LOGIC is
+	function eval_int(ip : unsigned) return STD_LOGIC is
 	variable result : STD_LOGIC;
 	begin
 			result := '0';
 			for i in ip'range loop
-				result := result or (ip(i) and im(i));
+				result := result or ip(i);
 			end loop;
 
 			return result;
@@ -128,7 +128,7 @@ begin
 	eflags.Sys		<= events.syscall;
 	eflags.Bp		<= events.break;
 	eflags.RI		<= events.illegal;
-	eflags.Int		<= eval_int(ip, im) and status(0);
+	eflags.Int		<= eval_int(ip) and status(0);
 
 	exception		<= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns;
 	
@@ -280,9 +280,9 @@ cop_ip_reg_write:
 			if rst = '1' then
 				ip(1 downto 0) <= (others => '0');
 			elsif ip_reg_we = '1' then
-				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8);
+				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8) and im(1 downto 0);
 			end if;	
-			ip(7 downto 2)	<= events.Int;
+			ip(7 downto 2)	<= events.Int and im(7 downto 2);
 		end if;
 	end process;
 

lib/CPUs/MIPS/src/core/mips_pipeline.vhd

@@ -35,14 +35,16 @@ entity pipeline is
 		clk			: in  STD_LOGIC;
 		halt		: in  STD_LOGIC;
 		int			: in  unsigned(5 downto 0);
+		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
 		imem_en		: out STD_LOGIC;
 		imem_addr	: out word_t;
 		imem_data	: in  word_t;
+		dmem_err	: in  STD_LOGIC;
 		dmem_rdy	: in  STD_LOGIC;
 		dmem_en		: out STD_LOGIC;
-		dmem_re		: out STD_LOGIC;
-		dmem_we		: out unsigned(3 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_be		: out unsigned(3 downto 0);
 		dmem_addr	: out word_t;
 		dmem_din	: in  word_t;
 		dmem_dout	: out word_t
@@ -623,8 +625,8 @@ proc_stage_DMEM_ADDR:
 			end if;
 		end if;
 	end process;
-	dmem_we		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
-	dmem_re		<= not EX_stage.ctrl.dmem_we;
+	dmem_be		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
+	dmem_we		<= EX_stage.ctrl.dmem_we;
 	dmem_dout	<= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
 	dmem_addr	<= EX_stage.va;
 	cop_din		<= EX_stage.reg_b;

lib/CPUs/MIPS/src/core/mips_top.vhd

@@ -31,17 +31,20 @@ use work.mips_types.all;
 entity mips_top is
 	Port
 	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		int			: in  unsigned (5 downto 0);
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_re		: out STD_LOGIC;
-		mem_we		: out unsigned(3 downto 0);
-		mem_din		: in  unsigned (WORD_WIDTH-1 downto 0);
-		mem_dout	: out unsigned (WORD_WIDTH-1 downto 0);
-		mem_addr	: out unsigned (WORD_WIDTH-1 downto 0)
+		debug		: out unsigned(1 downto 0);
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		DAT_O		: out word_t;
+		WE_O		: out STD_LOGIC;
+		SEL_O		: out unsigned(3 downto 0);
+		CYC_O		: out STD_LOGIC;
+		STB_O		: out STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
+		INT			: in  unsigned (5 downto 0)
 	);
 	
 end mips_top;
@@ -49,85 +52,96 @@ end mips_top;
 architecture rtl of mips_top is
 
 	COMPONENT pipeline is
-	Port (
+	Port 
+	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
 		halt		: in  STD_LOGIC;
 		int			: in  unsigned (5 downto 0);
+		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
 		imem_en		: out STD_LOGIC;
 		imem_addr	: out word_t;
 		imem_data	: in  word_t;
+		dmem_err	: in  STD_LOGIC;
 		dmem_rdy	: in  STD_LOGIC;
 		dmem_en		: out STD_LOGIC;
-		dmem_re		: out STD_LOGIC;
-		dmem_we		: out unsigned(3 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_be		: out unsigned(3 downto 0);
 		dmem_addr	: out word_t;
 		dmem_din	: in  word_t;
 		dmem_dout	: out word_t
 	);
 	END COMPONENT;
-	signal halt				: std_logic;
+	signal imem_err			: std_logic;
 	signal imem_rdy			: std_logic;
 	signal imem_en			: std_logic;
 	signal imem_addr		: word_t;
 	signal imem_din			: word_t;
+	signal dmem_err			: std_logic;
 	signal dmem_rdy			: std_logic;
 	signal dmem_en			: std_logic;
-	signal dmem_re			: std_logic;
+	signal dmem_we			: std_logic;
 	signal dmem_addr		: word_t;
 	signal dmem_dout		: word_t;
 	signal dmem_din			: word_t;
-	signal dmem_we			: unsigned(3 downto 0);
+	signal dmem_be			: unsigned(3 downto 0);
+
 
 	COMPONENT bui
-	Port
+	PORT
 	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ce				: in  STD_LOGIC;
-		cpu_wait		: out STD_LOGIC;
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		ADDR_O			: out word_t;
+		DAT_I			: in  word_t;
+		DAT_O			: out word_t;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		cpu_imem_err	: out STD_LOGIC;
 		cpu_imem_rdy	: out STD_LOGIC;
 		cpu_imem_en		: in  STD_LOGIC;
 		cpu_imem_addr	: in  word_t;
 		cpu_imem_din	: out word_t;
+		cpu_dmem_err	: out STD_LOGIC;
 		cpu_dmem_rdy	: out STD_LOGIC;
 		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_re		: in  STD_LOGIC;
-		cpu_dmem_we		: in  unsigned(3 downto 0);
-		cpu_dmem_addr	: in  word_t;
-		cpu_dmem_din	: out word_t;
+		cpu_dmem_we		: in  STD_LOGIC;
+		cpu_dmem_be		: in  unsigned(3 downto 0);
 		cpu_dmem_dout	: in  word_t;
-		mem_valid		: in  STD_LOGIC;
-		mem_rdy			: in  STD_LOGIC;
-		mem_addr		: out word_t;
-		mem_din			: in  word_t;
-		mem_dout		: out word_t;
-		mem_re			: out STD_LOGIC;
-		mem_we			: out unsigned(3 downto 0);
-		mem_ce			: out STD_LOGIC
+		cpu_dmem_din	: out word_t;
+		cpu_dmem_addr	: in  word_t
 	);
 	END COMPONENT;
 
 begin
 
 -------------------------------------------------------------------
+	debug(0)		<= imem_err;
+	debug(1)		<= dmem_err;
 	
 inst_pipeline: pipeline
 	PORT MAP
 	(
-		rst			=> rst,
-		clk			=> clk,
-		halt		=> halt,
-		int			=> int,
+		rst			=> RST_I,
+		clk			=> CLK_I,
+		halt		=> '0',
+		int			=> INT,
+		imem_err	=> imem_err,
 		imem_rdy	=> imem_rdy,
 		imem_en		=> imem_en,
 		imem_addr	=> imem_addr,
 		imem_data	=> imem_din,
+		dmem_err	=> dmem_err,
 		dmem_rdy	=> dmem_rdy,
 		dmem_en		=> dmem_en,
-		dmem_re		=> dmem_re,
 		dmem_we		=> dmem_we,
+		dmem_be		=> dmem_be,
 		dmem_addr	=> dmem_addr,
 		dmem_din	=> dmem_din,
 		dmem_dout	=> dmem_dout
@@ -136,29 +150,31 @@ inst_pipeline: pipeline
 inst_bui: bui
 	PORT MAP
 	(
-		rst				=> rst,
-		clk				=> clk,
-		ce				=> '1',
-		cpu_wait		=> halt,
+		RST_I			=> RST_I,
+		CLK_I			=> CLK_I,
+		ACK_I			=> ACK_I,
+		SRDY_I			=> SRDY_I,
+		ADDR_O			=> ADDR_O,
+		DAT_I			=> DAT_I,
+		DAT_O			=> DAT_O,
+		WE_O			=> WE_O,
+		SEL_O			=> SEL_O,
+		CYC_O			=> CYC_O,
+		STB_O			=> STB_O,
+		MRDY_O			=> MRDY_O,
+		cpu_imem_err	=> imem_err,
 		cpu_imem_rdy	=> imem_rdy,
 		cpu_imem_en		=> imem_en,
 		cpu_imem_addr	=> imem_addr,
 		cpu_imem_din	=> imem_din,
+		cpu_dmem_err	=> dmem_err,
 		cpu_dmem_rdy	=> dmem_rdy,
 		cpu_dmem_en		=> dmem_en,
-		cpu_dmem_re		=> dmem_re,
 		cpu_dmem_we		=> dmem_we,
+		cpu_dmem_be		=> dmem_be,
 		cpu_dmem_addr	=> dmem_addr,
 		cpu_dmem_din	=> dmem_din,
-		cpu_dmem_dout	=> dmem_dout,
-		mem_valid		=> mem_valid,
-		mem_rdy			=> mem_rdy,
-		mem_addr		=> mem_addr,
-		mem_din			=> mem_din,
-		mem_dout		=> mem_dout,
-		mem_re			=> mem_re,
-		mem_we			=> mem_we,
-		mem_ce			=> mem_en
+		cpu_dmem_dout	=> dmem_dout
 	);
 
 end rtl;

lib/FIFO/sim/tb_async_fifo_ctrl.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_async_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_async_fifo_ctrl
+view wave
+do {tb_async_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us

lib/FIFO/sim/tb_async_fifo_ctrl.wdo

@@ -0,0 +1,36 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
+add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {115874 ps} {612358 ps}

lib/FIFO/sim/tb_gray_counter.fdo

@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/tb_gray_counter.vhd"
+vsim -t 1ps   -lib work tb_gray_counter
+view wave
+do {tb_gray_counter.wdo}
+view structure
+view signals
+
+run 1us

lib/FIFO/sim/tb_gray_counter.wdo

@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_gray_counter/rst
+add wave -noupdate -format Logic /tb_gray_counter/ce
+add wave -noupdate -format Logic /tb_gray_counter/clk
+add wave -noupdate -format Literal /tb_gray_counter/bcnt
+add wave -noupdate -format Literal /tb_gray_counter/bnxt
+add wave -noupdate -format Literal /tb_gray_counter/gcnt
+add wave -noupdate -format Literal /tb_gray_counter/gnxt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {20898 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {134759 ps}

lib/FIFO/sim/tb_sync_fifo_ctrl.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_sync_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_sync_fifo_ctrl
+view wave
+do {tb_sync_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us

lib/FIFO/sim/tb_sync_fifo_ctrl.wdo

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2166667 ps}

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity async_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst					: in  STD_LOGIC;
+		clk_w				: in  STD_LOGIC;
+		clk_r				: in  STD_LOGIC;
+		we					: in  STD_LOGIC;
+		re					: in  STD_LOGIC;
+		ptr_w				: out unsigned (addr_width-1 downto 0);
+		ptr_r				: out unsigned (addr_width-1 downto 0);
+		fifo_full			: out STD_LOGIC;
+		fifo_empty			: out STD_LOGIC;
+		fifo_afull			: out STD_LOGIC;
+		fifo_aempty			: out STD_LOGIC
+	);
+end async_fifo_ctrl;
+
+architecture Behavioral of async_fifo_ctrl is
+
+	signal gcnt_w		: unsigned (addr_width downto 0);
+	signal gcnt2_w		: unsigned (addr_width downto 0);
+	signal bcnt2_aw		: unsigned (addr_width downto 0);
+	signal bcnt_w		: unsigned (addr_width downto 0);
+	signal gnxt_w		: unsigned (addr_width downto 0);
+	signal bnxt_w		: unsigned (addr_width downto 0);
+	signal gcnt_r		: unsigned (addr_width downto 0);
+	signal gcnt2_r		: unsigned (addr_width downto 0);
+	signal bcnt2_ar		: unsigned (addr_width downto 0);
+	signal bcnt_r		: unsigned (addr_width downto 0);
+	signal gnxt_r		: unsigned (addr_width downto 0);
+	signal bnxt_r		: unsigned (addr_width downto 0);
+
+	signal empty, full : std_logic;
+	signal write_inhibit, read_inhibit : std_logic;
+	signal winc, rinc : std_logic;
+
+	-- synthesis translate_off
+	signal diffw		: signed (addr_width downto 0);
+	signal diffr		: signed (addr_width downto 0);
+	-- synthesis translate_on
+
+begin
+
+	ptr_w		<= bcnt_w(addr_width-1 downto 0);
+	ptr_r		<= bcnt_r(addr_width-1 downto 0);
+	winc		<= we and (not write_inhibit);
+	rinc		<= re and (not read_inhibit);
+	fifo_full	<= write_inhibit;
+	fifo_empty	<= read_inhibit;
+	
+proc_write_inhibit:
+	process(rst, clk_w)
+	begin
+		if rst = '1' then
+			write_inhibit	<= '0';
+		elsif rising_edge(clk_w) then
+			write_inhibit	<= full;
+		end if;
+	end process;
+	
+proc_read_inhibit:
+	process(rst, clk_r)
+	begin
+		if rst = '1' then
+			read_inhibit	<= '1';
+		elsif rising_edge(clk_r) then
+			read_inhibit	<= empty;
+		end if;
+	end process;
+
+proc_sync_grptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			gcnt2_r <= p2;
+			p2 := p1;
+			p1 := gcnt_r;
+		end if;
+	end process;
+
+proc_ptr_gwptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			gcnt2_w <= p2;
+			p2 := p1;
+			p1 := gcnt_w;
+		end if;
+	end process;
+	
+proc_status_full:
+	process(gnxt_w, gcnt2_r)
+	begin
+		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
+			full <= '1';
+		else
+			full <= '0';
+		end if;
+	end process;
+
+proc_status_empty:
+	process(gnxt_r, gcnt2_w)
+	begin
+		if (gnxt_r = gcnt2_w) then
+			empty <= '1';
+		else
+			empty <= '0';
+		end if;
+	end process;
+	
+proc_sync_arptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			bcnt2_ar <= p2;
+			p2 := p1;
+			p1 := bcnt_r;
+		end if;
+	end process;
+
+proc_ptr_awptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			bcnt2_aw <= p2;
+			p2 := p1;
+			p1 := bcnt_w;
+		end if;
+	end process;
+	
+proc_status_almost_full:
+	process(rst, clk_w)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffw <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_afull <= '0';
+			diff := (others => '0');
+		elsif rising_edge(clk_w) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk_r)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffr <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_aempty <= '1';
+			diff := (others => '0');
+		elsif rising_edge(clk_r) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
+		end if;
+	end process;
+
+inst_gray_counter_w : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_w,
+		ce			=> winc, 
+		bcnt		=> bcnt_w,
+		bnxt		=> bnxt_w,
+		gcnt		=> gcnt_w,
+		gnxt		=> gnxt_w
+	);
+
+inst_gray_counter_r : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_r,
+		ce			=> rinc, 
+		bcnt		=> bcnt_r,
+		bnxt		=> bnxt_r,
+		gcnt		=> gcnt_r,
+		gnxt		=> gnxt_r
+	);
+
+end Behavioral;
+

lib/FIFO/src/dpram.vhd

@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram;
+
+architecture Behavioral of dpram is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/FIFO/src/fifo_ctrl_pkg.vhd

@@ -0,0 +1,46 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package fifo_ctrl_pkg is
+
+	-- Constants
+	-- Types
+	
+	-- Functions
+	function bin2gray(xb : unsigned) return unsigned;
+	function gray2bin(xg : unsigned) return unsigned;
+
+end fifo_ctrl_pkg;
+
+package body fifo_ctrl_pkg is
+
+	function bin2gray(xb : unsigned) return unsigned is
+	variable xg : unsigned(xb'left downto xb'right);
+	begin
+	
+    	xg(xg'left) := xb(xb'left);
+		for i in 1 to xb'left loop
+			xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
+		end loop;
+	
+		return xg;
+	end bin2gray;
+	
+	function gray2bin(xg : unsigned) return unsigned is
+	variable xb : unsigned(xg'left downto xg'right);
+	begin
+
+     	xb(xb'left) := xg(xg'left);
+		for i in 1 to xg'left loop
+			xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
+		end loop;
+		
+		return xb;
+	end gray2bin;
+
+end fifo_ctrl_pkg;
+

lib/FIFO/src/fifo_sync.vhd

@@ -52,17 +52,21 @@ end fifo_sync;
 
 architecture Behavioral of fifo_sync is
 	
-	signal mem_we		: STD_LOGIC;
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
 	signal ptr_w		: unsigned (addr_width-1 downto 0);
 	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: STD_LOGIC;
 	signal empty		: STD_LOGIC;
 	signal almost_full	: STD_LOGIC;
 	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
 	
 begin
 
-	mem_we <= we;
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
 	fifo_full	<= full;
 	fifo_empty	<= empty;
 	fifo_afull	<= almost_full;
@@ -85,12 +89,14 @@ begin
 		ptr_r			=>	ptr_r,
 		fifo_full		=>	full,
 		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
 		fifo_afull		=>	almost_full,
 		fifo_aempty		=>	almost_empty
 
 	);
 
-	inst_dpram_1w1r: entity work.dpram_1w1r_dist
+	inst_dpram_1w1r: entity work.dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> addr_width,
 		data_width	=> data_width
@@ -98,9 +104,9 @@ begin
 	PORT MAP(
 		clka		=> clk,
 		clkb		=> clk,
-		en_a		=> '1',
-		en_b		=> '1',
-		we_a		=> mem_we,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
 		addr_a		=> ptr_w,
 		addr_b		=> ptr_r,
 		din_a		=> data_w,

lib/FIFO/src/fifo_sync_dist.vhd

@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync_dist is
+	Generic (
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		fifo_full	: out STD_LOGIC;
+		fifo_empty	: out STD_LOGIC;
+		fifo_afull	: out STD_LOGIC;
+		fifo_aempty	: out STD_LOGIC;
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
+	);
+end fifo_sync_dist;
+
+architecture Behavioral of fifo_sync_dist is
+	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
+	signal full			: STD_LOGIC;
+	signal empty		: STD_LOGIC;
+	signal almost_full	: STD_LOGIC;
+	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
+	
+begin
+
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
+
+	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> addr_width,
+		almost_full_thresh	=> almost_full_thresh,
+		almost_empty_thresh	=> almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
+
+	);
+
+	inst_dpram_1w1r: entity work.dpram_1w1r_dist
+	GENERIC MAP (
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+	
+end Behavioral;
+

lib/FIFO/src/gray_counter.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity gray_counter is
+	Generic (
+		width : natural := 3;
+		init_value : natural := 0
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		bcnt		: out unsigned (width-1 downto 0);
+		bnxt		: out unsigned (width-1 downto 0);
+		gcnt		: out unsigned (width-1 downto 0);
+		gnxt		: out unsigned (width-1 downto 0)
+	);
+end gray_counter;
+
+architecture Behavioral of gray_counter is
+
+	signal cntb : unsigned (width-1 downto 0);
+	signal nxtb : unsigned (width-1 downto 0);
+	signal cntg : unsigned (width-1 downto 0);
+	signal nxtg : unsigned (width-1 downto 0);
+
+begin
+
+	bnxt	<= nxtb;
+	gnxt	<= nxtg;
+
+	process(rst, clk, ce, cntb, nxtb)
+	begin
+		if rst = '1' then
+			cntb	<= to_unsigned(init_value, width);
+			nxtb	<= to_unsigned(init_value, width);
+			cntg	<= to_unsigned(init_value, width);
+			nxtg	<= to_unsigned(init_value, width);
+			bcnt	<= to_unsigned(init_value, width);
+			gcnt	<= to_unsigned(init_value, width);
+		else
+			if rising_edge(clk) then
+				bcnt	<= nxtb;
+				gcnt	<= nxtg;
+				cntb	<= nxtb;
+				cntg	<= nxtg;
+			end if;	
+			nxtg <= bin2gray(nxtb);
+			nxtb <= cntb;
+			if ce = '1' then
+				nxtb <= cntb + 1;
+			end if;	
+		end if;	
+	end process;
+
+end Behavioral;
+

lib/FIFO/src/sync_fifo_ctrl.vhd

@@ -0,0 +1,203 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity sync_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		we				: in  STD_LOGIC;
+		re				: in  STD_LOGIC;
+		ptr_w			: out unsigned (addr_width-1 downto 0);
+		ptr_r			: out unsigned (addr_width-1 downto 0);
+		fifo_pre_full	: out STD_LOGIC;
+		fifo_pre_empty	: out STD_LOGIC;
+		fifo_full		: out STD_LOGIC;
+		fifo_empty		: out STD_LOGIC;
+		fifo_afull		: out STD_LOGIC;
+		fifo_aempty		: out STD_LOGIC
+	);
+end sync_fifo_ctrl;
+
+architecture Behavioral of sync_fifo_ctrl is
+
+	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
+	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
+	signal empty, full : std_logic;
+	signal pre_empty, pre_full : std_logic;
+	signal was_write : std_logic;
+	signal write, read : std_logic;
+	signal diff : unsigned (addr_width downto 0);
+	
+begin
+
+	read	<= re and not empty;
+	write	<= we and not full;
+
+	fifo_full		<= full;
+	fifo_empty		<= empty;
+	fifo_pre_full	<= pre_full;
+	fifo_pre_empty	<= pre_empty;
+
+
+proc_diff_gen:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			diff <= (others => '0');
+		elsif rising_edge(clk) then
+			if write = '1' and read = '0' then
+				diff <= diff + 1;
+			elsif write = '0' and read = '1' then
+				diff <= diff - 1;
+			end if;
+		end if;
+	end process;
+
+proc_status_almost_full:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_afull <= '0';
+		elsif rising_edge(clk) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_aempty <= '1';
+		elsif rising_edge(clk) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_full_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			full <= '0';
+		elsif rising_edge(clk) then
+			full <= pre_full;
+		end if;
+	end process;
+	
+proc_empty_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			empty <= '1';
+		elsif rising_edge(clk) then
+			empty <= pre_empty;
+		end if;
+	end process;
+	
+proc_status_w:
+	process(was_write, pW_next, pR_next, pW, pR, write, read)
+	begin
+		if (pW_next = pR) and (write = '1' or was_write = '1') then
+			pre_full <= '1';
+		else
+			pre_full <= '0';
+		end if;
+		if (pR_next = pW) and (read = '1' or was_write = '0') then
+			pre_empty <= '1';
+		else
+			pre_empty <= '0';
+		end if;
+	end process;
+
+proc_flag_write:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			was_write <= '0';
+		elsif rising_edge(clk) then
+			if write = '1' then
+				was_write <= '1';
+			elsif read = '1' then
+				was_write <= '0';
+			end if;
+		end if;
+	end process;
+	
+proc_ptr_w:
+	process(rst, clk, pW, write, full)
+	begin
+		if rst = '1' then
+			pW <= to_unsigned(0, addr_width);
+			pW_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if write = '1' then 
+				pW <= pW_next;
+			end if;
+		end if;
+		pW_next <= pW;
+		if write = '1' then 
+			pW_next <= pW + 1;
+		end if;
+		ptr_w		<= pW;
+	end process;
+
+proc_ptr_r:
+	process(rst, clk, pR_next, pR, read, empty)
+	begin
+		if rst = '1' then
+			pR <= to_unsigned(0, addr_width);
+			pR_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if read = '1' then
+				pR <= pR_next;
+			end if;	
+		end if;
+		pR_next	<= pR;
+		if read = '1' then
+			pR_next	<= pR + 1;
+		end if;
+		ptr_r		<= pR_next;
+	end process;
+
+end Behavioral;
+

lib/FIFO/src/tb_async_fifo_ctrl.vhd

@@ -0,0 +1,176 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_async_fifo_ctrl IS
+END tb_async_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_async_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD_W 	: time := 10 ns;
+	constant PERIOD_R 	: time := 20 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk_w				: STD_LOGIC := '0';
+	signal clk_r				: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.async_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk_w,
+		clk_r		=>	clk_r,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk_w,
+		clkb		=> clk_r,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk_w : PROCESS
+	BEGIN
+		clk_w <= not clk_w;
+		wait for PERIOD_W/2;
+	END PROCESS;
+
+ 	tb_clk_r : PROCESS
+	BEGIN
+		clk_r <= not clk_r;
+		wait for PERIOD_R/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD_W;
+		rst			<= '0';
+		wait for 5*PERIOD_W;
+		write_en <= '1';
+		wait for 15*PERIOD_W;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 15*PERIOD_R;
+		read_en <= '1';
+		
+		wait; 
+		
+	END PROCESS;
+	
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+	
+ 	tb_w : PROCESS(rst, clk_w)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk_w) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+	
+ 	tb_r : PROCESS(rst, clk_r)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk_r) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata2 = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;

lib/FIFO/src/tb_gray_counter.vhd

@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_gray_counter
+-- Module Name:   tb_gray_counter.vhd
+-- Project Name:  gray_counter package
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+ENTITY tb_gray_counter IS
+END tb_gray_counter;
+
+ARCHITECTURE behavior OF tb_gray_counter IS 
+
+	constant PERIOD		: time := 10 ns;
+	constant WIDTH		: integer := 3;
+
+	--Signals
+	signal gcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal gnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal rst			: STD_LOGIC := '1';
+	signal clk			: STD_LOGIC := '0';
+	signal ce			: STD_LOGIC := '0';
+
+BEGIN
+
+inst_gray_counter : entity work.gray_counter
+	generic map (width => WIDTH)
+	port map (
+		rst			=> rst,
+		clk			=> clk,
+		ce			=> ce, 
+		bcnt		=> bcnt,
+		bnxt		=> bnxt,
+		gcnt		=> gcnt,
+		gnxt		=> gnxt
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_counter : PROCESS
+ 	
+	BEGIN
+
+		wait for 4*PERIOD;
+		rst <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		wait for 3*PERIOD;
+		ce <= '0';
+		wait for 4*PERIOD;
+		ce <= '1';
+		wait for 1*PERIOD;
+		ce <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		
+		wait;
+		
+	END PROCESS;
+
+END behavior;

lib/FIFO/src/tb_sync_fifo_ctrl.vhd

@@ -0,0 +1,221 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_sync_fifo_ctrl IS
+END tb_sync_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD 	: time := 10 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk					: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD;
+		rst			<= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 1*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 3*PERIOD;
+		write_en <= '1';
+		wait for 4*PERIOD;
+		write_en <= '0';
+		wait for 17*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 25*PERIOD;
+		read_en <= '0';
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 7*PERIOD;
+		read_en <= '1';
+		wait for 15*PERIOD;
+		read_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+
+ 	tb_w : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+
+ 	tb_r : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;

lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd

@@ -43,9 +43,7 @@ entity ddr_phy is
 		phy_ctrl		: in  phy_ctrl_t;
 		part_ctrl		: in  part_ctrl_t;
 		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_dm_wr_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_dm_rd_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_dm_rd_out	: out unsigned(SDR_DM_WIDTH-1 downto 0);
+		sdr_dm			: in unsigned(SDR_DM_WIDTH-1 downto 0);
 		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
 		sdr_data_vld	: out STD_LOGIC;
 		sdr_data_req_w	: out STD_LOGIC;
@@ -83,9 +81,6 @@ architecture tech of ddr_phy is
 	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
 	signal u_tag_pipe : u_tag_array_t;
 	
-	type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal dm_out_pipe : dm_out_array_t;
-
 begin
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
@@ -102,19 +97,6 @@ utag_pipe:
 		end if;
 	end process;
 
-dmout_pipe:
-	process(sys_rst, sys_clk0)
-	begin
-		if rising_edge(sys_clk0) then
-			for i in dm_out_pipe'length-1 downto 1 loop
-				dm_out_pipe(i) <= dm_out_pipe(i-1);
-			end loop;	
-			if phy_ctrl.utag_we = '1' then
-				dm_out_pipe(0) <= sdr_dm_rd_in;
-			end if;	
-		end if;
-	end process;
-
 WE_REGISTER:
 	process(sys_rst, sys_clk0)
 	begin
@@ -239,8 +221,8 @@ gen_ddr_dm_out:
 			Q	=> part_dm(n),							-- 1-bit DDR output
 			C	=> sys_clk270,							-- 1-bit clock input
 			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_dm_wr_in(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_dm_wr_in(n),						-- 1-bit data input (negative edge)
+			D1	=> sdr_dm(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_dm(n),						-- 1-bit data input (negative edge)
 			R	=> '0',									-- 1-bit reset input
 			S	=> '0' 									-- 1-bit set input
 		);
@@ -368,7 +350,6 @@ misc_flags_and_data_out:
 			sdr_data_r		<= data_reg_r;
 			if p(3) = '1' then
 				u_tag_rd		<= u_tag_pipe(4);
-				sdr_dm_rd_out	<= dm_out_pipe(4);
 			end if;	
 			if phy_ctrl.we = '1' then
 				u_tag_wr		<= u_tag_pipe(0);

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd

@@ -83,14 +83,12 @@ architecture struct of sdram_ctrl_frontend_wb is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
 	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_dm_rd_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_dm_rd_out		: unsigned(SDR_DM_WIDTH-1 downto 0);
 	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
 	signal rdy				: std_logic;
 
-	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + 4;
+	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
 	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
 	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
 	signal cat_fifo_re				: std_logic;
@@ -109,8 +107,8 @@ architecture struct of sdram_ctrl_frontend_wb is
 --	signal write_fifo_almost_full	: std_logic;
 --	signal write_fifo_almost_empty	: std_logic;
 
-	signal read_fifo_din			: unsigned(35 downto 0);
-	signal read_fifo_dout			: unsigned(35 downto 0);
+	signal read_fifo_din			: unsigned(31 downto 0);
+	signal read_fifo_dout			: unsigned(31 downto 0);
 	signal read_fifo_re				: std_logic;
 	signal read_fifo_we				: std_logic;
 	signal read_fifo_full			: std_logic;
@@ -120,22 +118,18 @@ architecture struct of sdram_ctrl_frontend_wb is
 
 	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
 	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
-	alias dm_rd_fifo_in is cat_fifo_din(4-1 downto 0);
+	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
 	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
 	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
-	alias dm_rd_fifo_out is cat_fifo_dout(4-1 downto 0);
+	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
 
-	alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-4);
-	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 0);
-	alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-4);
-	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 0);
+	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
+	alias write_fifo_dm_in is write_fifo_din(3 downto 0);
+	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
+	alias write_fifo_dm_out is write_fifo_dout(3 downto 0);
 
-	alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-4);
-	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-4-1 downto 0);
-	alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-4);
-	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-4-1 downto 0);
+	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
+	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
 	
 begin 
    
@@ -165,7 +159,7 @@ begin
 	GENERIC MAP
 	(
 		addr_width	=> fifo_depth,
-		data_width	=> 36
+		data_width	=> write_fifo_din'length
 	)
 	PORT MAP
 	(
@@ -186,7 +180,7 @@ begin
 	GENERIC MAP
 	(
 		addr_width	=> fifo_depth,
-		data_width	=> 36
+		data_width	=> read_fifo_din'length
 	)
 	PORT MAP
 	(
@@ -231,9 +225,7 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm_wr_in,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
+		u_dm				=> u_dm_wr_in,
 		
 		-- SDRAM signals
 		sd_clk_p			=> sd_clk_p,
@@ -253,6 +245,8 @@ begin
    
 ------------------------------------------------------------------------------------------
 	SRDY_O				<= rdy;
+	ACK_O				<= not (read_fifo_empty);
+	DAT_O				<= read_fifo_data_out;
 	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
 	write_fifo_we 		<= STB_I and WE_I and rdy;
 	write_fifo_data_in	<= DAT_I;
@@ -260,34 +254,19 @@ begin
 	cat_fifo_we			<= STB_I and rdy;
 	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
 	addr_fifo_in		<= ADDR_I(24 downto 2) & "0";
-	dm_rd_fifo_in		<= not SEL_I;
-	tag_fifo_in			<= (others=>'0');
+	tag_fifo_in			<= "000" & ADDR_I(25);
 	
 	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
 	u_cmd				<= cmd_fifo_out;
 	u_addr				<= addr_fifo_out;
-	u_dm_rd_in			<= dm_rd_fifo_out & dm_rd_fifo_out;
-	u_dm_wr_in			<= write_fifo_dm_out & write_fifo_dm_out;
+	u_dm_wr_in			<= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111");
 	u_tag_in			<= tag_fifo_out;
+	u_data_w			<= write_fifo_data_out & write_fifo_data_out;
 	
 	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
 	cat_fifo_re			<= u_cmd_we;
-	u_data_w			<= write_fifo_data_out & write_fifo_data_out;
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 	read_fifo_we		<= u_data_vld;
-	read_fifo_data_in	<= u_data_r(31 downto 0);	
-	read_fifo_dm_in		<= u_dm_rd_out(3 downto 0);
-
-data_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			ACK_O		<= '0';
-			if MRDY_I = '1' then
-				ACK_O		<= write_fifo_we or (CYC_I and not (WE_I or read_fifo_empty));
-				DAT_O		<= read_fifo_data_out;
-			end if;
-		end if;
-	end process;
+	read_fifo_data_in	<= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32);	
 
 end architecture struct;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd

@@ -53,9 +53,7 @@ entity sdram_ctrl_top is
 		u_cmd				: in  user_cmd_t;
 		u_cmd_we			: in  STD_LOGIC;
 		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		u_dm_wr_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_dm_rd_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_dm_rd_out			: out unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_dm				: in unsigned(SDR_DM_WIDTH-1 downto 0);
 		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
 		
 		-- SDRAM signals
@@ -225,9 +223,7 @@ begin
 		sdr_data_req_w	=> u_data_req_w,
 		sdr_data_req_r	=> u_data_req_r,
 		sdr_data_w		=> u_data_wr,
-		sdr_dm_wr_in	=> u_dm_wr_in,
-		sdr_dm_rd_in	=> u_dm_rd_in,
-		sdr_dm_rd_out	=> u_dm_rd_out,
+		sdr_dm			=> u_dm,
 		sdr_data_r		=> u_data_rd,
 		sdr_data_vld	=> u_data_vld,
 		part_clk_p		=> sd_clk_p,

lib/misc/async_port_wb.vhd

@@ -0,0 +1,290 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.3 2008-10-12 14:12:14 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.sys_types.all;
+
+	------------------------------------------------------------------
+entity async_port_wb is
+	Generic
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		async_timespec	: async_timespec_t
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_rst	: out std_logic
+	);
+end async_port_wb;
+
+architecture Behavioral of async_port_wb is
+
+	type async_t is record
+		cs		: std_logic;
+		wr		: std_logic;
+		rd		: std_logic;
+		rst		: std_logic;
+		drive_d	: std_logic;
+	end record;
+	
+	type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
+	
+	signal s, sn		: async_state_t;
+	signal as			: async_t;
+	signal ack			: std_logic;
+	signal cc_rst		: std_logic;
+	signal cycle_cnt	: natural range 0 to 15;
+	signal cycle_reload	: natural range 0 to 15;
+	signal rdy			: std_logic;
+	signal rdyo			: std_logic;
+	signal en			: std_logic;
+	signal data_reg		: unsigned(data_width-1 downto 0);
+
+	------------------------------------------------------------------
+	begin
+
+	SRDY_O	<= CYC_I and rdyo;
+	en		<= CYC_I and STB_I;
+	
+	proc_cycle_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if cc_rst = '1' then
+				cycle_cnt <= cycle_reload;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt <= cycle_cnt - 1;
+			end if;
+		end if;
+	end process;
+	
+	------------------------------------------------------------------
+	proc_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				s <= start;
+			else
+				s <= sn;
+			end if;
+		end if;
+	end process;
+	
+	proc_state:
+	process(s, cycle_cnt, en, WE_I)
+	begin
+		
+		cycle_reload	<= async_timespec.ncyc_pulse_rst;
+		cc_rst			<= '0';
+		as.rst			<= '0';
+		as.cs			<= '0';
+		as.wr			<= '0';
+		as.rd			<= '0';
+		as.drive_d		<= '0';
+		ack				<= '0';
+		rdy				<= '0';
+		
+		sn	<= s;
+		case s is
+		
+		when start =>
+			cc_rst	<= '1';
+			sn		<= reset;
+		when reset =>
+			as.rst	<= '1';
+			if cycle_cnt = 0 then
+				sn	<= idle;
+			end if;
+		when idle =>
+			rdy			<= '1';
+			if en = '1' then
+				as.cs			<= '1';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_access-1;
+				if WE_I = '0' then
+					sn				<= leadin_rd;
+				else
+					sn				<= leadin_wr;
+				end if;
+			end if;
+
+		when leadin_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_rd-1;
+				as.rd			<= '1';
+				sn				<= read;
+			end if;
+
+		when leadin_wr =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_wr-1;
+				as.wr			<= '1';
+				as.drive_d		<= '1';
+				sn				<= write;
+			end if;
+	
+		when read =>
+			as.cs		<= '1';
+			as.rd		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+--				as.rd			<= '0';
+				sn				<= leadout_rd;
+				ack				<= '1';
+			end if;
+				
+		when write =>
+			as.drive_d	<= '1';
+			as.cs		<= '1';
+			as.wr		<= '1';
+			if cycle_cnt = 0 then
+				as.wr			<= '0';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+				sn				<= leadout_wr;
+--				ack				<= '1';
+			end if;
+
+		when leadout_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when leadout_wr =>
+			as.cs		<= '1';
+			as.drive_d	<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when release =>
+			if cycle_cnt = 0 then
+				sn				<= idle;
+			end if;
+
+		when others =>
+			sn <= idle;
+			
+		end case;		
+	end process;
+
+	------------------------------------------------------------------
+	output_ctrl:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_cs	<= (not async_timespec.pol_cs) xor as.cs;
+			async_wr	<= (not async_timespec.pol_we) xor as.wr;
+			async_rd	<= (not async_timespec.pol_oe) xor as.rd;
+			async_rst	<= (not async_timespec.pol_rst) xor as.rst;
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	din_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if as.rd = '1' then
+				DAT_O(data_width-1 downto 0) 	<= async_d;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_addr:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				async_a		<= (others => '0');
+			elsif en = '1' and rdy = '1' then
+				async_a 	<= ADDR_I(addr_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if en = '1' and rdy = '1' then
+				data_reg 	<= DAT_I(data_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_SRDY:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				rdyo 	<= '1';
+			elsif en = '1' then
+				rdyo 	<= rdy and not rdyo;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_ACK:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O 	<= '0';
+			else
+				ACK_O 	<= ack;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_data:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_d 	<= (others => 'Z');
+			if as.drive_d = '1' then
+				async_d 	<= data_reg;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+
+end Behavioral;

lib/misc/clockgen_virtex4.vhd

@@ -0,0 +1,236 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Clock generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee, work;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clockgen is
+	generic
+	(
+		sys1_phaseshift : integer := 0;
+		frequency_hz : integer := 100E6
+	);
+	port 
+	(
+		-- Clocks and Reset
+		rst				: in std_logic;   -- external async reset, low active
+		clk_in			: in std_logic;   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		: in std_logic;   -- feedback clock
+		sys1_clk0_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	: out std_logic;  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	: out std_logic;  -- System clock #0, dcm#0 output 270°
+		locked_out		: out std_logic;  -- DCM locked status
+		error_out		: out std_logic   -- indicates DCM Errors
+	);
+end;
+
+architecture tech of clockgen is
+
+	constant CLKIN_PER 				: real := real(1000E6/frequency_hz);
+
+	signal locked					: unsigned(1 downto 0);
+	signal dcm_rst					: unsigned(1 downto 0);
+	signal sys1_clk0				: std_logic;
+	signal sys1_clk270				: std_logic;
+	signal sys1_clk0_bufg			: std_logic;
+	signal sys1_clk270_bufg			: std_logic;
+	signal sys0_clk0					: std_logic;
+	signal sys0_clk270				: std_logic;
+	signal sys0_clk0_bufg			: std_logic;
+	signal sys0_clk270_bufg			: std_logic;
+	signal dcm1_locked, dcm2_locked	: unsigned(2 downto 0);
+	signal cnt_q 					: unsigned(4 downto 0);
+
+	type STATE_TYPE is (s0, s1, s2, s3, s4);
+	signal state_q : STATE_TYPE;
+
+begin 
+
+	sys1_clk0_out	<= sys1_clk0_bufg;
+	sys1_clk270_out	<= sys1_clk270_bufg;
+	sys0_clk0_out	<= sys0_clk0_bufg;
+	sys0_clk270_out	<= sys0_clk270_bufg;
+
+bufg11: bufg
+	port map
+	(
+		o  => sys0_clk0_bufg,  
+		i  => sys0_clk0
+	);
+
+bufg12: bufg
+	port map (
+		o  => sys0_clk270_bufg,  
+		i  => sys0_clk270
+	);
+
+bufg13: bufg
+	port map
+	(
+		o  => sys1_clk0_bufg,  
+		i  => sys1_clk0
+	);
+
+bufg14: bufg
+	port map (
+		o  => sys1_clk270_bufg,  
+		i  => sys1_clk270
+	);
+
+	-------------------------------------------------------------------------------------------------------
+	-- Clock generation
+	-------------------------------------------------------------------------------------------------------
+   
+inst_DCM_BASE_0 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys0_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys0_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(0),     -- DCM LOCK status output
+		CLKFB => clk_fb_in,       -- DCM clock feedback
+		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(0)            -- DCM asynchronous reset input
+	);
+
+	inst_DCM_BASE_1 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys1_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys1_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(1),     -- DCM LOCK status output
+		CLKFB => sys1_clk0_bufg,       -- DCM clock feedback
+		CLKIN => clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(1)            -- DCM asynchronous reset input
+	);
+
+	dcm_rst(1) <= not locked(0);
+	
+dcm_fsm:
+	process(rst, clk_in)
+	begin
+		if rst = '1' then
+			state_q <= s0;
+			dcm_rst(0) <= '0';
+			cnt_q <= "11111";
+			error_out <= '0';
+			locked_out <= '0';
+			dcm1_locked <= (others => '0');
+			dcm2_locked <= (others => '0');
+		elsif rising_edge(clk_in) then
+			case state_q is
+			when s0 =>
+				state_q <= s1;
+
+			when s1 =>
+			cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '1';
+					state_q <= s2;
+				end if;
+
+			when s2 =>
+				cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '0';
+					state_q <= s3;
+				end if;
+
+			when s3 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					state_q <= s4;
+					error_out <= '0';
+				end if;
+
+			when s4 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					locked_out <= '1';
+				else
+					error_out <= '1';
+				end if;
+			end case;
+
+			-- synchronize 'dcm1_locked'
+			dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
+			dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
+
+		end if;
+	end process;
+
+end architecture tech;
+
+

lib/misc/debounce.vhd

@@ -0,0 +1,91 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    19:34:24 10/23/05
+-- Design Name:    
+-- Module Name:    debounce - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+    Generic ( ncyc_latency : integer := 100);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+
+type debounce_state_t is (init_st, wait_st, rel_st);
+signal debounce_cs : debounce_state_t;
+signal debounce_ns : debounce_state_t;
+signal count       : integer range 0 to ncyc_latency;
+signal input_last	 : std_logic;
+
+begin
+
+	debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
+	begin
+		if (rst = '1') then
+			count <= 0;
+			output <= input;
+			input_last <= input;
+		else
+			if rising_edge(clk) then
+				debounce_cs <= debounce_ns;
+				if (debounce_cs = wait_st) then
+					if (count /= 0) then
+						count <= count - 1;
+					end if;
+				else
+					count <= ncyc_latency;
+					if	(debounce_cs = rel_st) then
+						output <= input;
+						input_last <= input;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
+	begin
+		debounce_ns <= debounce_cs;
+		case debounce_cs is
+			when init_st =>
+				if (input /= input_last) then
+					debounce_ns <= wait_st;
+				end if;
+			when wait_st =>
+				if (count = 0) then
+					debounce_ns <= rel_st;
+				end if;
+			when others => 
+				debounce_ns <= init_st;
+		end case;
+	end process;
+
+end Behavioral;

lib/misc/debounce2.vhd

@@ -0,0 +1,142 @@
+------------------------------------------------- 
+-- Signal Debouncer
+-- Jeff Bazinet
+-- February 14, 2002
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+
+library ieee; 
+use ieee.std_logic_1164.all;
+library lpm;
+use lpm.lpm_components.lpm_counter;
+
+
+entity debounce is
+	generic(BUFFER_WIDTH:	positive:= 30;
+		CLOCK_DIV: 	positive:= 15
+		);
+	port(	clock:		in std_logic;
+		reset:		in std_logic;
+		signal_in:	in std_logic;
+		signal_out:	out std_logic
+		);
+end entity debounce;
+
+
+architecture rtl of debounce is 
+
+	---------------------------------------------------------------
+	-- SIGNAL DECLARATION
+	---------------------------------------------------------------
+	
+	-- General
+	signal reset_n:	std_logic;
+	
+	-- SLOW CLOCK GENERATION
+	signal clock_reg:	std_logic_vector(CLOCK_DIV-1 downto 0);
+	signal clock_reg_high:	std_logic_vector(CLOCK_DIV-1 downto 1);	
+	signal clock_slow:	std_logic;
+	signal clock_slow_wire:	std_logic;
+	
+	-- DATA BUFFER FILL
+	signal counter_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	signal data_buffer_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	
+	-- CHECK FOR DEBOUNCE STABILITY
+	signal stable:	std_logic;
+	signal stable_old:	std_logic;
+	signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	
+	-- PUSH BUTTON ENABLE
+	signal button_pushed:	std_logic;
+	
+	begin
+	
+	---------------------------------------------------------------
+	-- SLOW CLOCK GENERATION
+	---------------------------------------------------------------
+	
+	COUNTER_1: lpm_counter
+		generic map (lpm_width => CLOCK_DIV)
+		port map (
+			clock => clock,
+			sclr => reset_n,
+			cout => clock_slow_wire
+			);
+			
+	process (clock) is
+		begin
+		
+		clock_slow <= clock_slow_wire;
+
+		end process;
+		
+	---------------------------------------------------------------
+	-- DATA BUFFER FILL
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			data_buffer_reg <= (others => '1');
+		elsif rising_edge(clock_slow) then
+			data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
+		end if;
+	
+	end process;
+	
+	---------------------------------------------------------------
+	-- CHECK FOR DEBOUNCE STABILITY
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			stable <= '0';
+			stable_old <= '0';
+			stable_state_reg <= (others => '0');
+		elsif rising_edge(clock) then
+			if (data_buffer_reg = stable_state_reg) then
+				stable <= '1';
+				stable_state_reg <= (others => '0');
+			else
+				stable <= '0';
+			end if;
+			stable_old <= stable;
+		end if;
+	
+	end process;
+	 
+	---------------------------------------------------------------
+	-- PUSH BUTTON ENABLE
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			button_pushed <= '0';
+		elsif rising_edge(clock) then
+			if (stable_old = '0' and stable = '1') then
+				button_pushed <= '1';
+			else
+				button_pushed <= '0';
+			end if;	
+		end if;
+	
+	end process;
+	
+	---------------------------------------------------------------
+	---------------------------------------------------------------
+	 
+	signal_out <= button_pushed;
+	reset_n <= not reset;
+	
+end rtl; 

lib/misc/dpram_1w1r.vhd

@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r;
+
+architecture Behavioral of dpram_1w1r is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_1w1r_dist.vhd

@@ -0,0 +1,84 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r_dist is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r_dist;
+
+architecture Behavioral of dpram_1w1r_dist is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+	attribute ram_style : string;
+	attribute ram_style of RAM: signal is "distributed";
+	
+begin
+
+process (clka)
+	begin
+	if clka'event and clka = '1' then
+		if en_a = '1' then
+			if we_a = '1' then
+				RAM(to_integer(addr_a)) <= din_a;
+			end if;
+		end if;
+	end if;
+end process;
+
+process (clkb)
+	begin
+	if clkb'event and clkb = '1' then
+		if en_b = '1' then
+			dout_b <= RAM(to_integer(addr_b));
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r;
+
+architecture Behavioral of dpram_2w2r is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if en_a = '1' then
+		dout_a <= RAM(to_integer(addr_a));
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) := din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) := din_b;
+		end if;
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r_virtex4.vhd

@@ -0,0 +1,211 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity dpram_2w2r is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r;
+
+architecture Structure of dpram_2w2r is
+
+	signal do_a	: std_logic_vector(31 downto 0);
+	signal do_b	: std_logic_vector(31 downto 0);
+	signal di_a	: std_logic_vector(31 downto 0);
+	signal di_b	: std_logic_vector(31 downto 0);
+	signal ad_a	: std_logic_vector(14 downto 0);
+	signal ad_b	: std_logic_vector(14 downto 0);
+	signal wr_a	: std_logic_vector(3 downto 0);
+	signal wr_b	: std_logic_vector(3 downto 0);
+
+begin
+
+-- RAMB16: 16k+2k Parity Paramatizable block RAM
+-- Virtex-4
+-- Xilinx HDL Libraries Guide, version 9.1i
+RAMB16_inst : RAMB16
+generic map
+(
+	DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
+	DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
+	INIT_A => X"000000000", -- Initial values on A output port
+	INIT_B => X"000000000", -- Initial values on B output port
+	INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
+	INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
+	RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+	RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+	READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+	READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+	SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
+
+	-- "GENERATE_X_ONLY" or "NONE"
+	SRVAL_A => X"000000000", -- Port A output value upon SSR assertion
+	SRVAL_B => X"000000000", -- Port B output value upon SSR assertion
+	WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+	WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+	WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+	WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+	
+	-- The following INIT_xx declarations specify the initial contents of the RAM
+	INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	
+	-- The next set of INITP_xx are for the parity bits
+	INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
+)
+port map 
+(
+	CASCADEOUTA => open, -- 1-bit cascade output
+	CASCADEOUTB => open, -- 1-bit cascade output
+	DOA => do_a, -- 32-bit A port Data Output
+	DOB => do_b, -- 32-bit B port Data Output
+	DOPA => open, -- 4-bit A port Parity Output
+	DOPB => open, -- 4-bit B port Parity Output
+	ADDRA => ad_a, -- 15-bit A Port Address Input
+	ADDRB => ad_b, -- 15-bit B Port Address Input
+	CASCADEINA => '0', -- 1-bit cascade A input
+	CASCADEINB => '0', -- 1-bit cascade B input
+	CLKA => clk_a, -- Port A Clock
+	CLKB => clk_b, -- Port B Clock
+	DIA => di_a, -- 32-bit A port Data Input
+	DIB => di_b, -- 32-bit B port Data Input
+	DIPA => "0000", -- 4-bit A port parity Input
+	DIPB => "0000", -- 4-bit B port parity Input
+	ENA => en_a, -- 1-bit A port Enable Input
+	ENB => en_b, -- 1-bit B port Enable Input
+	REGCEA => '0', -- 1-bit A port register enable input
+	REGCEB => '0', -- 1-bit B port register enable input
+	SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
+	SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
+	WEA => wr_a, -- 4-bit A port Write Enable Input
+	WEB => wr_b -- 4-bit B port Write Enable Input
+);
+-- End of RAMB16_inst instantiation
+	
+	dout_a	<= unsigned(do_a(7 downto 0));
+	dout_b	<= unsigned(do_b(7 downto 0));
+	di_a	<= X"000000" & std_logic_vector(din_a);
+	di_b	<= X"000000" & std_logic_vector(din_b);
+	ad_a	<= '0' & std_logic_vector(addr_a) & "000";
+	ad_b	<= '0' & std_logic_vector(addr_b) & "000";
+	wr_a	<= (3 downto 0 => we_a);
+	wr_b	<= (3 downto 0 => we_b);
+	
+end Structure;
+

lib/misc/lcd_port.vhd

@@ -0,0 +1,69 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+	------------------------------------------------------------------
+entity lcd_port is
+	Port (
+			rst			: in std_logic;
+			clk			: in std_logic;
+			we			: in std_logic;
+			din			: in unsigned(7 downto 0);
+			dout		: out unsigned(7 downto 0);
+			lcd_d		: inout unsigned(3 downto 0);
+			lcd_e		: out std_logic;
+			lcd_rs		: out std_logic;
+			lcd_rw		: out std_logic
+		);
+	end lcd_port;
+
+architecture Behavioral of lcd_port is
+
+	constant clcd_e : integer := 7;
+	constant clcd_rs : integer := 6;
+	constant clcd_rw : integer := 5;
+	
+	type lcd_t is record
+		d	: unsigned(3 downto 0);
+		e	: std_logic;
+		rs	: std_logic;
+		rw	: std_logic;
+	end record;
+	
+	------------------------------------------------------------------
+	begin
+
+	proc_lcd_port:
+	process(rst, clk)
+	variable vlcd : lcd_t;
+	begin
+		if (rst = '1') then
+			dout	<= (others => '0');
+			vlcd.d	:= (others => '0');
+			vlcd.e	:= '0';
+			vlcd.rw	:= '1';
+			vlcd.rs	:= '0';
+		elsif rising_edge(clk) then
+			dout <= unsigned("0000" & lcd_d);
+			if we = '1' then
+				vlcd.d	:= din(3 downto 0);
+				vlcd.e	:= din(clcd_e);
+				vlcd.rs	:= din(clcd_rs);
+				vlcd.rw	:= din(clcd_rw);
+			end if;
+		end if;	
+		if vlcd.rw = '0' then	
+			lcd_d <= unsigned(vlcd.d);
+		else
+			lcd_d <= (others => 'Z');
+		end if;
+		lcd_e	<= vlcd.e;
+		lcd_rs	<= vlcd.rs;
+		lcd_rw	<= vlcd.rw;
+	end process;
+	------------------------------------------------------------------
+
+end Behavioral;

lib/misc/oneshot.vhd

@@ -0,0 +1,223 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    21:52:19 10/22/05
+-- Design Name:    
+-- Module Name:    oneshot - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+--	COMPONENT oneshot
+--	GENERIC (mode : integer);
+--	PORT(
+--		rst : IN std_logic;
+--		clk : IN std_logic;
+--		input : IN std_logic;          
+--		output : OUT std_logic
+--		);
+--	END COMPONENT;
+--
+-- Instantation Template
+--
+--	oneshot_int: oneshot 
+--	GENERIC MAP (
+--		mode => 1)		
+--	PORT MAP(
+--		rst => ,
+--		clk => ,
+--		input => ,
+--		output => 
+--	);
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity oneshot is
+    Generic ( mode : integer range 0 to 2 := 1);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end oneshot;
+
+architecture Behavioral of oneshot is
+
+type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
+
+signal shot_cs : shot_state_t;
+signal shot_ns : shot_state_t;
+
+begin
+
+mode_0:
+if mode = 0 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= shot_neg_st;
+				end if;
+			when shot_neg_st =>
+				shot_ns <= release_neg_st;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= release_pos_st;
+				end if;
+			when others => null;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+mode_1:
+if mode = 1 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when shot_pos_st =>
+				shot_ns <= release_pos_st;
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= release_neg_st;
+				end if;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= shot_pos_st;
+				end if;
+			when others => null;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when shot_pos_st =>
+				shot_ns <= release_pos_st;
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= shot_neg_st;
+				end if;
+			when shot_neg_st =>
+				shot_ns <= release_neg_st;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= shot_pos_st;
+				end if;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+			
+
+end Behavioral;

lib/misc/pkg_template.vhd

@@ -0,0 +1,18 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package template_pkg is
+	-- Constants
+	-- Types
+	-- Functions
+
+end template_pkg;
+
+package body template_pkg is
+
+end template_pkg;
+

lib/misc/singleshot.vhd

@@ -0,0 +1,155 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    21:52:19 10/22/05
+-- Design Name:    
+-- Module Name:    singleshot - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+--	COMPONENT singleshot
+--	GENERIC (mode : integer);
+--	PORT(
+--		rst : IN std_logic;
+--		clk : IN std_logic;
+--		input : IN std_logic;          
+--		output : OUT std_logic
+--		);
+--	END COMPONENT;
+--
+-- Instantation Template
+--
+--	singleshot_int: oneshot 
+--	GENERIC MAP (
+--		mode => 1)		
+--	PORT MAP(
+--		rst => ,
+--		clk => ,
+--		input => ,
+--		output => 
+--	);
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity singleshot is
+    Generic ( mode : integer range 0 to 2 := 1);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end singleshot;
+
+architecture Behavioral of singleshot is
+
+type s_t is (idle, shot_in, active, shot_out);
+signal s, sn : s_t;
+
+begin
+
+process (rst, clk, sn)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			s <= idle;
+		else
+			s <= sn;
+		end if;
+	end if;	
+end process;
+
+mode_1:
+if mode = 1 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				output <= '1';
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+mode_0:
+if mode = 0 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				output <= '1';
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				output <= '1';
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				output <= '1';
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+end Behavioral;

lib/misc/tb_template.vhd

@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_template IS
+END tb_template;
+
+ARCHITECTURE behavior OF tb_template IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT your_comp
+	GENERIC
+	(
+	);
+	PORT
+	(
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+
+	--Inputs
+	signal clk		: STD_LOGIC := '0';
+
+	--Outputs
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: your_comp 
+	GENERIC MAP
+	(
+	)
+	PORT MAP
+	(
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+		
+	END PROCESS;
+	
+END tb_template;

lib/misc/utils_pkg.vhd

@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+package utils_pkg is
+	
+	-- Constants
+
+	-- Functions
+	function NextPowerOfTwo(x : natural) return natural;
+	function NextExpBaseTwo(x : natural) return natural;
+	function GCD(a, b : natural) return natural;
+	function LCM(a, b : natural) return natural;
+	
+end utils_pkg;
+
+
+package body utils_pkg is
+
+	function NextExpBaseTwo(x : natural) return natural is
+	begin
+		return natural(ceil(log2(real(x))));
+	end NextExpBaseTwo;	
+	
+	function NextPowerOfTwo(x : natural) return natural is
+	begin
+
+		return 2**NextExpBaseTwo(x);
+	end NextPowerOfTwo;	
+	
+	function GCD(a, b : natural) return natural is
+	variable aa : natural;
+	variable bb : natural;
+	begin
+		aa := a;
+		bb := b;
+		while bb /= 0 loop
+			if aa > bb then
+				aa := aa - bb;
+			else
+				bb := bb - aa;
+			end if;
+		end loop;
+		
+		return aa;
+
+	end GCD;	
+
+	function LCM(a, b : natural) return natural is
+	begin
+
+		return (a * b)/GCD(a, b);
+
+	end LCM;	
+
+end utils_pkg;
+
+

projects/mips_sys/ise92/mips_sys/mips_sys.prj

@@ -6,14 +6,16 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
 vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
 vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd"
 vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
 vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
@@ -23,17 +25,21 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vhdl work "../../src/sys_types.vhd"
 vhdl work "../../src/ram_ld.vhd"
 vhdl work "../../src/bootloader.ROM_ld.vhd"
 vhdl work "../../../../lib/uart/uart_tx.vhd"
 vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vhdl work "../../src/rom_wb.vhd"
+vhdl work "../../src/ram_wb.vhd"
+vhdl work "../../src/gpio_wb.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
 vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
 vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj

@@ -6,14 +6,16 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
@@ -23,17 +25,21 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_frontend.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -8,9 +8,9 @@ vcom -explicit  -93 "../src/sdram_config_sim.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
 vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
 
 # RAMs
 vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
@@ -32,6 +32,8 @@ vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
 vcom -explicit  -93 "../src/ram_sim.vhd"
 vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../src/ram_wb.vhd"
+vcom -explicit  -93 "../src/rom_wb.vhd"
 
 # UART
 vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
@@ -39,23 +41,31 @@ vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
 vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
 vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
 vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
+
+# GPIO
+vcom -explicit  -93 "../src/gpio_wb.vhd"
 
 # LCD
 vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
 
+# Flash and USB
+vcom -explicit  -93 "../src/sys_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
+
 # FIFOS
 vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
 
 # SDRAM
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd"
+vcom -explicit  -93 "../../../lib/misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
 
 # Top and TB
 vcom -explicit  -93 "../src/mips_sys_sim.vhd"

projects/mips_sys/sim/tb_mips_sys.wdo

@@ -13,6 +13,7 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
 add wave -noupdate -format Logic /tb_mips_sys/refresh
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
@@ -26,12 +27,61 @@ add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
 add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q
 add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data
 add wave -noupdate -format Literal /tb_mips_sys/sys_error
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
+add wave -noupdate -divider BUI
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s_ca
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval
+add wave -noupdate -format Literal -label .addr -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.addr
+add wave -noupdate -format Literal -label .dout -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.dout
+add wave -noupdate -format Logic -label .en -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.en
+add wave -noupdate -format Logic -label .re -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.re
+add wave -noupdate -format Literal -label .we -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
+add wave -noupdate -divider USB
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
+add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
+add wave -noupdate -divider Flash
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn
 add wave -noupdate -divider {MIPS TOP}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
@@ -45,18 +95,15 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/in
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
 add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
 add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
 add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
@@ -67,55 +114,21 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/rst
-add wave -noupdate -divider BUI
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_req
-add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_req
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_ack
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
-add wave -noupdate -divider {Memory Bus}
-add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re_r
-add wave -noupdate -format Literal /tb_mips_sys/uut/mem_we_r
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_re
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/busy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/r_wn
 add wave -noupdate -divider {CPU DMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/contention
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
@@ -125,7 +138,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
 add wave -noupdate -divider {CPU IMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
@@ -136,16 +149,9 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr
 add wave -noupdate -divider UUT
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_buf_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_busy_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_out_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_req_wr
-add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_vld_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/st
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
 add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
 add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
@@ -159,15 +165,12 @@ add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
 add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
 add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
 add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
-add wave -noupdate -format Literal /tb_mips_sys/uut/tick_usec
 add wave -noupdate -divider I-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
 add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
@@ -177,13 +180,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_ic
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
 add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
 add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_req
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_gnt
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_din
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_rdy
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
@@ -191,6 +187,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
 add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
@@ -198,13 +195,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_req
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_gnt
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_din
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_rdy
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss
@@ -224,9 +214,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/duncached_access
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1165623518 ps} 0}
+WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1129563255 ps} 0}
 configure wave -namecolwidth 218
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -240,4 +229,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {1165509887 ps} {1165713125 ps}
+WaveRestoreZoom {1129448646 ps} {1129766075 ps}

projects/mips_sys/src/tb_mips_sys.vhd

@@ -75,6 +75,23 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 	signal sys_user_rom_din		: word_t;  
 	signal sys_user_rom_addr	: word_t;   
 
+	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
+	signal sys_usb_a			: unsigned(1 downto 0);
+	signal sys_usb_csn			: std_logic;
+	signal sys_usb_wrn			: std_logic;
+	signal sys_usb_rdn			: std_logic;
+	signal sys_usb_rstn			: std_logic;
+	signal sys_usb_int			: std_logic := '0';
+	
+	signal sys_flash_d			: word_t;
+	signal sys_flash_a			: unsigned(24 downto 0);
+	signal sys_flash_ce			: std_logic;
+	signal sys_flash_wrn		: std_logic;
+	signal sys_flash_rdn		: std_logic;
+	signal sys_flash_rstn		: std_logic;
+	signal sys_flash_byten		: std_logic;
+	signal flash_reg			: word_t;
+
 	type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
 	signal urom_data : urom_data_t;
 	
@@ -120,6 +137,23 @@ uut: entity work.mips_sys
 		sys_sdr_ba_q => sys_sdr_ba_q,
 		sys_sdr_a_q => sys_sdr_a_q,
 		sys_sdr_data => sys_sdr_data,
+
+		sys_usb_d		=> sys_usb_d,
+		sys_usb_a		=> sys_usb_a,
+		sys_usb_csn		=> sys_usb_csn,
+		sys_usb_wrn		=> sys_usb_wrn,
+		sys_usb_rdn		=> sys_usb_rdn,
+		sys_usb_rstn	=> sys_usb_rstn,
+		sys_usb_int		=> sys_usb_int,
+
+		sys_flash_d		=> sys_flash_d,
+		sys_flash_a		=> sys_flash_a,
+		sys_flash_ce	=> sys_flash_ce,
+		sys_flash_wrn	=> sys_flash_wrn,
+		sys_flash_rdn	=> sys_flash_rdn,
+		sys_flash_rstn	=> sys_flash_rstn,
+		sys_flash_byten	=> sys_flash_byten,
+
 		sys_error => sys_error
 	);
 
@@ -160,6 +194,7 @@ uut: entity work.mips_sys
 	sys_sdr_clk_fb   <= sys_sdr_clk_p after 2300 ps;
 	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
 
+	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
 CLK_GEN: process
 	begin
 		wait for CLK_PERIOD/2;
@@ -168,7 +203,7 @@ CLK_GEN: process
 
 UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
 	type file_t is file of integer;
-	file load_urom : file_t open read_mode is "test_dcache.bin";
+	file load_urom : file_t open read_mode is "test_bui.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);
@@ -187,6 +222,21 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
 		end if;	
 	end process;
 
+FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
+	begin
+		if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
+			flash_reg <= sys_flash_d;
+		end if;
+	end process;
+		
+FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
+	begin
+		sys_flash_d <= (others => 'Z') after 10 ns;
+		if sys_flash_rdn = '0' and sys_flash_ce = '1' then
+			sys_flash_d <= flash_reg after 10 ns;
+		end if;
+	end process;
+
 STIMULUS: process
 
 	begin