This commit was manufactured by cvs2svn to create tag 'R5'.

git-svn-id: http://moon:8086/svn/vhdl/tags/R5@69 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -378,7 +378,6 @@ cache_state:
 				end if;	
 			end if;	
 		when upd_cache =>
-			CYC_O					<= '1';
 			tram_addr_wr			<= cache_index_reg;
 			tram_we					<= '1';
 			cache_entry_in.valid	<= '1';

lib/CPUs/MIPS/src/core/icache.vhd

@@ -296,14 +296,12 @@ cache_state:
 				end if;	
 			end if;	
 		when upd_cache =>
-			CYC_O					<= '1';
 			tag_ram_addr_wr			<= cache_index_reg;
 			tag_ram_we				<= '1';
 			cache_entry_in.valid	<= '1';
 			sn						<= rd_cache;
 			
 		when rd_cache =>
---			CYC_O					<= '1';
 			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';

lib/CPUs/MIPS/src/core/mips_bui.vhd

@@ -182,11 +182,28 @@ architecture behavior of bui is
 	alias write_fifo_data_out is write_fifo_dout(63 downto 32);
 	alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
 
+	signal read_cycle	: std_logic;
+
 begin
 
 
 	MRDY_O			<= '1';
-	CYC_O			<= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
+
+read_cyc_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				read_cycle		<= '0';
+			else
+				read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) 
+								or (dcache_mem_gnt and CYC_O_dcache) 
+								or (icache_mem_gnt and CYC_O_icache);
+			end if;
+		end if;
+	end process;	
+					
+	CYC_O			<= not bout_fifo_empty or read_cycle;
 	STB_O			<= not bout_fifo_empty;
 	ADDR_O			<= bout_fifo_addr_out;
 	DAT_O			<= bout_fifo_data_out;
@@ -255,7 +272,7 @@ inst_dcache : dcache
 	dcache_en		<= cpu_dmem_en and not busy;
 	
 -- Instantiate synchronous FIFO
-inst_bout_fifo: entity work.fifo_sync
+inst_bout_fifo: entity work.fifo_sync_dist
 	GENERIC MAP
 	(
 		addr_width	=> 4,
@@ -277,10 +294,11 @@ inst_bout_fifo: entity work.fifo_sync
 	bout_rdy			<= not bout_fifo_full;
 	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
 	
-	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
-						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
-						   STB_O_dcache when dcache_mem_gnt = '1' else
-						   STB_O_icache when icache_mem_gnt = '1' else '0';
+	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
+-- 	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+-- 						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
+-- 						   STB_O_dcache when dcache_mem_gnt = '1' else
+-- 						   STB_O_icache when icache_mem_gnt = '1' else '0';
 						   
 
 	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
@@ -294,13 +312,11 @@ inst_bout_fifo: entity work.fifo_sync
 	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
 
 -- Instantiate synchronous FIFO
-inst_write_fifo: entity work.fifo_sync
+inst_write_fifo: entity work.fifo_sync_dist
 	GENERIC MAP
 	(
 		addr_width			=> 4,
-		data_width			=> 68,
-		almost_full_thresh	=> 12,
-		almost_empty_thresh	=> 4
+		data_width			=> 68
 	)
 	PORT MAP
 	(

lib/FIFO/sim/tb_async_fifo_ctrl.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_async_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_async_fifo_ctrl
+view wave
+do {tb_async_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us

lib/FIFO/sim/tb_async_fifo_ctrl.wdo

@@ -0,0 +1,36 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
+add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {115874 ps} {612358 ps}

lib/FIFO/sim/tb_gray_counter.fdo

@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/tb_gray_counter.vhd"
+vsim -t 1ps   -lib work tb_gray_counter
+view wave
+do {tb_gray_counter.wdo}
+view structure
+view signals
+
+run 1us

lib/FIFO/sim/tb_gray_counter.wdo

@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_gray_counter/rst
+add wave -noupdate -format Logic /tb_gray_counter/ce
+add wave -noupdate -format Logic /tb_gray_counter/clk
+add wave -noupdate -format Literal /tb_gray_counter/bcnt
+add wave -noupdate -format Literal /tb_gray_counter/bnxt
+add wave -noupdate -format Literal /tb_gray_counter/gcnt
+add wave -noupdate -format Literal /tb_gray_counter/gnxt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {20898 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {134759 ps}

lib/FIFO/sim/tb_sync_fifo_ctrl.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_sync_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_sync_fifo_ctrl
+view wave
+do {tb_sync_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us

lib/FIFO/sim/tb_sync_fifo_ctrl.wdo

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2166667 ps}

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity async_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst					: in  STD_LOGIC;
+		clk_w				: in  STD_LOGIC;
+		clk_r				: in  STD_LOGIC;
+		we					: in  STD_LOGIC;
+		re					: in  STD_LOGIC;
+		ptr_w				: out unsigned (addr_width-1 downto 0);
+		ptr_r				: out unsigned (addr_width-1 downto 0);
+		fifo_full			: out STD_LOGIC;
+		fifo_empty			: out STD_LOGIC;
+		fifo_afull			: out STD_LOGIC;
+		fifo_aempty			: out STD_LOGIC
+	);
+end async_fifo_ctrl;
+
+architecture Behavioral of async_fifo_ctrl is
+
+	signal gcnt_w		: unsigned (addr_width downto 0);
+	signal gcnt2_w		: unsigned (addr_width downto 0);
+	signal bcnt2_aw		: unsigned (addr_width downto 0);
+	signal bcnt_w		: unsigned (addr_width downto 0);
+	signal gnxt_w		: unsigned (addr_width downto 0);
+	signal bnxt_w		: unsigned (addr_width downto 0);
+	signal gcnt_r		: unsigned (addr_width downto 0);
+	signal gcnt2_r		: unsigned (addr_width downto 0);
+	signal bcnt2_ar		: unsigned (addr_width downto 0);
+	signal bcnt_r		: unsigned (addr_width downto 0);
+	signal gnxt_r		: unsigned (addr_width downto 0);
+	signal bnxt_r		: unsigned (addr_width downto 0);
+
+	signal empty, full : std_logic;
+	signal write_inhibit, read_inhibit : std_logic;
+	signal winc, rinc : std_logic;
+
+	-- synthesis translate_off
+	signal diffw		: signed (addr_width downto 0);
+	signal diffr		: signed (addr_width downto 0);
+	-- synthesis translate_on
+
+begin
+
+	ptr_w		<= bcnt_w(addr_width-1 downto 0);
+	ptr_r		<= bcnt_r(addr_width-1 downto 0);
+	winc		<= we and (not write_inhibit);
+	rinc		<= re and (not read_inhibit);
+	fifo_full	<= write_inhibit;
+	fifo_empty	<= read_inhibit;
+	
+proc_write_inhibit:
+	process(rst, clk_w)
+	begin
+		if rst = '1' then
+			write_inhibit	<= '0';
+		elsif rising_edge(clk_w) then
+			write_inhibit	<= full;
+		end if;
+	end process;
+	
+proc_read_inhibit:
+	process(rst, clk_r)
+	begin
+		if rst = '1' then
+			read_inhibit	<= '1';
+		elsif rising_edge(clk_r) then
+			read_inhibit	<= empty;
+		end if;
+	end process;
+
+proc_sync_grptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			gcnt2_r <= p2;
+			p2 := p1;
+			p1 := gcnt_r;
+		end if;
+	end process;
+
+proc_ptr_gwptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			gcnt2_w <= p2;
+			p2 := p1;
+			p1 := gcnt_w;
+		end if;
+	end process;
+	
+proc_status_full:
+	process(gnxt_w, gcnt2_r)
+	begin
+		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
+			full <= '1';
+		else
+			full <= '0';
+		end if;
+	end process;
+
+proc_status_empty:
+	process(gnxt_r, gcnt2_w)
+	begin
+		if (gnxt_r = gcnt2_w) then
+			empty <= '1';
+		else
+			empty <= '0';
+		end if;
+	end process;
+	
+proc_sync_arptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			bcnt2_ar <= p2;
+			p2 := p1;
+			p1 := bcnt_r;
+		end if;
+	end process;
+
+proc_ptr_awptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			bcnt2_aw <= p2;
+			p2 := p1;
+			p1 := bcnt_w;
+		end if;
+	end process;
+	
+proc_status_almost_full:
+	process(rst, clk_w)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffw <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_afull <= '0';
+			diff := (others => '0');
+		elsif rising_edge(clk_w) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk_r)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffr <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_aempty <= '1';
+			diff := (others => '0');
+		elsif rising_edge(clk_r) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
+		end if;
+	end process;
+
+inst_gray_counter_w : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_w,
+		ce			=> winc, 
+		bcnt		=> bcnt_w,
+		bnxt		=> bnxt_w,
+		gcnt		=> gcnt_w,
+		gnxt		=> gnxt_w
+	);
+
+inst_gray_counter_r : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_r,
+		ce			=> rinc, 
+		bcnt		=> bcnt_r,
+		bnxt		=> bnxt_r,
+		gcnt		=> gcnt_r,
+		gnxt		=> gnxt_r
+	);
+
+end Behavioral;
+

lib/FIFO/src/dpram.vhd

@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram;
+
+architecture Behavioral of dpram is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/FIFO/src/fifo_ctrl_pkg.vhd

@@ -0,0 +1,46 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package fifo_ctrl_pkg is
+
+	-- Constants
+	-- Types
+	
+	-- Functions
+	function bin2gray(xb : unsigned) return unsigned;
+	function gray2bin(xg : unsigned) return unsigned;
+
+end fifo_ctrl_pkg;
+
+package body fifo_ctrl_pkg is
+
+	function bin2gray(xb : unsigned) return unsigned is
+	variable xg : unsigned(xb'left downto xb'right);
+	begin
+	
+    	xg(xg'left) := xb(xb'left);
+		for i in 1 to xb'left loop
+			xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
+		end loop;
+	
+		return xg;
+	end bin2gray;
+	
+	function gray2bin(xg : unsigned) return unsigned is
+	variable xb : unsigned(xg'left downto xg'right);
+	begin
+
+     	xb(xb'left) := xg(xg'left);
+		for i in 1 to xg'left loop
+			xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
+		end loop;
+		
+		return xb;
+	end gray2bin;
+
+end fifo_ctrl_pkg;
+

lib/FIFO/src/fifo_sync.vhd

@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync is
+	Generic (
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		fifo_full	: out STD_LOGIC;
+		fifo_empty	: out STD_LOGIC;
+		fifo_afull	: out STD_LOGIC;
+		fifo_aempty	: out STD_LOGIC;
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
+	);
+end fifo_sync;
+
+architecture Behavioral of fifo_sync is
+	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
+	signal full			: STD_LOGIC;
+	signal empty		: STD_LOGIC;
+	signal almost_full	: STD_LOGIC;
+	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
+	
+begin
+
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
+
+	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> addr_width,
+		almost_full_thresh	=> almost_full_thresh,
+		almost_empty_thresh	=> almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
+
+	);
+
+	inst_dpram_1w1r: entity work.dpram_1w1r
+	GENERIC MAP (
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+	
+end Behavioral;
+

lib/FIFO/src/fifo_sync_dist.vhd

@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync_dist is
+	Generic (
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		fifo_full	: out STD_LOGIC;
+		fifo_empty	: out STD_LOGIC;
+		fifo_afull	: out STD_LOGIC;
+		fifo_aempty	: out STD_LOGIC;
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
+	);
+end fifo_sync_dist;
+
+architecture Behavioral of fifo_sync_dist is
+	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
+	signal full			: STD_LOGIC;
+	signal empty		: STD_LOGIC;
+	signal almost_full	: STD_LOGIC;
+	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
+	
+begin
+
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
+
+	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> addr_width,
+		almost_full_thresh	=> almost_full_thresh,
+		almost_empty_thresh	=> almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
+
+	);
+
+	inst_dpram_1w1r: entity work.dpram_1w1r_dist
+	GENERIC MAP (
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+	
+end Behavioral;
+

lib/FIFO/src/gray_counter.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity gray_counter is
+	Generic (
+		width : natural := 3;
+		init_value : natural := 0
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		bcnt		: out unsigned (width-1 downto 0);
+		bnxt		: out unsigned (width-1 downto 0);
+		gcnt		: out unsigned (width-1 downto 0);
+		gnxt		: out unsigned (width-1 downto 0)
+	);
+end gray_counter;
+
+architecture Behavioral of gray_counter is
+
+	signal cntb : unsigned (width-1 downto 0);
+	signal nxtb : unsigned (width-1 downto 0);
+	signal cntg : unsigned (width-1 downto 0);
+	signal nxtg : unsigned (width-1 downto 0);
+
+begin
+
+	bnxt	<= nxtb;
+	gnxt	<= nxtg;
+
+	process(rst, clk, ce, cntb, nxtb)
+	begin
+		if rst = '1' then
+			cntb	<= to_unsigned(init_value, width);
+			nxtb	<= to_unsigned(init_value, width);
+			cntg	<= to_unsigned(init_value, width);
+			nxtg	<= to_unsigned(init_value, width);
+			bcnt	<= to_unsigned(init_value, width);
+			gcnt	<= to_unsigned(init_value, width);
+		else
+			if rising_edge(clk) then
+				bcnt	<= nxtb;
+				gcnt	<= nxtg;
+				cntb	<= nxtb;
+				cntg	<= nxtg;
+			end if;	
+			nxtg <= bin2gray(nxtb);
+			nxtb <= cntb;
+			if ce = '1' then
+				nxtb <= cntb + 1;
+			end if;	
+		end if;	
+	end process;
+
+end Behavioral;
+

lib/FIFO/src/sync_fifo_ctrl.vhd

@@ -0,0 +1,203 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity sync_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		we				: in  STD_LOGIC;
+		re				: in  STD_LOGIC;
+		ptr_w			: out unsigned (addr_width-1 downto 0);
+		ptr_r			: out unsigned (addr_width-1 downto 0);
+		fifo_pre_full	: out STD_LOGIC;
+		fifo_pre_empty	: out STD_LOGIC;
+		fifo_full		: out STD_LOGIC;
+		fifo_empty		: out STD_LOGIC;
+		fifo_afull		: out STD_LOGIC;
+		fifo_aempty		: out STD_LOGIC
+	);
+end sync_fifo_ctrl;
+
+architecture Behavioral of sync_fifo_ctrl is
+
+	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
+	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
+	signal empty, full : std_logic;
+	signal pre_empty, pre_full : std_logic;
+	signal was_write : std_logic;
+	signal write, read : std_logic;
+	signal diff : unsigned (addr_width downto 0);
+	
+begin
+
+	read	<= re and not empty;
+	write	<= we and not full;
+
+	fifo_full		<= full;
+	fifo_empty		<= empty;
+	fifo_pre_full	<= pre_full;
+	fifo_pre_empty	<= pre_empty;
+
+
+proc_diff_gen:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			diff <= (others => '0');
+		elsif rising_edge(clk) then
+			if write = '1' and read = '0' then
+				diff <= diff + 1;
+			elsif write = '0' and read = '1' then
+				diff <= diff - 1;
+			end if;
+		end if;
+	end process;
+
+proc_status_almost_full:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_afull <= '0';
+		elsif rising_edge(clk) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_aempty <= '1';
+		elsif rising_edge(clk) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_full_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			full <= '0';
+		elsif rising_edge(clk) then
+			full <= pre_full;
+		end if;
+	end process;
+	
+proc_empty_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			empty <= '1';
+		elsif rising_edge(clk) then
+			empty <= pre_empty;
+		end if;
+	end process;
+	
+proc_status_w:
+	process(was_write, pW_next, pR_next, pW, pR, write, read)
+	begin
+		if (pW_next = pR) and (write = '1' or was_write = '1') then
+			pre_full <= '1';
+		else
+			pre_full <= '0';
+		end if;
+		if (pR_next = pW) and (read = '1' or was_write = '0') then
+			pre_empty <= '1';
+		else
+			pre_empty <= '0';
+		end if;
+	end process;
+
+proc_flag_write:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			was_write <= '0';
+		elsif rising_edge(clk) then
+			if write = '1' then
+				was_write <= '1';
+			elsif read = '1' then
+				was_write <= '0';
+			end if;
+		end if;
+	end process;
+	
+proc_ptr_w:
+	process(rst, clk, pW, write, full)
+	begin
+		if rst = '1' then
+			pW <= to_unsigned(0, addr_width);
+			pW_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if write = '1' then 
+				pW <= pW_next;
+			end if;
+		end if;
+		pW_next <= pW;
+		if write = '1' then 
+			pW_next <= pW + 1;
+		end if;
+		ptr_w		<= pW;
+	end process;
+
+proc_ptr_r:
+	process(rst, clk, pR_next, pR, read, empty)
+	begin
+		if rst = '1' then
+			pR <= to_unsigned(0, addr_width);
+			pR_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if read = '1' then
+				pR <= pR_next;
+			end if;	
+		end if;
+		pR_next	<= pR;
+		if read = '1' then
+			pR_next	<= pR + 1;
+		end if;
+		ptr_r		<= pR_next;
+	end process;
+
+end Behavioral;
+

lib/FIFO/src/tb_async_fifo_ctrl.vhd

@@ -0,0 +1,176 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_async_fifo_ctrl IS
+END tb_async_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_async_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD_W 	: time := 10 ns;
+	constant PERIOD_R 	: time := 20 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk_w				: STD_LOGIC := '0';
+	signal clk_r				: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.async_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk_w,
+		clk_r		=>	clk_r,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk_w,
+		clkb		=> clk_r,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk_w : PROCESS
+	BEGIN
+		clk_w <= not clk_w;
+		wait for PERIOD_W/2;
+	END PROCESS;
+
+ 	tb_clk_r : PROCESS
+	BEGIN
+		clk_r <= not clk_r;
+		wait for PERIOD_R/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD_W;
+		rst			<= '0';
+		wait for 5*PERIOD_W;
+		write_en <= '1';
+		wait for 15*PERIOD_W;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 15*PERIOD_R;
+		read_en <= '1';
+		
+		wait; 
+		
+	END PROCESS;
+	
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+	
+ 	tb_w : PROCESS(rst, clk_w)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk_w) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+	
+ 	tb_r : PROCESS(rst, clk_r)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk_r) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata2 = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;

lib/FIFO/src/tb_gray_counter.vhd

@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_gray_counter
+-- Module Name:   tb_gray_counter.vhd
+-- Project Name:  gray_counter package
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+ENTITY tb_gray_counter IS
+END tb_gray_counter;
+
+ARCHITECTURE behavior OF tb_gray_counter IS 
+
+	constant PERIOD		: time := 10 ns;
+	constant WIDTH		: integer := 3;
+
+	--Signals
+	signal gcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal gnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal rst			: STD_LOGIC := '1';
+	signal clk			: STD_LOGIC := '0';
+	signal ce			: STD_LOGIC := '0';
+
+BEGIN
+
+inst_gray_counter : entity work.gray_counter
+	generic map (width => WIDTH)
+	port map (
+		rst			=> rst,
+		clk			=> clk,
+		ce			=> ce, 
+		bcnt		=> bcnt,
+		bnxt		=> bnxt,
+		gcnt		=> gcnt,
+		gnxt		=> gnxt
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_counter : PROCESS
+ 	
+	BEGIN
+
+		wait for 4*PERIOD;
+		rst <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		wait for 3*PERIOD;
+		ce <= '0';
+		wait for 4*PERIOD;
+		ce <= '1';
+		wait for 1*PERIOD;
+		ce <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		
+		wait;
+		
+	END PROCESS;
+
+END behavior;

lib/FIFO/src/tb_sync_fifo_ctrl.vhd

@@ -0,0 +1,221 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_sync_fifo_ctrl IS
+END tb_sync_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD 	: time := 10 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk					: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD;
+		rst			<= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 1*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 3*PERIOD;
+		write_en <= '1';
+		wait for 4*PERIOD;
+		write_en <= '0';
+		wait for 17*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 25*PERIOD;
+		read_en <= '0';
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 7*PERIOD;
+		read_en <= '1';
+		wait for 15*PERIOD;
+		read_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+
+ 	tb_w : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+
+ 	tb_r : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;

lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj

@@ -0,0 +1,13 @@
+vhdl work "../../../misc/utils_pkg.vhd"
+vhdl work "../src/sdram_config.vhd"
+vhdl work "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../src/sdram_types.vhd"
+vhdl work "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../FIFO/src/dpram.vhd"
+vhdl work "../src/sdram_ctrl.vhd"
+vhdl work "../src/sdram_cmd.vhd"
+vhdl work "../src/reset_virtex4.vhd"
+vhdl work "../src/fifo_sync.vhd"
+vhdl work "../src/ddr_phy_virtex4.vhd"
+vhdl work "../src/clockgen_virtex4.vhd"
+vhdl work "../src/sdram_ctrl_top.vhd"

lib/SDRAM/ddr_sdr_v1_5/sim/compile_simprim.do

@@ -0,0 +1,6 @@
+vlib simprim
+
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd

lib/SDRAM/ddr_sdr_v1_5/sim/compile_unisim.do

@@ -0,0 +1,6 @@
+vlib unisim
+
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo

@@ -0,0 +1,28 @@
+## NOTE:  Do not edit this file.
+##
+
+vlib work
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
+vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../src/fifo_sync.vhd"
+vcom -explicit  -93 "../src/sdram_config.vhd"
+vcom -explicit  -93 "../src/sdram_types.vhd"
+vcom -explicit  -93 "../src/reset_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_cmd.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_frontend_wb.vhd"
+vcom -explicit  -93 "../src/mt46v16m16.vhd"
+vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
+
+#restart -force
+vsim -t 1ps   -lib work tb_sdram_ctrl_frontend_wb
+do {tb_sdram_ctrl_frontend_wb.wdo}
+view wave
+view structure
+view signals
+run 10us

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo

@@ -0,0 +1,42 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
+add wave -noupdate -divider Part
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {8165533 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {7279048 ps} {8233593 ps}

lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd

@@ -0,0 +1,370 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: DDR physical layer (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ddr_phy is
+	Port (
+		sys_rst			: in  STD_LOGIC;
+		sys_clk0		: in  STD_LOGIC;
+		sys_clk270		: in  STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_rd		: out user_tag_t;
+		u_tag_wr		: out user_tag_t;
+		read_clk		: in  STD_LOGIC;
+		phy_ctrl		: in  phy_ctrl_t;
+		part_ctrl		: in  part_ctrl_t;
+		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		sdr_dm			: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
+		sdr_data_vld	: out STD_LOGIC;
+		sdr_data_req_w	: out STD_LOGIC;
+		sdr_data_req_r	: out STD_LOGIC;
+		part_clk_p		: out STD_LOGIC;
+		part_clk_n		: out STD_LOGIC;
+		part_dm			: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		part_dqs		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		part_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0);
+		part_ba			: out unsigned(DDR_BANK_WIDTH-1 downto 0);
+		part_addr		: out unsigned(DDR_ADDR_WIDTH-1 downto 0);
+		part_cs_n		: out STD_LOGIC;
+		part_we_n		: out STD_LOGIC;
+		part_cas_n		: out STD_LOGIC;
+		part_ras_n		: out STD_LOGIC;
+		part_cke		: out STD_LOGIC
+	);
+end ddr_phy;
+
+architecture tech of ddr_phy is
+
+	signal dqs_drive		: std_logic;
+	signal drive			: std_logic;
+	signal dqs				: unsigned(DDR_DQS_WIDTH-1 downto 0);  
+	signal dqs_zen			: unsigned(DDR_DQS_WIDTH-1 downto 0);  
+	signal dqs_rst			: std_logic;
+	signal ddr_data_w		: unsigned(DDR_DATA_WIDTH-1 downto 0);
+	signal data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal data_reg_r		: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal drive270			: unsigned(DDR_DATA_WIDTH-1 downto 0);
+	signal part_ctrl_reg	: part_ctrl_t;
+	signal we_reg			: std_logic;
+	signal read_en			: std_logic;
+	
+	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
+	signal u_tag_pipe : u_tag_array_t;
+	
+begin
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+utag_pipe:
+	process(sys_rst, sys_clk0)
+	begin
+		if rising_edge(sys_clk0) then
+			for i in u_tag_pipe'length-1 downto 1 loop
+				u_tag_pipe(i) <= u_tag_pipe(i-1);
+			end loop;	
+			if phy_ctrl.utag_we = '1' then
+				u_tag_pipe(0) <= u_tag_in;
+			end if;	
+		end if;
+	end process;
+
+WE_REGISTER:
+	process(sys_rst, sys_clk0)
+	begin
+		if sys_rst = '1' then
+			we_reg <= '0';
+		elsif rising_edge(sys_clk0) then
+			we_reg	<= phy_ctrl.we;
+		end if;
+	end process;
+	
+DATA_DRIVE_GEN:
+	process(sys_clk0)
+	begin
+		if falling_edge(sys_clk0) then
+			dqs_rst		<= not we_reg;
+			drive 		<= we_reg;
+		end if;
+	end process;
+
+DQS_DRIVE_GEN:
+	process(sys_clk0)
+	variable p : unsigned(1 downto 0);
+	begin
+		if rising_edge(sys_clk0) then
+			if phy_ctrl.drive_en = '1' then
+				p := (others => '1');
+			else
+				p := p(p'left-1 downto 0) & '0';
+			end if;
+		end if;
+		dqs_drive <= p(p'left);
+	end process;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- SDRAM Clock
+ODDR_clk_p : ODDR
+	generic map
+	(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+		INIT => '0',						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
+	) 										
+	port map (
+		Q	=> part_clk_p,	-- 1-bit DDR output
+		C	=> sys_clk0,	-- 1-bit clock input
+		CE	=> '1',			-- 1-bit clock enable input
+		D1	=> '1',			-- 1-bit data input (positive edge)
+		D2	=> '0',			-- 1-bit data input (negative edge)
+		R	=> '0',			-- 1-bit reset input
+		S	=> '0' 			-- 1-bit set input
+	);
+
+ODDR_clk_n : ODDR
+	generic map
+	(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+		INIT => '0',						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
+	) 										
+	port map (
+		Q	=> part_clk_n,	-- 1-bit DDR output
+		C	=> sys_clk0,	-- 1-bit clock input
+		CE	=> '1',			-- 1-bit clock enable input
+		D1	=> '0',			-- 1-bit data input (positive edge)
+		D2	=> '1',			-- 1-bit data input (negative edge)
+		R	=> '0',			-- 1-bit reset input
+		S	=> '0' 			-- 1-bit set input
+	);
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data OUT DDR-FFs
+gen_ddr_data_out:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+	begin 
+	ODDR_data : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> ddr_data_w(n),						-- 1-bit DDR output
+			C	=> sys_clk270,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D1	=> sdr_data_w(n + DDR_DATA_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_data_w(n),						-- 1-bit data input (negative edge)
+			R	=> '0',									-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_ddr_data_out;
+
+-- Sample tristate on clock90
+	process (sys_clk270)
+	begin  
+		if rising_edge(sys_clk270) then
+			for n in 0 to DDR_DATA_WIDTH-1 loop
+               drive270(n) <= drive;
+			end loop;
+		end if;
+	end process;
+
+-- Output mux
+out_mux_data:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+		part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
+	end generate;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data-mask OUT DDR-FFs
+gen_ddr_dm_out:
+	for n in 0 to DDR_DM_WIDTH-1 generate
+	begin 
+	ODDR_dm : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> part_dm(n),							-- 1-bit DDR output
+			C	=> sys_clk270,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D1	=> sdr_dm(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_dm(n),						-- 1-bit data input (negative edge)
+			R	=> '0',									-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_ddr_dm_out;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- DQS OUT DDR-FFs
+gen_dqs_out:
+	for n in 0 to DDR_DQS_WIDTH-1 generate
+	begin 
+	ODDR_dqs : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "OPPOSITE_EDGE",			-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> dqs(n),								-- 1-bit DDR output
+			C	=> sys_clk0,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D2	=> '0',									-- 1-bit data input (positive edge)
+			D1	=> '1',									-- 1-bit data input (negative edge)
+			R	=> dqs_rst,								-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_dqs_out;
+
+-- Tristate-Control fuer dqs      
+	process (sys_clk0) is
+	variable zctrl : boolean; 
+	begin
+		if rising_edge(sys_clk0) then
+			if dqs_drive = '1' then
+				zctrl := false;
+			else
+				zctrl := true;
+			end if;
+			if zctrl then 
+				dqs_zen <= (others => '1');
+			else
+				dqs_zen <= (others => '0');
+			end if;	
+		end if;
+	end process;
+
+-- Tristate-Buffer fuer dqs      
+gen_out_mux_dqs:
+	for n in 0 to DDR_DQS_WIDTH-1 generate
+		part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
+	end generate gen_out_mux_dqs;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+	process (sys_rst, sys_clk0) is
+	begin  
+		if sys_rst = '1' then
+			part_ctrl_reg.cmd		<= COMMAND(SD_DESELECT); 
+			part_ctrl_reg.ba		<= (others=>'0');
+			part_ctrl_reg.addr		<= (others=>'0');
+			part_ctrl_reg.cke		<= '0';
+		elsif rising_edge(sys_clk0) then
+			part_ctrl_reg <= part_ctrl;
+		end if;
+	end process;
+
+	process (sys_clk0) is
+	begin  
+		if falling_edge(sys_clk0) then
+			part_ras_n		<= part_ctrl_reg.cmd.ras_n;
+			part_cas_n		<= part_ctrl_reg.cmd.cas_n; 
+			part_we_n 		<= part_ctrl_reg.cmd.we_n; 
+			part_cs_n 		<= part_ctrl_reg.cmd.cs_n; 
+			part_ba   		<= part_ctrl_reg.ba; 
+			part_addr    	<= part_ctrl_reg.addr;
+			part_cke  		<= part_ctrl_reg.cke;
+		end if;
+	end process;
+
+-----------------------------------------------------------------
+-- READ DATA Processing
+-----------------------------------------------------------------
+gen_ddr_data_in:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+	begin 
+	IDDR_data : IDDR 
+		generic map
+		(
+			DDR_CLK_EDGE	=> "SAME_EDGE",					-- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
+			INIT_Q1			=> '0', 						-- Initial value of Q1: '0' or '1'
+			INIT_Q2			=> '0',							-- Initial value of Q2: '0' or '1'
+			SRTYPE			=> "SYNC"						-- Set/Reset type: "SYNC" or "ASYNC" 
+		)
+		port map
+		(
+			Q1				=> data_r(n),					-- 1-bit output for positive edge of clock 
+			Q2				=> data_r(n + DDR_DATA_WIDTH),	-- 1-bit output for negative edge of clock
+			C				=> read_clk, 					-- 1-bit clock input
+			CE				=> read_en,						-- 1-bit clock enable input
+			D				=> part_data(n),				-- 1-bit DDR data input
+			R				=> '0',							-- 1-bit reset
+			S				=> '0' 							-- 1-bit set
+		);
+	end generate;
+
+
+data_sample_stage:
+	process (sys_clk0)
+	begin
+		if falling_edge(sys_clk0) then
+			data_reg_r	<= data_r;
+		end if;
+	end process;
+
+misc_flags_and_data_out:
+	process (sys_rst, sys_clk0)
+	variable p : unsigned(3 downto 0);
+	begin
+		if sys_rst = '1' then
+			p				:= (others => '0');
+			read_en			<= '0';
+			sdr_data_vld	<= '0';
+			sdr_data_req_w	<= '0';
+			sdr_data_req_r	<= '0';
+		elsif rising_edge(sys_clk0) then
+			sdr_data_r		<= data_reg_r;
+			if p(3) = '1' then
+				u_tag_rd		<= u_tag_pipe(4);
+			end if;	
+			if phy_ctrl.we = '1' then
+				u_tag_wr		<= u_tag_pipe(0);
+			end if;	
+			sdr_data_req_w	<= phy_ctrl.we;
+			sdr_data_req_r	<= phy_ctrl.re;
+			sdr_data_vld	<= p(3);
+			read_en			<= p(1);
+			if phy_ctrl.re = '1' then
+				p := p(p'left-1 downto 0) & '1';
+			else
+				p := p(p'left-1 downto 0) & '0';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end tech;

lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd

@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Reset generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity reset is
+	port
+	(
+		clk			: in std_logic;
+		rst_in		: in std_logic;
+		rst_out		: out std_logic
+	);
+end;
+
+architecture tech of reset is
+   
+	signal rst : std_logic;
+	signal shift_pipe : std_logic_vector(3 downto 0);
+	attribute KEEP : string;
+	attribute KEEP of shift_pipe	: signal is "TRUE";
+
+begin
+   
+	rst <= shift_pipe(0);
+
+bufg_reset: bufg
+	port map
+	(
+		o  => rst_out,  
+		i  => rst
+	);
+	
+fdp0: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map 
+	(
+		d		=> rst_in,
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(3)
+	);
+
+fdp1: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+
+		d		=> shift_pipe(3),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(2)
+	);
+
+fdp2: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+		d		=> shift_pipe(2),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(1)
+	);
+
+fdp3: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+
+		d		=> shift_pipe(1),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(0)
+	);
+  
+end tech;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd

@@ -0,0 +1,269 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM command controller
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_cmd is
+	Generic (BL 		: natural := 2);
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		enable			: in  STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_out		: out user_tag_t;
+		phy_ctrl		: out phy_ctrl_t;
+		cmd				: in  sdr_cmd_t;
+		cmd_we			: in  STD_LOGIC;
+		cmd_ack			: out STD_LOGIC;
+		col_addr		: in col_addr_t;
+		mode_word		: in  mode_word_t;
+		sdr_cmd_ctrl	: out sdr_cmd_lines_t;
+		sdr_addr		: out  sdr_addr_t;
+		sdr_ba			: out  sdr_ba_t
+	);
+end sdram_cmd;
+
+architecture behaviour of sdram_cmd is
+
+	signal st_sdr, st_sdr_next : sdr_state_t;
+	
+	signal cc_preset : natural range 0 to 10;
+	signal cc_load_en : std_logic;
+	signal cycle_finished : std_logic;
+
+	signal burst_preset : natural range 0 to 3;
+	signal burst_load_en : std_logic;
+	signal burst_finished : std_logic;
+
+begin
+
+	u_tag_out <= u_tag_in;
+	
+------------------------------------------------------------------------------------------
+
+fsm_sdr_state:
+	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
+	begin
+		st_sdr_next		<= st_sdr;
+		sdr_cmd_ctrl <= COMMAND(SD_NOP);
+		
+		cc_load_en <= '0';
+		cc_preset <= TIMING(cmd);
+		burst_load_en <= '0';
+		cmd_ack	<= '0';
+		burst_preset <= BL/2-1;
+		phy_ctrl.re <= '0';
+		phy_ctrl.drive_en <= '0';
+		phy_ctrl.we <= '0';
+		phy_ctrl.utag_we <= '0';
+		sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
+		sdr_ba	 <= mode_word(mode_word_t'left downto mode_word_t'left-1);
+		
+		case st_sdr is 
+		when PWR_DOWN =>
+			sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
+			if enable = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+			
+		when PRECHARGE =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+
+		when MODE =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+
+		when IDLE =>
+			if cmd_we = '1' then
+				cmd_ack <= '1';
+				cc_load_en <= '1';
+				cc_preset <= TIMING(cmd);
+				sdr_cmd_ctrl <= COMMAND(cmd);
+				case cmd is
+					when SD_PRE =>
+						st_sdr_next <= PRECHARGE;
+						sdr_addr(BIT_PRE_ALL)	<= mode_word(BIT_PRE_ALL);
+					when SD_LMR =>
+						st_sdr_next <= MODE;
+					when SD_ACT =>
+						st_sdr_next <= ROW_ACT;
+					when SD_AR =>
+						st_sdr_next <= AUTO_REF;
+					when others	=> null;
+					end case;	
+			end if;	
+				
+		when ROW_ACT =>
+			if cycle_finished = '1' then
+				if cmd_we = '1' then
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					cc_load_en <= '1';
+					cc_preset <= TIMING(cmd);
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					case cmd is
+					when SD_PRE =>
+						st_sdr_next <= PRECHARGE;
+					when SD_READ =>
+						phy_ctrl.utag_we <= '1';
+						st_sdr_next <= READ;
+						sdr_addr(col_addr_t'range) <= col_addr;
+					when SD_WRITE =>
+						phy_ctrl.utag_we <= '1';
+						phy_ctrl.drive_en <= '1';
+						st_sdr_next <= WRITE;
+						sdr_addr(col_addr_t'range) <= col_addr;
+					when others	=> null;
+					end case;	
+				end if;	
+			end if;	
+
+		when WRITE =>
+			phy_ctrl.drive_en <= '1';
+			phy_ctrl.we <= '1';
+			if burst_finished = '1' then
+				if cmd_we = '1' and cmd = SD_WRITE then
+					sdr_addr(col_addr_t'range) <= col_addr;
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					phy_ctrl.utag_we <= '1';
+				else	
+					phy_ctrl.drive_en <= '0';
+					cc_load_en <= '1';
+					cc_preset <= TIMING(SD_WRITE)+1;
+					st_sdr_next <= ROW_ACT;
+				end if;
+			end if;	
+
+		when READ =>
+			phy_ctrl.re <= '1';
+			if burst_finished = '1' then
+				if cmd_we = '1' and cmd = SD_READ then
+					sdr_addr(col_addr_t'range) <= col_addr;
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					phy_ctrl.utag_we <= '1';
+				else
+					cc_load_en <= '1';
+					cc_preset <= TIMING(SD_READ);
+					st_sdr_next <= ROW_ACT;
+				end if;
+			end if;	
+
+		when WRITE_A =>			-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when READ_A =>			-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when BURST_STOP =>		-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+			
+		when SELF_REF =>		-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+			
+		when PRE_PWR_DOWN =>	-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when ACT_PWR_DOWN =>	-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+		
+		when AUTO_REF =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+			
+		when others =>
+			st_sdr_next <= IDLE;
+		end case;
+		
+	end process;
+	
+fsm_sdr_state_next:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			st_sdr		<= PWR_DOWN;
+		elsif rising_edge(clk) then
+			st_sdr		<= st_sdr_next;
+		end if;
+	end process;
+	
+------------------------------------------------------------------------------------------
+cycle_counter:
+	process (rst, clk)
+	variable cycle_cnt : natural range 0 to 10;
+	begin
+		if rst = '1' then
+			cycle_cnt	:= 0;
+			cycle_finished	<= '0';
+		elsif rising_edge(clk) then
+			cycle_finished	<= '0';
+			if cc_load_en = '1' then
+				cycle_cnt := cc_preset;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt := cycle_cnt - 1;
+			else
+				cycle_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+burst_counter:
+	process (rst, clk)
+	variable burst_cnt : natural range 0 to 3;
+	begin
+		if rst = '1' then
+			burst_cnt	:= 0;
+		elsif rising_edge(clk) then
+			burst_finished	<= '0';
+			if burst_load_en = '1' then
+				burst_cnt := burst_preset;
+			elsif burst_cnt /= 0 then
+				burst_cnt := burst_cnt - 1;
+			end if;	
+			if burst_cnt = 0 then
+				burst_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 16;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 4;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 1; -- µs
+	
+	subtype user_tag_t is unsigned(3 downto 0);
+	
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd

@@ -0,0 +1,487 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM main controller and user I/F
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity sdram_ctrl is
+	Generic
+	(
+		f_sysclk 		: natural := 100E6;
+		BL 				: natural := 2
+	);
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		u_busy			: out STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_out		: out user_tag_t;
+		u_addr			: in  user_addr_t;
+		u_cmd			: in  user_cmd_t;
+		u_cmd_we		: in  STD_LOGIC;
+		col_addr		: out col_addr_t;
+		sdr_cmd_busy	: in  STD_LOGIC;
+		sdr_cmd			: out  sdr_cmd_t;
+		sdr_cmd_we		: out  STD_LOGIC;
+		sdr_mode		: out  mode_word_t;
+		sdr_cke			: out  STD_LOGIC
+	);
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+	constant LMR_BURST_LEN		: natural := NextExpBaseTwo(BL);
+
+	type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
+	signal st_ctrl, st_ctrl_next : ctrl_state_t;
+	
+	constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
+	signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
+	signal pwr_up_cnt_rst : std_logic;
+	signal pwr_up_finished : std_logic;
+
+	signal cycle_cnt : natural range 0 to 255;
+	signal cc_preset : natural range 0 to 255;
+	signal cc_load_en : std_logic;
+	signal cycle_finished : std_logic;
+
+	signal seq_cnt : natural range 0 to 31;
+	signal seq_rst_en : std_logic;
+	signal seq_cnt_en : std_logic;
+	
+	constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
+	signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
+	signal refresh_request : std_logic;
+	signal refresh_cnt_rst : std_logic;
+
+	signal addr_reg_load_en : std_logic;
+
+	signal u_tag_reg : user_tag_t;
+	signal bank_addr_reg : bank_addr_t;
+	signal row_addr_reg : row_addr_t;
+	signal col_addr_reg : col_addr_t;
+
+	signal u_bank_addr : bank_addr_t;
+	signal u_row_addr : row_addr_t;
+	signal u_col_addr : col_addr_t;
+
+	signal act_request : std_logic;
+	signal act_request_set : std_logic;
+	signal act_request_clr : std_logic;
+
+	type init_seq_rom_t is array (0 to 14) of init_seq_t;
+	
+	constant init_seq_rom : init_seq_rom_t :=
+	(
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_PRE,
+			mode_word	=> "000010000000000",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+			wait_cycle	=> 200
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_PRE,
+			mode_word	=> "000010000000000",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_AR,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_AR,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+			wait_cycle	=> 200
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		)
+	
+	);
+		
+begin
+
+	u_row_addr		<= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
+	u_bank_addr		<= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
+	u_col_addr		<= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
+
+------------------------------------------------------------------------------------------
+fsm_ctrl_state:
+	process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
+	begin
+
+		u_busy 				<= '1';
+		pwr_up_cnt_rst		<= '0';
+		cc_preset			<= init_seq_rom(seq_cnt).wait_cycle;
+		cc_load_en			<= '0';
+		sdr_cmd				<= init_seq_rom(seq_cnt).cmd;
+		sdr_cmd_we			<= '0';
+		sdr_mode			<= bank_addr_reg & row_addr_reg;
+		col_addr			<= col_addr_reg;
+		sdr_cke				<= '1';
+		seq_cnt_en			<= '0';
+		seq_rst_en			<= '0';
+		addr_reg_load_en	<= '0';
+		refresh_cnt_rst		<= '0';
+		act_request_set		<= '0';
+		act_request_clr		<= '0';
+		u_tag_out			<= u_tag_reg;
+		
+		st_ctrl_next		<= st_ctrl;
+		case st_ctrl is 
+		when RESET =>
+			sdr_cke			<= '0';
+			pwr_up_cnt_rst	<= '1';
+			st_ctrl_next	<= POWER_WAIT;
+			
+		when POWER_WAIT =>
+			sdr_cke			<= '0';
+			if pwr_up_finished = '1' then
+				seq_rst_en		<= '1';
+				st_ctrl_next	<= INIT;
+			end if;	
+
+		when INIT =>
+			sdr_mode	<= init_seq_rom(seq_cnt).mode_word;
+			sdr_cmd		<= init_seq_rom(seq_cnt).cmd;
+			cc_preset	<= init_seq_rom(seq_cnt).wait_cycle;
+			if seq_cnt = init_seq_rom_t'high then
+				act_request_set	<= '1';	
+				refresh_cnt_rst	<= '1';
+				st_ctrl_next	<= USER_READY;
+			elsif sdr_cmd_busy = '0' then
+				cc_load_en		<= '1';
+				sdr_cmd_we		<= '1';
+				st_ctrl_next	<= INIT_WAIT;
+			end if;	
+				
+		when INIT_WAIT =>
+			if sdr_cmd_busy = '0' and cycle_finished = '1' then
+				seq_cnt_en		<= '1';
+				st_ctrl_next	<= INIT;
+			end if;	
+			
+		when USER_READY =>
+			if sdr_cmd_busy = '0' then
+				if refresh_request = '1' then
+					sdr_mode(BIT_PRE_ALL) <= '1';
+					sdr_cmd_we		<= '1';
+					sdr_cmd			<= SD_PRE;
+					st_ctrl_next	<= REFRESH;
+				else	
+					u_busy		<= '0';
+					if u_cmd_we = '1' then
+						case u_cmd is
+						when UCMD_NOP =>
+							sdr_cmd		<= SD_NOP;
+						when UCMD_LMR =>
+							sdr_cmd		<= SD_NOP;
+						when UCMD_WRITE =>
+							col_addr				<= u_col_addr;
+							u_tag_out				<= u_tag_in;
+							sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
+							addr_reg_load_en		<= '1';
+							act_request_clr			<= '1';	
+							sdr_cmd					<= SD_WRITE;
+							if (u_row_addr /= row_addr_reg) or act_request = '1' then
+								st_ctrl_next		<= USER_WRITE_PRE;
+							elsif (u_bank_addr /= bank_addr_reg) then
+								if ENABLE_PRE_ALL = '1' then
+									st_ctrl_next		<= USER_WRITE_ACT;
+								else	
+									st_ctrl_next		<= USER_WRITE_PRE;
+								end if;	
+							elsif sdr_cmd_busy = '0' then
+								sdr_cmd_we			<= '1';
+							else
+								st_ctrl_next		<= USER_WRITE;
+							end if;
+						when UCMD_READ =>
+							col_addr				<= u_col_addr;
+							u_tag_out				<= u_tag_in;
+							sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
+							addr_reg_load_en		<= '1';
+							act_request_clr			<= '1';	
+							sdr_cmd					<= SD_READ;
+							if (u_row_addr /= row_addr_reg) or act_request = '1' then
+								st_ctrl_next		<= USER_READ_PRE;
+							elsif (u_bank_addr /= bank_addr_reg) then
+								if ENABLE_PRE_ALL = '1' then
+									st_ctrl_next		<= USER_READ_ACT;
+								else	
+									st_ctrl_next		<= USER_READ_PRE;
+								end if;	
+							elsif sdr_cmd_busy = '0' then
+								sdr_cmd_we			<= '1';
+							else
+								st_ctrl_next		<= USER_READ;
+							end if;
+						when others => null;
+						end case;
+					end if;	
+				end if;	
+			end if;	
+
+		when USER_WRITE_PRE =>
+		sdr_cmd			<= SD_PRE;
+		sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_WRITE_ACT;
+		end if;
+
+		when USER_WRITE_ACT =>
+		sdr_cmd			<= SD_ACT;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_WRITE;
+		end if;
+
+		when USER_WRITE =>
+		sdr_cmd			<= SD_WRITE;
+		sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+		end if;
+
+		when USER_READ_PRE =>
+		sdr_cmd			<= SD_PRE;
+		sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READ_ACT;
+		end if;
+
+		when USER_READ_ACT =>
+		sdr_cmd			<= SD_ACT;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READ;
+		end if;
+
+		when USER_READ =>
+		sdr_cmd			<= SD_READ;
+		sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+		end if;
+
+		when REFRESH =>
+		sdr_cmd			<= SD_AR;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+			refresh_cnt_rst	<= '1';
+			act_request_set	<= '1';	
+		end if;
+		
+		when others =>
+			st_ctrl_next <= RESET;
+		end case;
+		
+	end process;
+	
+fsm_ctrl_state_next:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			st_ctrl		<= RESET;
+		elsif rising_edge(clk) then
+			st_ctrl		<= st_ctrl_next;
+		end if;
+	end process;
+	
+------------------------------------------------------------------------------------------
+act_request_register:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			act_request <= '1';
+		elsif rising_edge(clk) then
+			if act_request_set = '1' then
+				act_request <= '1';
+			elsif act_request_clr = '1' then	
+				act_request <= '0';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+user_addr_register:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			bank_addr_reg <= (others => '0');
+			row_addr_reg <= (others => '0');
+			col_addr_reg <= (others => '0');
+			u_tag_reg <= (others => '0');
+		elsif rising_edge(clk) then
+			if addr_reg_load_en = '1' then
+				bank_addr_reg <= u_bank_addr;
+				row_addr_reg <= u_row_addr;
+				col_addr_reg <= u_col_addr;
+				u_tag_reg <= u_tag_in;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+power_up_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			pwr_up_cnt	<= 0;
+			pwr_up_finished <= '0';
+		elsif rising_edge(clk) then
+			pwr_up_finished <= '0';
+			if pwr_up_cnt_rst = '1' then
+				pwr_up_cnt	<= PWR_UP_CLOCK_INTERVAL-1;
+			else
+				if pwr_up_cnt /= 0 then
+					pwr_up_cnt <= pwr_up_cnt - 1;
+				else
+					pwr_up_finished <= '1';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+
+------------------------------------------------------------------------------------------
+refresh_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			refresh_cnt	<= 0;
+			refresh_request <= '0';
+		elsif rising_edge(clk) then
+			refresh_request <= '0';
+			if refresh_cnt_rst = '1' then
+				refresh_cnt	<= REFRESH_CLOCK_INTERVAL-1;
+			else
+				if refresh_cnt /= 0 then
+					refresh_cnt <= refresh_cnt - 1;
+				else
+					refresh_request <= '1';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+cycle_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			cycle_cnt	<= 0;
+			cycle_finished	<= '0';
+		elsif rising_edge(clk) then
+			cycle_finished	<= '0';
+			if cc_load_en = '1' then
+				cycle_cnt <= cc_preset;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt <= cycle_cnt - 1;
+			else
+				cycle_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+seq_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			seq_cnt	<= 0;
+		elsif rising_edge(clk) then
+			if seq_rst_en = '1' then
+				seq_cnt <= 0;
+			elsif seq_cnt_en = '1' then
+				if seq_cnt /= init_seq_rom_t'high then
+					seq_cnt <= seq_cnt + 1;
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd

@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_frontend_wb is
+	Generic
+	(
+		BL 				: natural := 2;
+		f_sysclk 		: natural := 100E6;
+		fifo_depth		: integer := 4
+	);
+	Port
+	(
+		RST_I				: in  STD_LOGIC;
+		CLK_I				: in  STD_LOGIC;
+		CLK270_I			: in  STD_LOGIC;
+		CLK270VAR_I			: in  STD_LOGIC;
+		
+		CYC_I				: in  STD_LOGIC;
+		STB_I				: in  STD_LOGIC;
+		SEL_I				: in  unsigned(3 downto 0);
+		WE_I				: in  STD_LOGIC;
+		ACK_O				: out STD_LOGIC;
+		MRDY_I				: in  STD_LOGIC;
+		SRDY_O				: out STD_LOGIC;
+		ADDR_I				: in  unsigned(31 downto 0);
+		DAT_I				: in  unsigned(31 downto 0);
+		DAT_O				: out unsigned(31 downto 0);
+
+		-- SDRAM signals
+		sd_clk_p			: out  STD_LOGIC;
+		sd_clk_n			: out  STD_LOGIC;
+		sd_cke				: out  STD_LOGIC;
+		sd_cs_n				: out  STD_LOGIC;
+		sd_cas_n			: out  STD_LOGIC;
+		sd_ras_n			: out  STD_LOGIC;
+		sd_we_n				: out  STD_LOGIC;
+		sd_addr				: out  sdr_addr_t;
+		sd_ba				: out  sdr_ba_t;
+		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+		
+	);
+end sdram_ctrl_frontend_wb;
+
+architecture struct of sdram_ctrl_frontend_wb is
+
+	-- Number of user data words for simulation
+	signal u_addr			: user_addr_t;
+	signal u_tag_in			: user_tag_t;
+	signal u_tag_rd			: user_tag_t;
+	signal u_tag_wr			: user_tag_t;
+	signal u_cmd			: user_cmd_t;
+	signal u_cmd_we			: std_logic;
+	signal u_busy			: std_logic;
+	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_data_vld		: std_logic;
+	signal u_req_wr			: std_logic;
+	signal rdy				: std_logic;
+
+	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_re				: std_logic;
+	signal cat_fifo_we				: std_logic;
+	signal cat_fifo_full			: std_logic;
+	signal cat_fifo_empty			: std_logic;
+--	signal cat_fifo_almost_full		: std_logic;
+--	signal cat_fifo_almost_empty	: std_logic;
+
+	signal write_fifo_din			: unsigned(35 downto 0);
+	signal write_fifo_dout			: unsigned(35 downto 0);
+	signal write_fifo_re			: std_logic;
+	signal write_fifo_we			: std_logic;
+	signal write_fifo_full			: std_logic;
+	signal write_fifo_empty			: std_logic;
+--	signal write_fifo_almost_full	: std_logic;
+--	signal write_fifo_almost_empty	: std_logic;
+
+	signal read_fifo_din			: unsigned(31 downto 0);
+	signal read_fifo_dout			: unsigned(31 downto 0);
+	signal read_fifo_re				: std_logic;
+	signal read_fifo_we				: std_logic;
+	signal read_fifo_full			: std_logic;
+	signal read_fifo_empty			: std_logic;
+--	signal read_fifo_almost_full	: std_logic;
+--	signal read_fifo_almost_empty	: std_logic;
+
+	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+
+	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
+	alias write_fifo_dm_in is write_fifo_din(3 downto 0);
+	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
+	alias write_fifo_dm_out is write_fifo_dout(3 downto 0);
+
+	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
+	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
+	
+begin 
+   
+	-- Instantiate synchronous FIFO
+	inst_cat_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> CAT_FIFO_WIDTH
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	cat_fifo_we,
+		re			=>	cat_fifo_re,
+		fifo_full	=>	cat_fifo_full,
+		fifo_empty	=>	cat_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cat_fifo_din,
+		data_r		=>  cat_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_write_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> write_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	write_fifo_we,
+		re			=>	write_fifo_re,
+		fifo_full	=>	write_fifo_full,
+		fifo_empty	=>	write_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  write_fifo_din,
+		data_r		=>  write_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_read_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> read_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	read_fifo_we,
+		re			=>	read_fifo_re,
+		fifo_full	=>	read_fifo_full,
+		fifo_empty	=>	read_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  read_fifo_din,
+		data_r		=>  read_fifo_dout
+	);
+
+	-- DDR SDRAM Controller Core
+	inst_sdram_ctrl : entity work.sdram_ctrl_top
+	Generic map
+	(
+		BL 				=> BL,
+		f_sysclk 		=> f_sysclk
+	)
+	Port map
+	(
+	
+		sys_rst_in			=> RST_I,
+		sys_clk0_in			=> CLK_I,
+
+		sys_clk270_in		=> CLK270_I,
+		capture_clk270_in	=> CLK270VAR_I,
+		
+		-- User interface
+		u_data_vld			=> u_data_vld,
+		u_data_req_w		=> u_req_wr,
+		u_data_req_r		=> open,
+		u_tag_in			=> u_tag_in,
+		u_tag_rd			=> u_tag_rd,
+		u_tag_wr			=> u_tag_wr,
+		u_busy				=> u_busy,
+		u_addr				=> u_addr,
+		u_cmd				=> u_cmd,
+		u_cmd_we			=> u_cmd_we,
+		u_data_wr			=> u_data_w,
+		u_data_rd			=> u_data_r,
+		u_dm				=> u_dm_wr_in,
+		
+		-- SDRAM signals
+		sd_clk_p			=> sd_clk_p,
+		sd_clk_n			=> sd_clk_n,
+		sd_cke				=> sd_cke,
+		sd_cs_n				=> sd_cs_n,
+		sd_cas_n			=> sd_cas_n,
+		sd_ras_n			=> sd_ras_n,
+		sd_we_n				=> sd_we_n,
+		sd_addr				=> sd_addr,
+		sd_ba				=> sd_ba,
+		sd_dm				=> sd_dm,
+		sd_dqs				=> sd_dqs,
+		sd_data				=> sd_data
+		
+	);
+   
+------------------------------------------------------------------------------------------
+	SRDY_O				<= rdy;
+	ACK_O				<= not (read_fifo_empty);
+	DAT_O				<= read_fifo_data_out;
+	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
+	write_fifo_we 		<= STB_I and WE_I and rdy;
+	write_fifo_data_in	<= DAT_I;
+	write_fifo_dm_in	<= not SEL_I;
+	cat_fifo_we			<= STB_I and rdy;
+	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
+	addr_fifo_in		<= ADDR_I(24 downto 2) & "0";
+	tag_fifo_in			<= "000" & ADDR_I(25);
+	
+	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
+	u_cmd				<= cmd_fifo_out;
+	u_addr				<= addr_fifo_out;
+	u_dm_wr_in			<= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111");
+	u_tag_in			<= tag_fifo_out;
+	u_data_w			<= write_fifo_data_out & write_fifo_data_out;
+	
+	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
+	cat_fifo_re			<= u_cmd_we;
+	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
+	read_fifo_we		<= u_data_vld;
+	read_fifo_data_in	<= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32);	
+
+end architecture struct;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd

@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Top-level put all together
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_top is
+	Generic
+	(
+		BL 				: natural := 2;
+		f_sysclk 		: natural := 100E6
+	);
+	Port
+	(
+		sys_rst_in			: in  STD_LOGIC;
+		sys_clk0_in			: in  STD_LOGIC;
+		sys_clk270_in		: in  STD_LOGIC;
+		capture_clk270_in	: in  STD_LOGIC;
+		
+		-- User interface
+		u_data_vld			: out STD_LOGIC;
+		u_data_req_w		: out STD_LOGIC;
+		u_data_req_r		: out STD_LOGIC;
+		u_busy				: out STD_LOGIC;
+		u_tag_in			: in  user_tag_t;
+		u_tag_rd			: out user_tag_t;
+		u_tag_wr			: out user_tag_t;
+		u_addr				: in  user_addr_t;
+		u_cmd				: in  user_cmd_t;
+		u_cmd_we			: in  STD_LOGIC;
+		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		u_dm				: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
+		
+		-- SDRAM signals
+		sd_clk_p			: out  STD_LOGIC;
+		sd_clk_n			: out  STD_LOGIC;
+		sd_cke				: out  STD_LOGIC;
+		sd_cs_n				: out  STD_LOGIC;
+		sd_cas_n			: out  STD_LOGIC;
+		sd_ras_n			: out  STD_LOGIC;
+		sd_we_n				: out  STD_LOGIC;
+		sd_addr				: out  sdr_addr_t;
+		sd_ba				: out  sdr_ba_t;
+		sd_dm				: out  unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+		
+	);
+end sdram_ctrl_top;
+
+architecture rtl of sdram_ctrl_top is
+
+
+	signal phy_ctrl			: phy_ctrl_t;
+
+	signal u_tag			: user_tag_t;
+	signal sd_cmd_in		: sdr_cmd_t;
+	signal sd_cmd			: sdr_cmd_t;
+	signal sd_cmd_we		: std_logic;
+	signal cmd_ctrl			: sdr_cmd_lines_t;
+	signal cke				: std_logic;
+	signal ba				: unsigned(DDR_BANK_WIDTH-1 downto 0);
+	signal addr				: unsigned(DDR_ADDR_WIDTH-1 downto 0);
+
+	-- Clock generator
+
+	signal ctrl_rst			: std_logic;  
+	signal part_ctrl		: part_ctrl_t;  
+
+	-- SD command FIFO
+
+	constant CMD_FIFO_ADDR_WIDTH	: positive := 2;
+	constant CMD_FIFO_DATA_WIDTH	: positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
+	signal cmd_fifo_din				: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+	signal cmd_fifo_dout			: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+	signal cmd_fifo_re				: std_logic;
+	signal cmd_fifo_we				: std_logic;
+	signal cmd_fifo_full			: std_logic;
+	signal cmd_fifo_empty			: std_logic;
+
+	alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+	alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+	alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+	alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+	alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+	alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+	alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+	alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+begin 
+      	
+	---------------------------------
+	part_ctrl.cmd	<= cmd_ctrl;
+	part_ctrl.ba	<= ba;
+	part_ctrl.addr	<= addr;
+	part_ctrl.cke	<= cke;
+
+	---------------------------------
+	sd_cmd_we		<= not cmd_fifo_empty;
+	cmd_fifo_in		<= to_unsigned(sd_cmd_in, 4);
+	sd_cmd			<= sdr_cmd_t(to_integer(cmd_fifo_out));
+
+	---------------------------------
+	inst_reset: entity work.reset
+	port map
+	(
+		clk					=> sys_clk0_in,
+		rst_in				=> sys_rst_in,
+		rst_out				=> ctrl_rst
+	);
+	
+	-- Main controller
+	inst_sdram_ctrl : entity work.sdram_ctrl
+	Generic map 
+	(
+		f_sysclk	=> 100E6,
+		BL			=> BL
+	)
+	Port map 
+	(
+		rst				=> ctrl_rst,
+		clk				=> sys_clk0_in,
+		u_busy			=> u_busy,
+		u_tag_in		=> u_tag_in,
+		u_tag_out		=> tag_fifo_in,
+		u_cmd			=> u_cmd,
+		u_cmd_we		=> u_cmd_we,
+		u_addr			=> u_addr,
+		sdr_cmd_busy	=> cmd_fifo_full,
+		sdr_cmd			=> sd_cmd_in,
+		sdr_cmd_we		=> cmd_fifo_we,
+		col_addr		=> col_fifo_in,
+		sdr_mode		=> mode_fifo_in,
+		sdr_cke			=> cke
+	);
+   
+	-- Instantiate synchronous FIFO
+	inst_sd_cmd_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> CMD_FIFO_ADDR_WIDTH,
+		data_width			=> CMD_FIFO_DATA_WIDTH,
+		almost_full_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1),
+		almost_empty_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1)
+	)
+	PORT MAP
+	(
+		rst			=>	ctrl_rst,
+		clk			=>	sys_clk0_in,
+		we			=>	cmd_fifo_we,
+		re			=>	cmd_fifo_re,
+		fifo_full	=>	cmd_fifo_full,
+		fifo_empty	=>	cmd_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cmd_fifo_din,
+		data_r		=>  cmd_fifo_dout
+	);
+
+	-- DDR SDRAM command fsm
+	inst_sdram_cmd : entity work.sdram_cmd
+	Generic map
+	(
+		BL				=> BL
+	)
+	Port map
+	(
+		rst				=> ctrl_rst,
+		clk				=> sys_clk0_in,
+		u_tag_in		=> tag_fifo_out,
+		u_tag_out		=> u_tag,
+		phy_ctrl		=> phy_ctrl,
+		enable			=> cke,
+		cmd				=> sd_cmd,
+		cmd_we			=> sd_cmd_we,
+		cmd_ack			=> cmd_fifo_re,
+		sdr_cmd_ctrl	=> cmd_ctrl,
+		col_addr		=> col_fifo_out,
+		mode_word		=> mode_fifo_out,
+		sdr_ba			=> ba,
+		sdr_addr		=> addr
+	);
+   
+	-- DDR phy
+	inst_ddr_phy : entity work.ddr_phy
+	Port map
+	(
+		sys_rst			=> ctrl_rst,
+		sys_clk0		=> sys_clk0_in,
+		sys_clk270		=> sys_clk270_in,
+		u_tag_in		=> u_tag,
+		u_tag_rd		=> u_tag_rd,
+		u_tag_wr		=> u_tag_wr,
+		read_clk		=> capture_clk270_in,
+		phy_ctrl		=> phy_ctrl,
+		part_ctrl		=> part_ctrl,
+		sdr_data_req_w	=> u_data_req_w,
+		sdr_data_req_r	=> u_data_req_r,
+		sdr_data_w		=> u_data_wr,
+		sdr_dm			=> u_dm,
+		sdr_data_r		=> u_data_rd,
+		sdr_data_vld	=> u_data_vld,
+		part_clk_p		=> sd_clk_p,
+		part_clk_n		=> sd_clk_n,
+		part_addr		=> sd_addr,
+		part_ba			=> sd_ba,
+		part_dm			=> sd_dm,
+		part_dqs		=> sd_dqs,
+		part_data		=> sd_data,
+		part_cs_n		=> sd_cs_n,
+		part_we_n		=> sd_we_n,
+		part_cas_n		=> sd_cas_n,
+		part_ras_n		=> sd_ras_n,
+		part_cke		=> sd_cke
+	);
+   
+end architecture rtl;
+

lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd

@@ -0,0 +1,133 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Type definitions
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.sdram_config.all;
+
+package sdram_types is
+
+	-----------------------------------------------------------------------------------------
+	-- Table of Timing Parameters as a function of operation
+
+	-- Derived constants from sdram_config
+
+	constant DDR_DQS_WIDTH  	: positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
+	constant DDR_DM_WIDTH   	: positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
+	constant SDR_DATA_WIDTH 	: positive := 2*DDR_DATA_WIDTH;  -- 
+	constant SDR_DM_WIDTH		: positive := 2*DDR_DM_WIDTH;  -- 
+
+	subtype user_cmd_t is unsigned(1 downto 0);
+	constant UCMD_NOP			: user_cmd_t := "00";
+	constant UCMD_READ			: user_cmd_t := "01";
+	constant UCMD_WRITE			: user_cmd_t := "10";
+	constant UCMD_LMR			: user_cmd_t := "11";
+
+	subtype sdr_cmd_t is natural range 0 to 9;
+	constant SD_DESELECT		: sdr_cmd_t := 0;
+	constant SD_NOP				: sdr_cmd_t := 1;
+	constant SD_LMR				: sdr_cmd_t := 2;
+	constant SD_ACT				: sdr_cmd_t := 3;
+	constant SD_READ			: sdr_cmd_t := 4;
+	constant SD_WRITE			: sdr_cmd_t := 5;
+	constant SD_PRE				: sdr_cmd_t := 6;
+	constant SD_BST				: sdr_cmd_t := 7;
+	constant SD_AR				: sdr_cmd_t := 8;
+	constant SD_SR				: sdr_cmd_t := 9;
+	
+	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
+	subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
+	subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+	subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+	subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
+
+	subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+	subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+	subtype col_addr_t is unsigned(8 downto 0);
+	
+	subtype cycle_cnt_t is natural range 0 to 10;
+	
+	type phy_ctrl_t is
+	record
+		drive_en		: std_logic;
+		re				: std_logic;
+		we				: std_logic;
+		utag_we			: std_logic;
+	end record phy_ctrl_t;
+
+	type sdr_cmd_lines_t is
+	record
+         cs_n    : std_logic;
+         ras_n   : std_logic;
+         cas_n   : std_logic;
+         we_n    : std_logic;
+	end record sdr_cmd_lines_t;
+
+	type part_ctrl_t is
+	record
+		cmd		: sdr_cmd_lines_t;
+		ba	 	: unsigned(DDR_BANK_WIDTH-1 downto 0);
+		addr	: unsigned(DDR_ADDR_WIDTH-1 downto 0);
+		cke		: std_logic;
+	end record part_ctrl_t;
+	
+	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
+	constant COMMAND : part_cmd_array_t :=
+	--	 command                 cs_n     ras_qn      cas_qn      we_qn
+	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
+		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
+		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
+		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
+		SD_READ             =>   (   '0',      '1',        '0',        '1'),
+		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
+		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
+		SD_BST              =>   (   '0',      '1',        '1',        '0'),
+		SD_AR               =>   (   '0',      '0',        '0',        '1'),
+		SD_SR               =>   (   '0',      '0',        '0',        '1')
+	);
+
+	type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
+	constant TIMING : part_timing_array_t :=
+	--	 command                 cycle_cnt
+	(	SD_DESELECT         =>   (     0        ),
+		SD_NOP              =>   (     0        ),
+		SD_LMR              =>   (     TMRD-1   ),
+		SD_ACT              =>   (     TRCD-1   ),
+		SD_READ             =>   (     TCAS-1   ),
+		SD_WRITE            =>   (     TWR-1    ),
+		SD_PRE              =>   (     TRP-1    ),
+		SD_BST              =>   (     0        ),
+		SD_AR               =>   (     TRFC-1   ),
+		SD_SR               =>   (     TRFC-1   )
+	);
+
+	type init_seq_t is 
+	record
+		cmd			: sdr_cmd_t;
+		mode_word	: mode_word_t;
+		wait_cycle	: natural;
+	end record init_seq_t;	
+	
+end sdram_types;

lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd

@@ -0,0 +1,505 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdram_ctrl_frontend_wb is
+end;
+
+architecture struct of tb_sdram_ctrl_frontend_wb is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+	constant BURST_LEN		: natural := 2;
+
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal locked			: std_logic;  
+	signal error			: std_logic;  
+	signal clk_out			: std_logic;  
+	signal clk_fb			: std_logic;  
+	signal part_clk_p		: std_logic;  
+	signal part_clk_n		: std_logic;  
+	signal part_cke			: std_logic;  
+	signal part_cs_n		: std_logic;  
+	signal part_we_n		: std_logic;  
+	signal part_ras_n		: std_logic;  
+	signal part_cas_n		: std_logic;  
+	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+	signal CLK_O			: std_logic;
+	signal CLK270_O			: std_logic;
+	signal CLK270VAR_O		: std_logic;
+	signal RST_O			: std_logic;
+	signal CYC_O			: std_logic := '0';
+	signal STB_O			: std_logic := '0';
+	signal WE_O				: std_logic := '0';
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic;
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic;
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0);
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+begin 
+   
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst,   -- external async reset, low active
+		clk_in			=> clk,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> CLK270VAR_O,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> CLK_O,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> CLK270_O,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> error
+	);
+
+
+	clk_fb	<= part_clk_p after 1 ns;
+	RST_O	<= not locked;
+	
+	-- DDR SDRAM Controller Core
+	sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
+	GENERIC MAP
+	(
+		BL 				=> BURST_LEN,
+		f_sysclk 		=> 100E6,
+		fifo_depth		=> 3
+	)
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CLK270_I	=> CLK270_O,
+		CLK270VAR_I	=> CLK270VAR_O,
+		
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I,
+
+		-- SDRAM signals
+		sd_clk_p	=> part_clk_p,
+		sd_clk_n	=> part_clk_n,
+		sd_cke		=> part_cke,
+		sd_cs_n		=> part_cs_n,
+		sd_cas_n	=> part_cas_n,
+		sd_ras_n	=> part_ras_n,
+		sd_we_n		=> part_we_n,
+		sd_addr		=> part_addr,
+		sd_ba		=> part_ba,
+		sd_dm		=> part_dm,
+		sd_dqs		=> part_dqs,
+		sd_data		=> part_data
+		
+	);
+   
+
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data),
+         dqs   => std_logic_vector(part_dqs),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm)
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+		
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		
+		wait until RST_O = '0';
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "0011";
+		ADDR_O	<= X"0000_0080";
+		DAT_O	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0080";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		MRDY_O	<= '0';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		MRDY_O	<= '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		CYC_O	<= '0';
+
+		wait; 
+	
+	end process;
+	
+end architecture struct;

lib/misc/async_port_wb.vhd

@@ -0,0 +1,290 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.3 2008-10-12 14:12:14 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.sys_types.all;
+
+	------------------------------------------------------------------
+entity async_port_wb is
+	Generic
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		async_timespec	: async_timespec_t
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_rst	: out std_logic
+	);
+end async_port_wb;
+
+architecture Behavioral of async_port_wb is
+
+	type async_t is record
+		cs		: std_logic;
+		wr		: std_logic;
+		rd		: std_logic;
+		rst		: std_logic;
+		drive_d	: std_logic;
+	end record;
+	
+	type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
+	
+	signal s, sn		: async_state_t;
+	signal as			: async_t;
+	signal ack			: std_logic;
+	signal cc_rst		: std_logic;
+	signal cycle_cnt	: natural range 0 to 15;
+	signal cycle_reload	: natural range 0 to 15;
+	signal rdy			: std_logic;
+	signal rdyo			: std_logic;
+	signal en			: std_logic;
+	signal data_reg		: unsigned(data_width-1 downto 0);
+
+	------------------------------------------------------------------
+	begin
+
+	SRDY_O	<= CYC_I and rdyo;
+	en		<= CYC_I and STB_I;
+	
+	proc_cycle_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if cc_rst = '1' then
+				cycle_cnt <= cycle_reload;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt <= cycle_cnt - 1;
+			end if;
+		end if;
+	end process;
+	
+	------------------------------------------------------------------
+	proc_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				s <= start;
+			else
+				s <= sn;
+			end if;
+		end if;
+	end process;
+	
+	proc_state:
+	process(s, cycle_cnt, en, WE_I)
+	begin
+		
+		cycle_reload	<= async_timespec.ncyc_pulse_rst;
+		cc_rst			<= '0';
+		as.rst			<= '0';
+		as.cs			<= '0';
+		as.wr			<= '0';
+		as.rd			<= '0';
+		as.drive_d		<= '0';
+		ack				<= '0';
+		rdy				<= '0';
+		
+		sn	<= s;
+		case s is
+		
+		when start =>
+			cc_rst	<= '1';
+			sn		<= reset;
+		when reset =>
+			as.rst	<= '1';
+			if cycle_cnt = 0 then
+				sn	<= idle;
+			end if;
+		when idle =>
+			rdy			<= '1';
+			if en = '1' then
+				as.cs			<= '1';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_access-1;
+				if WE_I = '0' then
+					sn				<= leadin_rd;
+				else
+					sn				<= leadin_wr;
+				end if;
+			end if;
+
+		when leadin_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_rd-1;
+				as.rd			<= '1';
+				sn				<= read;
+			end if;
+
+		when leadin_wr =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_wr-1;
+				as.wr			<= '1';
+				as.drive_d		<= '1';
+				sn				<= write;
+			end if;
+	
+		when read =>
+			as.cs		<= '1';
+			as.rd		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+--				as.rd			<= '0';
+				sn				<= leadout_rd;
+				ack				<= '1';
+			end if;
+				
+		when write =>
+			as.drive_d	<= '1';
+			as.cs		<= '1';
+			as.wr		<= '1';
+			if cycle_cnt = 0 then
+				as.wr			<= '0';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+				sn				<= leadout_wr;
+--				ack				<= '1';
+			end if;
+
+		when leadout_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when leadout_wr =>
+			as.cs		<= '1';
+			as.drive_d	<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when release =>
+			if cycle_cnt = 0 then
+				sn				<= idle;
+			end if;
+
+		when others =>
+			sn <= idle;
+			
+		end case;		
+	end process;
+
+	------------------------------------------------------------------
+	output_ctrl:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_cs	<= (not async_timespec.pol_cs) xor as.cs;
+			async_wr	<= (not async_timespec.pol_we) xor as.wr;
+			async_rd	<= (not async_timespec.pol_oe) xor as.rd;
+			async_rst	<= (not async_timespec.pol_rst) xor as.rst;
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	din_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if as.rd = '1' then
+				DAT_O(data_width-1 downto 0) 	<= async_d;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_addr:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				async_a		<= (others => '0');
+			elsif en = '1' and rdy = '1' then
+				async_a 	<= ADDR_I(addr_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if en = '1' and rdy = '1' then
+				data_reg 	<= DAT_I(data_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_SRDY:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				rdyo 	<= '1';
+			elsif en = '1' then
+				rdyo 	<= rdy and not rdyo;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_ACK:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O 	<= '0';
+			else
+				ACK_O 	<= ack;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_data:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_d 	<= (others => 'Z');
+			if as.drive_d = '1' then
+				async_d 	<= data_reg;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+
+end Behavioral;

lib/misc/clockgen_virtex4.vhd

@@ -0,0 +1,236 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Clock generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee, work;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clockgen is
+	generic
+	(
+		sys1_phaseshift : integer := 0;
+		frequency_hz : integer := 100E6
+	);
+	port 
+	(
+		-- Clocks and Reset
+		rst				: in std_logic;   -- external async reset, low active
+		clk_in			: in std_logic;   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		: in std_logic;   -- feedback clock
+		sys1_clk0_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	: out std_logic;  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	: out std_logic;  -- System clock #0, dcm#0 output 270°
+		locked_out		: out std_logic;  -- DCM locked status
+		error_out		: out std_logic   -- indicates DCM Errors
+	);
+end;
+
+architecture tech of clockgen is
+
+	constant CLKIN_PER 				: real := real(1000E6/frequency_hz);
+
+	signal locked					: unsigned(1 downto 0);
+	signal dcm_rst					: unsigned(1 downto 0);
+	signal sys1_clk0				: std_logic;
+	signal sys1_clk270				: std_logic;
+	signal sys1_clk0_bufg			: std_logic;
+	signal sys1_clk270_bufg			: std_logic;
+	signal sys0_clk0					: std_logic;
+	signal sys0_clk270				: std_logic;
+	signal sys0_clk0_bufg			: std_logic;
+	signal sys0_clk270_bufg			: std_logic;
+	signal dcm1_locked, dcm2_locked	: unsigned(2 downto 0);
+	signal cnt_q 					: unsigned(4 downto 0);
+
+	type STATE_TYPE is (s0, s1, s2, s3, s4);
+	signal state_q : STATE_TYPE;
+
+begin 
+
+	sys1_clk0_out	<= sys1_clk0_bufg;
+	sys1_clk270_out	<= sys1_clk270_bufg;
+	sys0_clk0_out	<= sys0_clk0_bufg;
+	sys0_clk270_out	<= sys0_clk270_bufg;
+
+bufg11: bufg
+	port map
+	(
+		o  => sys0_clk0_bufg,  
+		i  => sys0_clk0
+	);
+
+bufg12: bufg
+	port map (
+		o  => sys0_clk270_bufg,  
+		i  => sys0_clk270
+	);
+
+bufg13: bufg
+	port map
+	(
+		o  => sys1_clk0_bufg,  
+		i  => sys1_clk0
+	);
+
+bufg14: bufg
+	port map (
+		o  => sys1_clk270_bufg,  
+		i  => sys1_clk270
+	);
+
+	-------------------------------------------------------------------------------------------------------
+	-- Clock generation
+	-------------------------------------------------------------------------------------------------------
+   
+inst_DCM_BASE_0 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys0_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys0_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(0),     -- DCM LOCK status output
+		CLKFB => clk_fb_in,       -- DCM clock feedback
+		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(0)            -- DCM asynchronous reset input
+	);
+
+	inst_DCM_BASE_1 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys1_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys1_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(1),     -- DCM LOCK status output
+		CLKFB => sys1_clk0_bufg,       -- DCM clock feedback
+		CLKIN => clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(1)            -- DCM asynchronous reset input
+	);
+
+	dcm_rst(1) <= not locked(0);
+	
+dcm_fsm:
+	process(rst, clk_in)
+	begin
+		if rst = '1' then
+			state_q <= s0;
+			dcm_rst(0) <= '0';
+			cnt_q <= "11111";
+			error_out <= '0';
+			locked_out <= '0';
+			dcm1_locked <= (others => '0');
+			dcm2_locked <= (others => '0');
+		elsif rising_edge(clk_in) then
+			case state_q is
+			when s0 =>
+				state_q <= s1;
+
+			when s1 =>
+			cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '1';
+					state_q <= s2;
+				end if;
+
+			when s2 =>
+				cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '0';
+					state_q <= s3;
+				end if;
+
+			when s3 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					state_q <= s4;
+					error_out <= '0';
+				end if;
+
+			when s4 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					locked_out <= '1';
+				else
+					error_out <= '1';
+				end if;
+			end case;
+
+			-- synchronize 'dcm1_locked'
+			dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
+			dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
+
+		end if;
+	end process;
+
+end architecture tech;
+
+

lib/misc/debounce.vhd

@@ -0,0 +1,91 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    19:34:24 10/23/05
+-- Design Name:    
+-- Module Name:    debounce - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+    Generic ( ncyc_latency : integer := 100);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+
+type debounce_state_t is (init_st, wait_st, rel_st);
+signal debounce_cs : debounce_state_t;
+signal debounce_ns : debounce_state_t;
+signal count       : integer range 0 to ncyc_latency;
+signal input_last	 : std_logic;
+
+begin
+
+	debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
+	begin
+		if (rst = '1') then
+			count <= 0;
+			output <= input;
+			input_last <= input;
+		else
+			if rising_edge(clk) then
+				debounce_cs <= debounce_ns;
+				if (debounce_cs = wait_st) then
+					if (count /= 0) then
+						count <= count - 1;
+					end if;
+				else
+					count <= ncyc_latency;
+					if	(debounce_cs = rel_st) then
+						output <= input;
+						input_last <= input;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
+	begin
+		debounce_ns <= debounce_cs;
+		case debounce_cs is
+			when init_st =>
+				if (input /= input_last) then
+					debounce_ns <= wait_st;
+				end if;
+			when wait_st =>
+				if (count = 0) then
+					debounce_ns <= rel_st;
+				end if;
+			when others => 
+				debounce_ns <= init_st;
+		end case;
+	end process;
+
+end Behavioral;

lib/misc/debounce2.vhd

@@ -0,0 +1,142 @@
+------------------------------------------------- 
+-- Signal Debouncer
+-- Jeff Bazinet
+-- February 14, 2002
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+
+library ieee; 
+use ieee.std_logic_1164.all;
+library lpm;
+use lpm.lpm_components.lpm_counter;
+
+
+entity debounce is
+	generic(BUFFER_WIDTH:	positive:= 30;
+		CLOCK_DIV: 	positive:= 15
+		);
+	port(	clock:		in std_logic;
+		reset:		in std_logic;
+		signal_in:	in std_logic;
+		signal_out:	out std_logic
+		);
+end entity debounce;
+
+
+architecture rtl of debounce is 
+
+	---------------------------------------------------------------
+	-- SIGNAL DECLARATION
+	---------------------------------------------------------------
+	
+	-- General
+	signal reset_n:	std_logic;
+	
+	-- SLOW CLOCK GENERATION
+	signal clock_reg:	std_logic_vector(CLOCK_DIV-1 downto 0);
+	signal clock_reg_high:	std_logic_vector(CLOCK_DIV-1 downto 1);	
+	signal clock_slow:	std_logic;
+	signal clock_slow_wire:	std_logic;
+	
+	-- DATA BUFFER FILL
+	signal counter_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	signal data_buffer_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	
+	-- CHECK FOR DEBOUNCE STABILITY
+	signal stable:	std_logic;
+	signal stable_old:	std_logic;
+	signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
+	
+	-- PUSH BUTTON ENABLE
+	signal button_pushed:	std_logic;
+	
+	begin
+	
+	---------------------------------------------------------------
+	-- SLOW CLOCK GENERATION
+	---------------------------------------------------------------
+	
+	COUNTER_1: lpm_counter
+		generic map (lpm_width => CLOCK_DIV)
+		port map (
+			clock => clock,
+			sclr => reset_n,
+			cout => clock_slow_wire
+			);
+			
+	process (clock) is
+		begin
+		
+		clock_slow <= clock_slow_wire;
+
+		end process;
+		
+	---------------------------------------------------------------
+	-- DATA BUFFER FILL
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			data_buffer_reg <= (others => '1');
+		elsif rising_edge(clock_slow) then
+			data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
+		end if;
+	
+	end process;
+	
+	---------------------------------------------------------------
+	-- CHECK FOR DEBOUNCE STABILITY
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			stable <= '0';
+			stable_old <= '0';
+			stable_state_reg <= (others => '0');
+		elsif rising_edge(clock) then
+			if (data_buffer_reg = stable_state_reg) then
+				stable <= '1';
+				stable_state_reg <= (others => '0');
+			else
+				stable <= '0';
+			end if;
+			stable_old <= stable;
+		end if;
+	
+	end process;
+	 
+	---------------------------------------------------------------
+	-- PUSH BUTTON ENABLE
+	---------------------------------------------------------------
+	
+	process (clock) is
+		begin
+	
+		if (reset = '0') then
+			-- Initialization
+			button_pushed <= '0';
+		elsif rising_edge(clock) then
+			if (stable_old = '0' and stable = '1') then
+				button_pushed <= '1';
+			else
+				button_pushed <= '0';
+			end if;	
+		end if;
+	
+	end process;
+	
+	---------------------------------------------------------------
+	---------------------------------------------------------------
+	 
+	signal_out <= button_pushed;
+	reset_n <= not reset;
+	
+end rtl; 

lib/misc/dpram_1w1r.vhd

@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r;
+
+architecture Behavioral of dpram_1w1r is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_1w1r_dist.vhd

@@ -0,0 +1,84 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r_dist is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r_dist;
+
+architecture Behavioral of dpram_1w1r_dist is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+	attribute ram_style : string;
+	attribute ram_style of RAM: signal is "distributed";
+	
+begin
+
+process (clka)
+	begin
+	if clka'event and clka = '1' then
+		if en_a = '1' then
+			if we_a = '1' then
+				RAM(to_integer(addr_a)) <= din_a;
+			end if;
+		end if;
+	end if;
+end process;
+
+process (clkb)
+	begin
+	if clkb'event and clkb = '1' then
+		if en_b = '1' then
+			dout_b <= RAM(to_integer(addr_b));
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r;
+
+architecture Behavioral of dpram_2w2r is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if en_a = '1' then
+		dout_a <= RAM(to_integer(addr_a));
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) := din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) := din_b;
+		end if;
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r_virtex4.vhd

@@ -0,0 +1,211 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity dpram_2w2r is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r;
+
+architecture Structure of dpram_2w2r is
+
+	signal do_a	: std_logic_vector(31 downto 0);
+	signal do_b	: std_logic_vector(31 downto 0);
+	signal di_a	: std_logic_vector(31 downto 0);
+	signal di_b	: std_logic_vector(31 downto 0);
+	signal ad_a	: std_logic_vector(14 downto 0);
+	signal ad_b	: std_logic_vector(14 downto 0);
+	signal wr_a	: std_logic_vector(3 downto 0);
+	signal wr_b	: std_logic_vector(3 downto 0);
+
+begin
+
+-- RAMB16: 16k+2k Parity Paramatizable block RAM
+-- Virtex-4
+-- Xilinx HDL Libraries Guide, version 9.1i
+RAMB16_inst : RAMB16
+generic map
+(
+	DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
+	DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
+	INIT_A => X"000000000", -- Initial values on A output port
+	INIT_B => X"000000000", -- Initial values on B output port
+	INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
+	INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
+	RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+	RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+	READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+	READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+	SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
+
+	-- "GENERATE_X_ONLY" or "NONE"
+	SRVAL_A => X"000000000", -- Port A output value upon SSR assertion
+	SRVAL_B => X"000000000", -- Port B output value upon SSR assertion
+	WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+	WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+	WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+	WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+	
+	-- The following INIT_xx declarations specify the initial contents of the RAM
+	INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+	
+	-- The next set of INITP_xx are for the parity bits
+	INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+	INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
+)
+port map 
+(
+	CASCADEOUTA => open, -- 1-bit cascade output
+	CASCADEOUTB => open, -- 1-bit cascade output
+	DOA => do_a, -- 32-bit A port Data Output
+	DOB => do_b, -- 32-bit B port Data Output
+	DOPA => open, -- 4-bit A port Parity Output
+	DOPB => open, -- 4-bit B port Parity Output
+	ADDRA => ad_a, -- 15-bit A Port Address Input
+	ADDRB => ad_b, -- 15-bit B Port Address Input
+	CASCADEINA => '0', -- 1-bit cascade A input
+	CASCADEINB => '0', -- 1-bit cascade B input
+	CLKA => clk_a, -- Port A Clock
+	CLKB => clk_b, -- Port B Clock
+	DIA => di_a, -- 32-bit A port Data Input
+	DIB => di_b, -- 32-bit B port Data Input
+	DIPA => "0000", -- 4-bit A port parity Input
+	DIPB => "0000", -- 4-bit B port parity Input
+	ENA => en_a, -- 1-bit A port Enable Input
+	ENB => en_b, -- 1-bit B port Enable Input
+	REGCEA => '0', -- 1-bit A port register enable input
+	REGCEB => '0', -- 1-bit B port register enable input
+	SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
+	SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
+	WEA => wr_a, -- 4-bit A port Write Enable Input
+	WEB => wr_b -- 4-bit B port Write Enable Input
+);
+-- End of RAMB16_inst instantiation
+	
+	dout_a	<= unsigned(do_a(7 downto 0));
+	dout_b	<= unsigned(do_b(7 downto 0));
+	di_a	<= X"000000" & std_logic_vector(din_a);
+	di_b	<= X"000000" & std_logic_vector(din_b);
+	ad_a	<= '0' & std_logic_vector(addr_a) & "000";
+	ad_b	<= '0' & std_logic_vector(addr_b) & "000";
+	wr_a	<= (3 downto 0 => we_a);
+	wr_b	<= (3 downto 0 => we_b);
+	
+end Structure;
+

lib/misc/lcd_port.vhd

@@ -0,0 +1,69 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+	------------------------------------------------------------------
+entity lcd_port is
+	Port (
+			rst			: in std_logic;
+			clk			: in std_logic;
+			we			: in std_logic;
+			din			: in unsigned(7 downto 0);
+			dout		: out unsigned(7 downto 0);
+			lcd_d		: inout unsigned(3 downto 0);
+			lcd_e		: out std_logic;
+			lcd_rs		: out std_logic;
+			lcd_rw		: out std_logic
+		);
+	end lcd_port;
+
+architecture Behavioral of lcd_port is
+
+	constant clcd_e : integer := 7;
+	constant clcd_rs : integer := 6;
+	constant clcd_rw : integer := 5;
+	
+	type lcd_t is record
+		d	: unsigned(3 downto 0);
+		e	: std_logic;
+		rs	: std_logic;
+		rw	: std_logic;
+	end record;
+	
+	------------------------------------------------------------------
+	begin
+
+	proc_lcd_port:
+	process(rst, clk)
+	variable vlcd : lcd_t;
+	begin
+		if (rst = '1') then
+			dout	<= (others => '0');
+			vlcd.d	:= (others => '0');
+			vlcd.e	:= '0';
+			vlcd.rw	:= '1';
+			vlcd.rs	:= '0';
+		elsif rising_edge(clk) then
+			dout <= unsigned("0000" & lcd_d);
+			if we = '1' then
+				vlcd.d	:= din(3 downto 0);
+				vlcd.e	:= din(clcd_e);
+				vlcd.rs	:= din(clcd_rs);
+				vlcd.rw	:= din(clcd_rw);
+			end if;
+		end if;	
+		if vlcd.rw = '0' then	
+			lcd_d <= unsigned(vlcd.d);
+		else
+			lcd_d <= (others => 'Z');
+		end if;
+		lcd_e	<= vlcd.e;
+		lcd_rs	<= vlcd.rs;
+		lcd_rw	<= vlcd.rw;
+	end process;
+	------------------------------------------------------------------
+
+end Behavioral;

lib/misc/oneshot.vhd

@@ -0,0 +1,223 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    21:52:19 10/22/05
+-- Design Name:    
+-- Module Name:    oneshot - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+--	COMPONENT oneshot
+--	GENERIC (mode : integer);
+--	PORT(
+--		rst : IN std_logic;
+--		clk : IN std_logic;
+--		input : IN std_logic;          
+--		output : OUT std_logic
+--		);
+--	END COMPONENT;
+--
+-- Instantation Template
+--
+--	oneshot_int: oneshot 
+--	GENERIC MAP (
+--		mode => 1)		
+--	PORT MAP(
+--		rst => ,
+--		clk => ,
+--		input => ,
+--		output => 
+--	);
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity oneshot is
+    Generic ( mode : integer range 0 to 2 := 1);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end oneshot;
+
+architecture Behavioral of oneshot is
+
+type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
+
+signal shot_cs : shot_state_t;
+signal shot_ns : shot_state_t;
+
+begin
+
+mode_0:
+if mode = 0 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= shot_neg_st;
+				end if;
+			when shot_neg_st =>
+				shot_ns <= release_neg_st;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= release_pos_st;
+				end if;
+			when others => null;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+mode_1:
+if mode = 1 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when shot_pos_st =>
+				shot_ns <= release_pos_st;
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= release_neg_st;
+				end if;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= shot_pos_st;
+				end if;
+			when others => null;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+	shot_clk: process(rst, clk, shot_ns, input)
+	begin
+		if (rst = '1') then
+			if (input = '1') then
+				shot_cs <= release_pos_st;
+			else
+				shot_cs <= release_neg_st;
+			end if;
+		else
+			if rising_edge(clk) then
+				shot_cs <= shot_ns;
+			end if;
+		end if;
+	end process;
+
+	shot_in: process(rst, clk, input, shot_cs)
+	begin
+		shot_ns <= shot_cs;
+		case shot_cs is
+			when shot_pos_st =>
+				shot_ns <= release_pos_st;
+			when release_pos_st =>
+				if (input = '0') then
+					shot_ns <= shot_neg_st;
+				end if;
+			when shot_neg_st =>
+				shot_ns <= release_neg_st;
+			when release_neg_st =>
+				if (input = '1') then
+					shot_ns <= shot_pos_st;
+				end if;
+		end case;
+	end process;
+
+	shot_out: process(shot_cs)
+	begin
+		output   <= '0';
+		case shot_cs is
+			when shot_pos_st =>
+				output   <= '1';
+			when shot_neg_st =>
+				output   <= '1';
+			when others => null;
+		end case;
+	end process;
+end generate;
+
+			
+
+end Behavioral;

lib/misc/pkg_template.vhd

@@ -0,0 +1,18 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package template_pkg is
+	-- Constants
+	-- Types
+	-- Functions
+
+end template_pkg;
+
+package body template_pkg is
+
+end template_pkg;
+

lib/misc/singleshot.vhd

@@ -0,0 +1,155 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    21:52:19 10/22/05
+-- Design Name:    
+-- Module Name:    singleshot - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+--	COMPONENT singleshot
+--	GENERIC (mode : integer);
+--	PORT(
+--		rst : IN std_logic;
+--		clk : IN std_logic;
+--		input : IN std_logic;          
+--		output : OUT std_logic
+--		);
+--	END COMPONENT;
+--
+-- Instantation Template
+--
+--	singleshot_int: oneshot 
+--	GENERIC MAP (
+--		mode => 1)		
+--	PORT MAP(
+--		rst => ,
+--		clk => ,
+--		input => ,
+--		output => 
+--	);
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity singleshot is
+    Generic ( mode : integer range 0 to 2 := 1);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           input : in std_logic;
+           output : out std_logic);
+end singleshot;
+
+architecture Behavioral of singleshot is
+
+type s_t is (idle, shot_in, active, shot_out);
+signal s, sn : s_t;
+
+begin
+
+process (rst, clk, sn)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			s <= idle;
+		else
+			s <= sn;
+		end if;
+	end if;	
+end process;
+
+mode_1:
+if mode = 1 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				output <= '1';
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+mode_0:
+if mode = 0 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				output <= '1';
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+	process (input, s)
+	begin
+		output <= '0';
+		sn <= s;
+		case s is
+			when idle =>
+			if input = '1' then 
+				sn <= shot_in;
+			end if;	
+			when shot_in =>
+				output <= '1';
+				sn <= active;
+			when active =>
+			if input = '0' then 
+				sn <= shot_out;
+			end if;
+			when shot_out =>
+				output <= '1';
+				sn <= idle;
+			when others => null;
+		end case;	
+	end process;
+end generate;
+
+end Behavioral;

lib/misc/tb_template.vhd

@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_template IS
+END tb_template;
+
+ARCHITECTURE behavior OF tb_template IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT your_comp
+	GENERIC
+	(
+	);
+	PORT
+	(
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+
+	--Inputs
+	signal clk		: STD_LOGIC := '0';
+
+	--Outputs
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: your_comp 
+	GENERIC MAP
+	(
+	)
+	PORT MAP
+	(
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+		
+	END PROCESS;
+	
+END tb_template;

lib/misc/utils_pkg.vhd

@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+package utils_pkg is
+	
+	-- Constants
+
+	-- Functions
+	function NextPowerOfTwo(x : natural) return natural;
+	function NextExpBaseTwo(x : natural) return natural;
+	function GCD(a, b : natural) return natural;
+	function LCM(a, b : natural) return natural;
+	
+end utils_pkg;
+
+
+package body utils_pkg is
+
+	function NextExpBaseTwo(x : natural) return natural is
+	begin
+		return natural(ceil(log2(real(x))));
+	end NextExpBaseTwo;	
+	
+	function NextPowerOfTwo(x : natural) return natural is
+	begin
+
+		return 2**NextExpBaseTwo(x);
+	end NextPowerOfTwo;	
+	
+	function GCD(a, b : natural) return natural is
+	variable aa : natural;
+	variable bb : natural;
+	begin
+		aa := a;
+		bb := b;
+		while bb /= 0 loop
+			if aa > bb then
+				aa := aa - bb;
+			else
+				bb := bb - aa;
+			end if;
+		end loop;
+		
+		return aa;
+
+	end GCD;	
+
+	function LCM(a, b : natural) return natural is
+	begin
+
+		return (a * b)/GCD(a, b);
+
+	end LCM;	
+
+end utils_pkg;
+
+

projects/mips_sys/ise91/mips_sys/mips_sys.prj

@@ -0,0 +1,35 @@
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/misc/dpram_1w2r.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
+vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vhdl work "../../src/ram_ld.vhd"
+vhdl work "../../asm/bootloader/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,35 @@
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w2r.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\asm\bootloader\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise91/mips_sys/ucf/systest.ucf

@@ -0,0 +1,245 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
+
+NET "sys_clk_in" LOC = "AE14";
+#NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+#NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+#NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+#NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+#NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+

projects/mips_sys/ise92/mips_sys/mips_sys.prj

@@ -0,0 +1,45 @@
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd"
+vhdl work "../../src/sys_types.vhd"
+vhdl work "../../src/ram_ld.vhd"
+vhdl work "../../src/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vhdl work "../../src/rom_wb.vhd"
+vhdl work "../../src/ram_wb.vhd"
+vhdl work "../../src/gpio_wb.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,45 @@
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/ucf/systest.ucf

@@ -0,0 +1,245 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
+
+NET "sys_clk_in" LOC = "AE14";
+#NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+#NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+#NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+#NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+#NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -0,0 +1,80 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+# Configs
+vcom -explicit  -93 "../src/sdram_config_sim.vhd"
+
+# Packages
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
+
+# RAMs
+vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
+
+# CPU
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/dcache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/icache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/ram_sim.vhd"
+vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../src/ram_wb.vhd"
+vcom -explicit  -93 "../src/rom_wb.vhd"
+
+# UART
+vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
+
+# GPIO
+vcom -explicit  -93 "../src/gpio_wb.vhd"
+
+# LCD
+vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
+
+# Flash and USB
+vcom -explicit  -93 "../src/sys_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
+
+# FIFOS
+vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+
+# SDRAM
+vcom -explicit  -93 "../../../lib/misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+
+# Top and TB
+vcom -explicit  -93 "../src/mips_sys_sim.vhd"
+vcom -explicit  -93 "../src/tb_mips_sys.vhd"
+
+vsim -t 1ps   -lib work tb_mips_sys
+do {tb_mips_sys.wdo}
+view wave
+view structure
+view signals
+run 5ms
+			 

projects/mips_sys/sim/tb_mips_sys.wdo

@@ -0,0 +1,232 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider UUT
+add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
+add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
+add wave -noupdate -format Literal /tb_mips_sys/dip
+add wave -noupdate -format Literal /tb_mips_sys/btn
+add wave -noupdate -format Literal /tb_mips_sys/led
+add wave -noupdate -format Logic /tb_mips_sys/sys_rx
+add wave -noupdate -format Logic /tb_mips_sys/sys_tx
+add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
+add wave -noupdate -format Logic /tb_mips_sys/refresh
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data
+add wave -noupdate -format Literal /tb_mips_sys/sys_error
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
+add wave -noupdate -divider BUI
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s_ca
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval
+add wave -noupdate -format Literal -label .addr -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.addr
+add wave -noupdate -format Literal -label .dout -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.dout
+add wave -noupdate -format Logic -label .en -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.en
+add wave -noupdate -format Logic -label .re -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.re
+add wave -noupdate -format Literal -label .we -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
+add wave -noupdate -divider USB
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
+add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
+add wave -noupdate -divider Flash
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn
+add wave -noupdate -divider {MIPS TOP}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/badvaddr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_code
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
+add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
+add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -divider {CPU DMEM}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
+add wave -noupdate -divider {CPU IMEM}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
+add wave -noupdate -divider {User ROM}
+add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_clk
+add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr
+add wave -noupdate -divider UUT
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
+add wave -noupdate -divider I-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
+add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
+add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
+add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_data_reg
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_force_we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_was_write
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1129563255 ps} 0}
+configure wave -namecolwidth 218
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {1129448646 ps} {1129766075 ps}

projects/mips_sys/src/mips_pipeline.vhd

@@ -0,0 +1,886 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The pipeline
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+entity pipeline is
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		int			: in  unsigned(5 downto 0);
+		imem_rdy	: in  STD_LOGIC;
+		imem_en		: out STD_LOGIC;
+		imem_addr	: out word_t;
+		imem_data	: in  word_t;
+		dmem_rdy	: in  STD_LOGIC;
+		dmem_en		: out STD_LOGIC;
+		dmem_re		: out STD_LOGIC;
+		dmem_we		: out unsigned(3 downto 0);
+		dmem_addr	: out word_t;
+		dmem_din	: in  word_t;
+		dmem_dout	: out word_t
+	);
+end pipeline;
+
+architecture Behavioral of pipeline is
+
+--------------------------------------------------------------------------
+	COMPONENT reg_dual is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port 
+	(
+		clk_w		: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		wptr		: in  unsigned (addr_width-1 downto 0);
+		din			: in  unsigned (data_width-1 downto 0);
+		rptr_a		: in  unsigned (addr_width-1 downto 0);
+		rptr_b		: in  unsigned (addr_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT idecode_rom is
+	Port 
+	(
+		nop			: in  std_logic;
+		inst_in		: in  word_t;
+		ctrl_out	: out ctrl_lines_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT shifter is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		shift_ctrl	: in  shift_ctrl_t;
+		din			: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT alu is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		op2_shifted	: in  unsigned (data_width-1 downto 0);
+		ctrl		: in  alu_ctrl_t;
+		result		: out unsigned (data_width-1 downto 0);
+		flags		: out alu_flags_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT bcu is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		flags		: out bcu_flags_t
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT cop is
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		IR_valid	: in  STD_LOGIC;
+		IR			: in  word_t;
+		events		: in  event_t;
+		ctrl_in		: in  cop_ctrl_in_t;
+		ctrl_out	: out cop_ctrl_out_t;
+		din			: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		hilo_we		: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		mul_divn	: in  std_logic;
+		start		: in  std_logic;
+		s_un		: in  std_logic;
+		hilo_sel	: in  std_logic;
+		busy		: out std_logic;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	constant RESET_VECTOR	: word_t := X"BFC00000";
+
+	signal ID_stage			: ID_t;
+	signal EX_stage			: EX_t;
+	signal MEM_stage		: MEM_t;
+	signal WB_stage			: WB_t;
+	signal clk_2, clk_1		: STD_LOGIC;
+	signal hdu				: hdu_t;
+	signal cpu_rst			: STD_LOGIC;
+	signal reg_a			: word_t;
+	signal reg_b			: word_t;
+	signal ctrl_lines		: ctrl_lines_t;
+	signal ID_act			: STD_LOGIC;
+	signal EX_act			: STD_LOGIC;
+	signal MEM_act			: STD_LOGIC;
+	signal WB_act			: STD_LOGIC;
+	signal ID_nop			: STD_LOGIC;
+	signal EX_nop			: STD_LOGIC;
+	signal MEM_nop			: STD_LOGIC;
+	signal WB_nop			: STD_LOGIC;
+	signal IF_stall			: STD_LOGIC;
+	signal EX_stall			: STD_LOGIC;
+	signal MEM_stall		: STD_LOGIC;
+	signal WB_stall			: STD_LOGIC;
+	signal cpu_run			: STD_LOGIC;
+	signal branch_ce		: STD_LOGIC;
+	signal run_en			: STD_LOGIC;
+	signal mul_dep			: STD_LOGIC;
+	signal imem_dep			: STD_LOGIC;
+	signal dmem_dep			: STD_LOGIC;
+	signal cop_en			: STD_LOGIC;
+	signal cop_ctrl			: cop_ctrl_in_t;
+	signal cop_din			: word_t;
+	signal cop_dout			: word_t;
+	signal alu_result		: word_t;
+	signal mul_result		: word_t;
+	signal mul_busy			: STD_LOGIC;
+	signal events			: event_t;
+	signal bcu_op_a			: word_t;
+	signal bcu_op_b			: word_t;
+	signal bcu_flags		: bcu_flags_t;
+	
+	attribute ram_style : string;
+	
+	attribute ram_style of reg_a: signal is "distributed";
+	attribute ram_style of reg_b: signal is "distributed";
+
+	signal pc : pc_t;
+	
+--------------------------------------------------------------------------
+begin
+	
+	clk_1					<= clk;
+	clk_2					<= not clk;
+	cpu_run					<= not halt and run_en;
+	
+	events.Int				<= int;
+	events.illegal			<= EX_stage.ctrl.exc_illegal;
+	events.break			<= EX_stage.ctrl.exc_break;
+	events.syscall			<= EX_stage.ctrl.exc_syscall;
+	
+	-- Stall Detection Unit ---------------------------------------------------
+	imem_en 				<= run_en and (not (ID_stage.cop_stat.exc_strobe or mul_dep) or ID_stage.cop_stat.ec) and not dmem_dep;
+
+	ID_nop					<= cpu_rst or imem_dep;
+	EX_nop					<= cpu_rst or EX_stage.cop_stat.exc_strobe or mul_dep;
+	MEM_nop					<= cpu_rst or EX_stage.cop_stat.exc_strobe;
+	WB_nop					<= cpu_rst or EX_stage.cop_stat.exc_strobe or dmem_dep;
+
+	IF_stall				<= not cpu_run or mul_dep or ID_stage.cop_stat.ec or imem_dep or dmem_dep;
+	EX_stall				<= not cpu_run or dmem_dep;
+	MEM_stall				<= not cpu_run or dmem_dep;
+	WB_stall				<= not cpu_run;
+
+	mul_dep					<= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
+	imem_dep				<= not imem_rdy;
+	dmem_dep				<= not dmem_rdy and MEM_stage.ctrl.dmem_en;
+	---------------------------------------------------------------------------
+	
+	events.inst_load_err	<= '1' when EX_stage.epc(1 downto 0) /= "00" else '0';
+	events.inst_priv_addr	<= EX_stage.epc(word_t'left);
+	
+	cop_en					<= not ID_nop;
+	
+--------------------------------------------------------------------------
+-- Muldiv
+--------------------------------------------------------------------------
+inst_muldiv: muldiv
+	PORT MAP
+	(
+		rst			=> cpu_rst,
+		clk			=> clk,
+		hilo_we		=> EX_stage.ctrl.mul_hilo_we,
+		din_hi		=> EX_stage.reg_a,
+		din_lo		=> EX_stage.reg_b,
+		mul_divn	=> EX_stage.ctrl.mul_mul_divn,
+		start		=> EX_stage.ctrl.mul_start,
+		s_un		=> EX_stage.ctrl.mul_s_un,
+		hilo_sel	=> EX_stage.ctrl.mul_hilo_sel,
+		busy		=> mul_busy,
+		dout		=> mul_result
+	);
+
+--------------------------------------------------------------------------
+-- Coprocessor
+--------------------------------------------------------------------------
+inst_cop: cop
+	PORT MAP
+	(
+		rst			=> cpu_rst,
+		clk			=> clk,
+		ce			=> cop_en,
+		events		=> events,
+		IR_valid	=> ID_stage.ctrl.cop_instr_en,
+		IR			=> ID_stage.IR,
+		ctrl_in		=> cop_ctrl,
+		ctrl_out	=> ID_stage.cop_stat,
+		dout		=> cop_dout,
+		din			=> cop_din
+	);
+
+	cop_ctrl.bd_ex		<= EX_stage.ctrl.branch;
+	cop_ctrl.bd_mem		<= MEM_stage.ctrl.branch;
+	cop_ctrl.bd_wb		<= WB_stage.ctrl.branch;
+	cop_ctrl.epc_id		<= ID_stage.epc;
+	cop_ctrl.epc_ex		<= EX_stage.epc;
+	cop_ctrl.epc_mem	<= MEM_stage.epc;
+	cop_ctrl.epc_wb		<= WB_stage.epc;
+	cop_ctrl.dmem_addr	<= EX_stage.va;
+	
+--------------------------------------------------------------------------
+-- IF stage
+--------------------------------------------------------------------------
+	imem_addr		<= pc.curr;
+
+proc_stage_pc:
+	process(pc, rst, IF_stall)
+	begin
+		if rst = '1' then
+			pc.curr	<= RESET_VECTOR after 2 ns;
+		elsif IF_stall = '0' then
+			if pc.is_branch then
+				pc.curr	<= pc.pc_branch after 2 ns;
+			else
+				pc.curr	<= pc.nxt after 2 ns;
+			end if;	
+		end if;	
+	end process;
+
+proc_stage_pc_branch:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if IF_stall = '0' then
+				pc.pc_branch	<= pc.curr + ID_stage.bimm18;
+			end if;	
+		end if;	
+	end process;
+
+proc_stage_pc_next:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			branch_ce	<= '0';
+			if rst = '1' then
+				pc.nxt	<= RESET_VECTOR;
+				pc.last	<= RESET_VECTOR;
+			elsif ID_stage.cop_stat.exc_strobe = '1' then
+				pc.nxt	<= ID_stage.cop_stat.exc_vec;
+			elsif IF_stall = '0' then
+				branch_ce	<= '1';
+				pc.last	<= pc.curr;
+				if ID_stage.ctrl.jump = '1' then
+					pc.nxt	<= ID_stage.jimm32;
+				elsif ID_stage.ctrl.jump_long = '1' then
+					pc.nxt	<= ID_stage.reg_a;
+				else
+					pc.nxt	<= pc.curr + 4;
+				end if;
+			end if;
+		end if;	
+	end process;
+
+proc_stage_branch:
+	process(clk_2)
+	begin
+		if rising_edge(clk_2) and branch_ce = '1' then
+			pc.is_branch	<= false;
+			if EX_stage.ctrl.branch = '1' then
+
+				case EX_stage.ctrl.bc_src is
+
+				when bc_eq_ne =>
+					if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when bc_lez_gtz =>
+					if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when bc_ltz_gez =>
+					if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+	process(rst, clk_1)
+	variable reset_delay : unsigned (5 downto 0);
+	begin
+		if rst = '1' then
+			reset_delay := (others => '1');
+			cpu_rst <= '1';
+			run_en	<= '0';
+		elsif rising_edge(clk_1) then
+			if reset_delay /= (5 downto 0 => '0') then
+				reset_delay := reset_delay - 1;
+			else
+				cpu_rst <= '0';
+			end if;	
+			if reset_delay(reset_delay'left) = '0' then
+				run_en	<= '1';
+			end if;	
+		end if;
+	end process;
+
+--------------------------------------------------------------------------
+-- ID stage
+--------------------------------------------------------------------------
+	ID_act						<= not ID_nop;
+	ID_stage.IR					<= imem_data;
+	ID_stage.pcn				<= pc.curr;
+	ID_stage.op					<= decode_op(ID_stage.IR) when ID_nop = '0' else NOP;
+	ID_stage.jimm32				<= extract_jimm32(ID_stage.IR, ID_stage.pcn);
+	ID_stage.bimm18				<= extract_bimm18(ID_stage.IR, ID_stage.pcn);
+	ID_stage.shamt				<= extract_shamt(ID_stage.IR);
+	ID_stage.reg_a_rptr			<= extract_rs(ID_stage.IR);
+	ID_stage.reg_b_rptr			<= extract_rt(ID_stage.IR);
+	ID_stage.ctrl				<= ctrl_lines;
+	ID_stage.reg_write			<= ID_stage.ctrl.reg_write or ID_stage.cop_stat.reg_write;
+	ID_stage.epc				<= pc.last;
+	
+proc_stage_hdu:
+	process(ID_stage, EX_stage, MEM_stage, WB_stage)
+	variable read_a, read_b : boolean;
+	variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean;
+	variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean;
+	variable reg_ptr_a : reg_ptr_t;
+	variable reg_ptr_b : reg_ptr_t;
+	begin
+		
+		reg_ptr_a			:= ID_stage.reg_a_rptr;
+		reg_ptr_b			:= ID_stage.reg_b_rptr;
+		raw_a_EX			:= reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
+		raw_a_MEM			:= reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
+		raw_a_WB			:= reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
+		raw_b_EX			:= reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
+		raw_b_MEM			:= reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
+		raw_b_WB			:= reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
+
+		hdu.alu_fwd_a_ex	<= raw_a_EX after 1 ns;
+		hdu.alu_fwd_a_mem	<= raw_a_MEM after 1 ns;
+		hdu.alu_fwd_a_wb	<= raw_a_WB after 1 ns;
+		hdu.alu_fwd_b_ex	<= raw_b_EX after 1 ns;
+		hdu.alu_fwd_b_mem	<= raw_b_MEM after 1 ns;
+		hdu.alu_fwd_b_wb	<= raw_b_WB after 1 ns;
+
+	end process;
+	
+proc_stage_fwd_a:
+	process(reg_a, hdu, EX_stage, MEM_stage, WB_stage)
+	variable data : word_t;
+	begin
+		data		:= reg_a;
+		if hdu.alu_fwd_a_ex then
+			data	:= EX_stage.result;
+		elsif hdu.alu_fwd_a_mem then
+			data 	:= MEM_stage.data;
+		elsif hdu.alu_fwd_a_wb then
+			data 	:= WB_stage.data;
+		end if;
+		ID_stage.reg_a	<= data after 2 ns;
+	end process;
+
+proc_stage_fwd_b:
+	process(reg_b, hdu, EX_stage, MEM_stage, WB_stage)
+	variable data : word_t;
+	begin
+		data		:= reg_b;
+		if hdu.alu_fwd_b_ex then
+			data	:= EX_stage.result;
+		elsif hdu.alu_fwd_b_mem then
+			data	:= MEM_stage.data;
+		elsif hdu.alu_fwd_b_wb then
+			data	:= WB_stage.data;
+		end if;
+		ID_stage.reg_b	<= data after 2 ns;
+	end process;
+	
+proc_imm_mux:
+	process(ID_stage)
+	variable data : word_t;
+	begin
+		data := extract_uimm16(ID_stage.IR);
+
+		case ID_stage.ctrl.imm_src is
+
+		when src_imm32 =>
+			data := extract_simm32(ID_stage.IR);
+
+		when src_imm16 =>
+			data := extract_uimm16(ID_stage.IR);
+
+		when src_imm16_high =>
+			data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0');
+			
+		when others => null;
+
+		end case;
+
+		ID_stage.imm <= data after 2 ns;
+
+	end process;
+
+--------------------------------------------------------------------------
+inst_idecode_rom: idecode_rom
+	PORT MAP
+	(
+		nop			=> ID_nop,
+		inst_in		=> ID_stage.IR,
+		ctrl_out	=> ctrl_lines
+	);
+
+inst_reg_dual: reg_dual
+	GENERIC MAP
+	(
+		addr_width	=> reg_ptr_t'length,
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		clk_w		=> clk_1,
+		we			=> WB_stage.wreg_we,
+		en			=> '1',
+		wptr		=> WB_stage.reg_wptr,
+		din			=> WB_stage.data,
+		rptr_a		=> ID_stage.reg_a_rptr,
+		rptr_b		=> ID_stage.reg_b_rptr,
+		dout_a		=> reg_a,
+		dout_b		=> reg_b
+	);
+
+--------------------------------------------------------------------------
+-- EX stage
+--------------------------------------------------------------------------
+	EX_stage.reg_a_rptr		<= extract_rs(EX_stage.IR);
+	EX_stage.reg_b_rptr		<= extract_rt(EX_stage.IR);
+	EX_stage.result			<= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result;
+	EX_act					<= not (EX_nop or EX_stall);
+	
+proc_stage_ID_EX_1:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if cpu_rst = '1' then
+				EX_stage.epc			<= (others => '0');
+			elsif EX_stall = '0' then
+				EX_stage.op				<= ID_stage.op;
+				if ID_nop = '0' then
+					EX_stage.IR			<= ID_stage.IR;
+				else
+					EX_stage.IR			<= (others => '0');
+				end if;
+				EX_stage.ctrl			<= ID_stage.ctrl;
+				EX_stage.reg_write		<= ID_stage.reg_write;
+				EX_stage.pcn			<= ID_stage.pcn;
+				EX_stage.epc			<= ID_stage.epc;
+				EX_stage.cop_stat		<= ID_stage.cop_stat;
+				if EX_nop = '1' then
+					EX_stage.op						<= NOP;
+					EX_stage.IR						<= (others => '0');
+					EX_stage.ctrl					<= ctrl_lines_default;
+					EX_stage.cop_stat.exc_strobe	<= '0';
+					EX_stage.reg_write				<= '0';
+				end if;
+			end if;	
+		end if;
+	end process;
+
+proc_stage_EX_except:
+	process(EX_stage)
+	begin
+		events.data_load_err	<= '0';
+		events.data_store_err	<= '0';
+		events.alu_ovf			<= '0';
+		events.alu_uvf			<= '0';
+		if EX_stage.ctrl.alu_exc_en = '1' then
+			if EX_stage.alu_flags.ovf = '1' then
+				events.alu_ovf	<= '1';
+			end if;	
+			if EX_stage.alu_flags.uvf = '1' then
+				events.alu_uvf	<= '1';
+			end if;	
+		end if;	
+		if EX_stage.ctrl.except_en = '1' then
+			if EX_stage.ctrl.word2_en = '1' then
+				if EX_stage.va(0) = '1' then
+					events.data_load_err	<= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we;
+					events.data_store_err	<= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we;
+				end if;
+			elsif EX_stage.va(1 downto 0) /= "00" then
+				events.data_load_err	<= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we;
+				events.data_store_err	<= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we;
+			end if;	
+		end if;
+	end process;
+	
+proc_stage_DMEM_ADDR:
+	process(clk_1)
+	variable vaddr : word_t;
+	begin
+		if rising_edge(clk_1) and EX_act = '1' then
+			vaddr			:= ID_stage.reg_a + extract_simm32(ID_stage.IR);
+			EX_stage.va		<= vaddr;
+			if ID_stage.cop_stat.RE = '1' then
+				EX_stage.pa_off	<= not vaddr(1 downto 0);
+			else	
+				EX_stage.pa_off	<= vaddr(1 downto 0);
+			end if;
+		end if;
+	end process;
+	dmem_we		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
+	dmem_re		<= not EX_stage.ctrl.dmem_we;
+	dmem_en		<= EX_stage.ctrl.dmem_en and not(ID_stage.cop_stat.exc_strobe) after 1 ns;
+	dmem_dout	<= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
+	dmem_addr	<= EX_stage.va;
+	cop_din		<= EX_stage.reg_b;
+	
+--------------------------------------------------------------------------
+proc_wptr_mux:
+	process(EX_stage)
+	variable opclass : opcode_t;
+	variable reg_wptr : reg_ptr_t;
+	begin
+	
+		opclass := extract_opc(EX_stage.IR);
+		case opclass is
+		when "000000" =>
+			reg_wptr					:= extract_rd(EX_stage.IR);
+		when others =>
+			reg_wptr					:= extract_rt(EX_stage.IR);
+		end case;
+		
+		EX_stage.wreg_we <= EX_stage.reg_write after 1 ns;
+		if reg_wptr = "00000" then
+			EX_stage.wreg_we <= '0' after 1 ns;
+		end if;	
+
+		EX_stage.reg_wptr	<= reg_wptr after 1 ns;
+		case EX_stage.ctrl.wptr_srcsel is
+			when wptr_src_imm =>
+				EX_stage.reg_wptr	<= reg_wptr after 1 ns;
+
+			when wptr_src_const =>
+				EX_stage.reg_wptr	<= to_unsigned(31, reg_ptr_t'length) after 1 ns;
+				EX_stage.wreg_we <= '1' after 1 ns;
+
+			when others => null;
+		end case;
+
+	end process;
+
+--------------------------------------------------------------------------
+proc_stage_fwd_reg_a:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if EX_act = '1' then
+				EX_stage.reg_a	<= ID_stage.reg_a;
+				bcu_op_a		<= ID_stage.reg_a;
+			end if;
+		end if;
+	end process;
+
+proc_stage_fwd_reg_b:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if EX_act = '1' then
+				EX_stage.reg_b	<= ID_stage.reg_b;
+				bcu_op_b		<= ID_stage.reg_b;
+			end if;
+		end if;
+	end process;
+
+alu_op1_mux:
+	process(EX_stage)
+	variable data : word_t;
+	begin
+	
+		data := EX_stage.reg_a;
+
+--		case EX_stage.ctrl.alu.op1_src is
+--
+--		when alu_src_reg =>
+--			data := EX_stage.reg_a;
+--
+--		when alu_src_muldiv =>
+--			data := mul_result;
+--
+--		when others => null;
+--
+--		end case;
+
+		EX_stage.alu_op1 <= data;
+
+	end process;
+
+alu_op2_mux:
+	process(clk_1)
+	variable data : word_t;
+	begin
+
+		if rising_edge(clk_1) and EX_act = '1' then
+			data := ID_stage.reg_b;
+
+			case ID_stage.ctrl.alu.op2_src is
+
+			when alu_src_reg =>
+				data := ID_stage.reg_b;
+
+			when alu_src_imm =>
+				data := ID_stage.imm;
+
+			when others => null;
+
+			end case;
+
+			EX_stage.alu_op2 <= data;
+		end if;
+
+	end process;
+
+shifter_sa_mux:
+	process(clk_1)
+	variable data 		: shamt_t;
+	variable data_inv 	: shamt_t;
+
+	begin
+		if rising_edge(clk_1) and EX_act = '1' then
+			data 		:= ID_stage.reg_a(4 downto 0);
+			case ID_stage.ctrl.shamt2_srcsel is
+
+				when sa_src_reg =>
+					data := ID_stage.reg_a(4 downto 0);
+
+				when sa_src_imm =>
+					data := ID_stage.shamt;
+
+				when others => null;
+
+			end case;
+			data_inv := not data + 1;
+			if ID_stage.ctrl.alu.shift_right = '0' then
+				EX_stage.shift_ctrl.shamt_rnd	<= data_inv after 2 ns;
+			else	
+				EX_stage.shift_ctrl.shamt_rnd	<= data after 2 ns;
+			end if;
+			EX_stage.shift_ctrl.shamt_nrm	<= data after 1 ns;
+			EX_stage.shift_ctrl.shift_right	<= ID_stage.ctrl.alu.shift_right;
+			EX_stage.shift_ctrl.shift_arith	<= ID_stage.ctrl.alu.shift_arith;
+		end if;
+		
+	end process;
+
+--------------------------------------------------------------------------
+inst_shifter: shifter
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		shift_ctrl	=> EX_stage.shift_ctrl,
+		din			=> EX_stage.reg_b,
+		dout		=> EX_stage.alu_op2_s
+	);
+
+inst_alu: alu
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		op1_in			=> EX_stage.alu_op1,
+		op2_in			=> EX_stage.alu_op2,
+		op2_shifted		=> EX_stage.alu_op2_s,
+		ctrl			=> EX_stage.ctrl.alu,
+		result			=> alu_result,
+		flags			=> EX_stage.alu_flags
+	);
+
+inst_bcu: bcu
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		op1_in		=> bcu_op_a,
+		op2_in		=> bcu_op_b,
+		flags		=> bcu_flags
+	);
+
+--------------------------------------------------------------------------
+-- MEM stage
+--------------------------------------------------------------------------
+	MEM_act					<= not (MEM_nop or MEM_stall);
+
+proc_stage_MEM_n:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if MEM_stall = '0' then
+				MEM_stage.op				<= EX_stage.op;
+				MEM_stage.wreg_we		<= EX_stage.wreg_we;
+				MEM_stage.ctrl			<= EX_stage.ctrl;
+				MEM_stage.pcn			<= EX_stage.pcn;
+				MEM_stage.epc			<= EX_stage.epc;
+				MEM_stage.pa_off		<= EX_stage.pa_off;
+				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
+				MEM_stage.cop_stat		<= EX_stage.cop_stat;
+				if EX_stage.ctrl.dmem_en = '1' then
+					MEM_stage.ex_result		<= EX_stage.reg_b;
+				else
+					MEM_stage.ex_result		<= EX_stage.result;
+				end if;	
+				if MEM_nop = '1' then
+					MEM_stage.op		<= NOP;
+					MEM_stage.wreg_we	<= '0';
+					MEM_stage.ctrl		<= ctrl_lines_default;
+	--				MEM_stage.epc		<= (others => '0');
+	--				MEM_stage.pcn		<= (others => '0');
+	--				MEM_stage.pa_off	<= (others => '0');
+	--				MEM_stage.reg_wptr	<= (others => '0');
+	--				MEM_stage.ex_result	<= (others => '0');
+				end if;
+			end if;	
+		end if;
+	end process;
+
+proc_stage_MEM_mux:
+	process(MEM_stage, dmem_din, cop_dout)
+	variable temp1 : word_t;
+	variable temp2 : word_t;
+	variable data : word_t;
+	variable be : unsigned(3 downto 0);
+	begin
+		data	:= MEM_stage.ex_result;
+		be		:= load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
+		if MEM_stage.cop_stat.cop_access = '1' then
+			data		:= cop_dout;
+		elsif MEM_stage.ctrl.reg_link = '1' then
+			data		:= MEM_stage.pcn + 4;
+		elsif MEM_stage.ctrl.dmem_en = '1' then
+			temp1		:= load_shift(dmem_din,  MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
+			temp2		:= load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
+			if be(0) = '1' then
+				data(7 downto 0)	:= temp2(7 downto 0);
+			end if;	
+			if be(1) = '1' then
+				data(15 downto 8)	:= temp2(15 downto 8);
+			end if;	
+			if be(2) = '1' then
+				data(23 downto 16)	:= temp2(23 downto 16);
+			end if;	
+			if be(3) = '1' then
+				data(31 downto 24)	:= temp2(31 downto 24);
+			end if;	
+		end if;
+		MEM_stage.data				<= data after 1 ns;
+		
+	end process;
+
+--------------------------------------------------------------------------
+-- WB stage
+--------------------------------------------------------------------------
+	WB_act					<= not (WB_nop or WB_stall);
+
+proc_stage_WB_p:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if WB_stall = '0' then
+				WB_stage.op				<= MEM_stage.op;
+				WB_stage.ctrl			<= MEM_stage.ctrl;
+				WB_stage.wreg_we		<= MEM_stage.wreg_we;
+				WB_stage.reg_wptr		<= MEM_stage.reg_wptr;
+				WB_stage.data			<= MEM_stage.data;
+				WB_stage.epc			<= MEM_stage.epc;
+				if WB_nop = '1' then
+					WB_stage.op				<= NOP;
+					WB_stage.ctrl			<= ctrl_lines_default;
+					WB_stage.wreg_we		<= '0';
+	--				WB_stage.epc			<= (others => '0');
+	--				WB_stage.reg_wptr		<= (others => '0');
+	--				WB_stage.data			<= (others => '0');
+				end if;	
+			end if;	
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end Behavioral;

projects/mips_sys/src/mips_sys.vhd

@@ -0,0 +1,872 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+library work;
+use work.mips_types.all;
+--use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.vga_types.all;
+use work.sys_types.all;
+
+
+ENTITY mips_sys IS
+GENERIC
+(
+	sys_freq			: integer		    := 100E6;
+	ddr_phaseshift		: integer			:= 0;
+	ddr_frequency_hz	: integer			:= 100E6
+);
+PORT
+(
+	sys_rst_n_in		: in std_logic;
+	sys_clk_in			: in std_logic;
+
+	-- Buttons and LEDs
+	sys_btn				: in unsigned(4 downto 0);
+	sys_dip				: in unsigned(7 downto 0);
+	sys_led				: out unsigned(8 downto 0);
+
+	-- UART
+	sys_rx				: in std_logic;
+	sys_tx				: out std_logic;
+
+	-- LCD
+	sys_lcd_d			: inout unsigned(3 downto 0);
+	sys_lcd_e			: out std_logic;
+	sys_lcd_rs			: out std_logic;
+	sys_lcd_rw			: out std_logic;
+
+	-- DDR SDRAM
+	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
+	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
+	sys_sdr_cke_q		: out std_logic;    -- clock enable
+	sys_sdr_cs_qn		: out std_logic;    -- /chip select
+	sys_sdr_ras_qn		: out std_logic;    -- /ras
+	sys_sdr_cas_qn		: out std_logic;    -- /cas
+	sys_sdr_we_qn		: out std_logic;    -- /write enable
+	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
+	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
+	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
+	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
+	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
+	sys_sdr_clk_fb		: in std_logic;
+	
+	-- VGA
+	sys_vga_clk			: out std_logic;
+	sys_vga_red			: out unsigned(7 downto 0);
+	sys_vga_green		: out unsigned(7 downto 0);
+	sys_vga_blue		: out unsigned(7 downto 0);
+	sys_vga_blank_n		: out std_logic;
+	sys_vga_sync_n		: out std_logic;
+	sys_vga_hsync		: out std_logic;
+	sys_vga_vsync		: out std_logic;
+
+	sys_usb_d			: inout unsigned(15 downto 0);
+	sys_usb_a			: out unsigned(1 downto 0);
+	sys_usb_csn			: out std_logic;
+	sys_usb_wrn			: out std_logic;
+	sys_usb_rdn			: out std_logic;
+	sys_usb_rstn		: out std_logic;
+	sys_usb_int			: in std_logic;
+
+	sys_flash_d			: inout unsigned(31 downto 0);
+	sys_flash_a			: out unsigned(24 downto 0);
+	sys_flash_ce		: out std_logic;
+	sys_flash_wrn		: out std_logic;
+	sys_flash_rdn		: out std_logic;
+	sys_flash_rstn		: out std_logic;
+	sys_flash_byten		: out std_logic;	
+	sys_error			: out unsigned(1 downto 0) -- indicates Errors
+	
+);
+--	attribute BUFFER_TYPE : string;
+--	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
+--	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
+
+END mips_sys;
+
+ARCHITECTURE behavior OF mips_sys IS 
+
+	COMPONENT mips_top
+	Port 
+	(
+		debug		: out unsigned(1 downto 0);
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		DAT_O		: out word_t;
+		WE_O		: out STD_LOGIC;
+		SEL_O		: out unsigned(3 downto 0);
+		CYC_O		: out STD_LOGIC;
+		STB_O		: out STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
+		INT			: in  unsigned (5 downto 0)
+		
+	);
+	END COMPONENT;
+	
+	COMPONENT rom_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT ram_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT lcd_port
+	PORT 
+	(
+		rst			: in std_logic;
+		clk			: in std_logic;
+		we			: in std_logic;
+		din			: in unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		lcd_d		: inout unsigned(3 downto 0);
+		lcd_e		: out std_logic;
+		lcd_rs		: out std_logic;
+		lcd_rw		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT async_port_wb
+	GENERIC
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		async_timespec	: async_timespec_t
+	);
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_rst	: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT uart_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		INT_RX_O	: out STD_LOGIC;
+		INT_TX_O	: out STD_LOGIC;
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT gpio_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+
+		sys_gpo0	: out unsigned(31 downto 0);
+		sys_gpo1	: out unsigned(31 downto 0);
+		sys_gpi0	: in  unsigned(31 downto 0);
+		sys_gpi1	: in  unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT vga_frontend
+	GENERIC
+	(
+		sys_freq					: integer;
+		fifo_depth					: integer;
+		fifo_almost_full_thresh		: natural;
+		fifo_almost_empty_thresh	: natural;
+		tsvga						: vga_timespec_t
+	);
+	PORT
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(31 downto 0);
+		MDAT_O			: out unsigned(31 downto 0);
+		
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+	END COMPONENT;
+
+	signal rst			: std_logic;
+	signal clk			: std_logic;
+	signal clk270		: std_logic;
+	signal clk270var	: std_logic;
+	signal rst_in		: std_logic;
+	signal int_uart_rx	: std_logic;
+	signal locked		: std_logic;
+	signal usb_addr 	: unsigned(31 downto 0);
+	signal flash_addr	: unsigned(31 downto 0);
+
+	-- Arbiter
+	constant ARB_MAX_MASTER	: natural := 2;
+	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	
+	-- J-Bus signals
+	signal INT	 		: unsigned(5 downto 0);
+	signal MDAT_I		: word_t;
+	signal MDAT_O 		: word_t;
+	signal ADDR_O 		: word_t;
+	signal SEL_O 		: unsigned(3 downto 0);
+	signal WE_O 		: std_logic;
+	signal CYC_O 		: std_logic;
+	signal STB_O 		: std_logic;
+	signal ACK_I		: std_logic;
+	signal SRDY_I		: std_logic;
+	signal MRDY_O		: std_logic;
+
+	-- CPU Master
+	signal MRDY_O_cpu	: std_logic;
+	signal MDAT_O_cpu	: word_t;
+	signal ADDR_O_cpu	: word_t;
+	signal SEL_O_cpu	: unsigned(3 downto 0);
+	signal WE_O_cpu		: std_logic;
+	signal CYC_O_cpu	: std_logic;
+	signal STB_O_cpu	: std_logic;
+	signal SRDY_I_cpu	: std_logic;
+	signal ACK_I_cpu	: std_logic;
+
+	-- VGA Master
+	signal MRDY_O_vga	: std_logic;
+	signal MDAT_O_vga	: word_t;
+	signal ADDR_O_vga	: word_t;
+	signal SEL_O_vga	: unsigned(3 downto 0);
+	signal WE_O_vga		: std_logic;
+	signal CYC_O_vga	: std_logic;
+	signal STB_O_vga	: std_logic;
+	signal SRDY_I_vga	: std_logic;
+	signal ACK_I_vga	: std_logic;
+
+	-- Slaves
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal SDAT_O_flash	: unsigned(31 downto 0);
+
+	signal CYC_I_usb	: std_logic;
+	signal ACK_O_usb	: std_logic;
+	signal SRDY_O_usb	: std_logic;
+	signal SDAT_O_usb	: unsigned(31 downto 0);
+
+	signal CYC_I_sdram	: std_logic;
+	signal ACK_O_sdram	: std_logic;
+	signal SRDY_O_sdram	: std_logic;
+	signal SDAT_O_sdram	: unsigned(31 downto 0);
+
+	signal CYC_I_ram	: std_logic;
+	signal ACK_O_ram	: std_logic;
+	signal SRDY_O_ram	: std_logic;
+	signal SDAT_O_ram	: unsigned(31 downto 0);
+
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal SDAT_O_rom	: unsigned(31 downto 0);
+
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal SDAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_urom	: std_logic;
+	signal ACK_O_urom	: std_logic;
+	signal SRDY_O_urom	: std_logic;
+	signal SDAT_O_urom	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal SDAT_O_uart	: unsigned(31 downto 0);
+
+	signal CYC_I_vga	: std_logic;
+	signal ACK_O_vga	: std_logic;
+	signal SRDY_O_vga	: std_logic;
+	signal SDAT_O_vga	: unsigned(31 downto 0);
+
+	signal gpo0			: unsigned(31 downto 0);
+	signal gpo1			: unsigned(31 downto 0);
+	signal gpi0			: unsigned(31 downto 0);
+	signal gpi1			: unsigned(31 downto 0);
+
+	signal debug		: unsigned(1 downto 0);
+
+	-- DDR SDRAM
+	constant BURST_LEN		: natural := 2;
+
+	
+--	attribute rom_style: string;
+--	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
+
+	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
+	signal mem_area : mem_area_t;
+
+BEGIN
+
+	gpi0(4 downto 0)	<= sys_btn;
+	gpi1(7 downto 0)	<= sys_dip;
+	sys_led				<= gpo0(8 downto 0);
+	sys_error			<= debug;
+	rst_in 				<= not sys_rst_n_in;
+	rst					<= not locked;
+	sys_usb_rstn		<= not gpo1(0);
+	sys_flash_byten		<= '1';
+	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
+	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
+
+
+	---------------------------------------------------------------
+	-- Arbiter
+	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
+	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
+	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
+	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
+	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
+	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
+	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
+	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
+	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
+	ACK_I_cpu	<= ACK_I and arb_gnt(0);
+	ACK_I_vga	<= ACK_I and arb_gnt(1);
+	
+	arb_req(0)	<= CYC_O_cpu;
+	arb_req(1)	<= CYC_O_vga;
+	
+	
+arbiter_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				arb_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif arb_req(arb_idx) = '0' then
+				if arb_idx /= ARB_MAX_MASTER-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				arb_gnt	<= (others => '0');
+				arb_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+	
+int_sample:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4);
+		end if;
+	end process;
+	
+mem_mux:
+	process(ADDR_O)
+	begin
+		mem_area	<= mem_dead;
+		if ADDR_O(31 downto 28) = X"0" then
+			mem_area	<= mem_urom;
+		elsif ADDR_O(31 downto 28) = X"A" then
+			if ADDR_O(26) = '1' then
+				mem_area	<= mem_flash;
+			elsif ADDR_O(17 downto 16) = "00" then
+				mem_area	<= mem_gpio;
+			elsif ADDR_O(17 downto 16) = "01" then
+				mem_area	<= mem_uart;
+			elsif ADDR_O(17 downto 16) = "10" then
+				mem_area	<= mem_usb;
+			elsif ADDR_O(17 downto 16) = "11" then
+				mem_area	<= mem_vga;
+			end if;	
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
+			mem_area	<= mem_rom;
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
+			mem_area	<= mem_ram;
+		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
+			mem_area	<= mem_sdram;
+		end if;
+	end process;	
+
+signal_mux:
+	process(mem_area, CYC_O)
+	begin
+	
+		CYC_I_urom		<= '0';
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_usb		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_ram		<= '0';
+		CYC_I_sdram		<= '0';
+		CYC_I_vga		<= '0';
+		
+		case mem_area is
+
+		when mem_urom =>
+			CYC_I_urom		<= CYC_O;
+			
+		when mem_gpio =>
+			CYC_I_gpio		<= CYC_O;
+
+		when mem_uart =>
+			CYC_I_uart		<= CYC_O;
+
+		when mem_flash =>
+			CYC_I_flash		<= CYC_O;
+
+		when mem_usb =>
+			CYC_I_usb		<= CYC_O;
+
+		when mem_rom =>
+			CYC_I_rom		<= CYC_O;
+
+		when mem_ram =>
+			CYC_I_ram		<= CYC_O;
+
+		when mem_sdram =>
+			CYC_I_sdram		<= CYC_O;
+		
+		when mem_vga =>
+			CYC_I_vga		<= CYC_O;
+
+		when others => null;
+		
+		end case;
+		
+	end process;
+
+--	sys_user_rom_addr	<= ADDR_O;
+--	sys_user_rom_clk	<= clk;
+--	sys_user_rom_en		<= CYC_I_urom and STB_O;
+--	SDAT_O_urom			<= sys_user_rom_din;
+	SRDY_O_urom			<= CYC_I_urom;
+	
+urom_ack_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ACK_O_urom	<= CYC_I_urom and STB_O;
+		end if;
+	end process;
+	
+------------------------------------------------------------------
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
+ 	MDAT_I		<=	SDAT_O_sdram when CYC_I_sdram = '1' else
+					SDAT_O_ram when CYC_I_ram = '1' else
+					SDAT_O_rom when CYC_I_rom = '1' else
+					SDAT_O_urom when CYC_I_urom = '1' else
+					SDAT_O_flash when CYC_I_flash = '1' else
+					SDAT_O_usb when CYC_I_usb = '1' else
+					SDAT_O_uart when CYC_I_uart = '1' else
+					SDAT_O_vga when CYC_I_vga = '1' else
+					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
+
+------------------------------------------------------------------
+inst_mips_top: mips_top
+	PORT MAP
+	(
+		debug			=> debug,
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		ACK_I			=> ACK_I_cpu,
+		SRDY_I			=> SRDY_I_cpu,
+		MRDY_O			=> MRDY_O_cpu,
+		CYC_O			=> CYC_O_cpu,
+		STB_O			=> STB_O_cpu,
+		WE_O			=> WE_O_cpu,
+		SEL_O			=> SEL_O_cpu,
+		DAT_I			=> MDAT_I,
+		DAT_O			=> MDAT_O_cpu,
+		ADDR_O			=> ADDR_O_cpu,
+		INT				=> INT
+	);
+
+inst_ram_wb : ram_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_ram,
+		STB_I	=> STB_O,
+		SEL_I	=> SEL_O,
+		WE_I	=> WE_O,
+		ACK_O	=> ACK_O_ram,
+		SRDY_O	=> SRDY_O_ram,
+		MRDY_I	=> MRDY_O,
+		ADDR_I	=> ADDR_O,
+		DAT_I	=> MDAT_O,
+		DAT_O	=> SDAT_O_ram
+	);
+
+inst_rom_wb : rom_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_rom,
+		STB_I	=> STB_O,
+		ACK_O	=> ACK_O_rom,
+		MRDY_I	=> MRDY_O,
+		SRDY_O	=> SRDY_O_rom,
+		ADDR_I	=> ADDR_O,
+		DAT_O	=> SDAT_O_rom
+	);
+
+
+inst_lcd_port: lcd_port
+	PORT MAP
+	(
+		clk => clk,
+		rst => rst,
+		we => '0',
+		din => X"00",
+		dout => open,
+		lcd_d => sys_lcd_d,
+		lcd_e => sys_lcd_e,
+		lcd_rs => sys_lcd_rs,
+		lcd_rw => sys_lcd_rw
+	);
+	
+inst_gpio_wb : gpio_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_gpio,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_gpio,
+
+		sys_gpo0	=> gpo0,
+		sys_gpo1	=> gpo1,
+		sys_gpi0	=> gpi0,
+		sys_gpi1	=> gpi1
+	);
+
+
+inst_flash_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 25,
+		data_width		=> 32,
+		async_timespec	=> ts_flash
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_flash,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> flash_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_flash,
+		async_a		=> sys_flash_a,
+		async_d		=> sys_flash_d,
+		async_cs	=> sys_flash_ce,
+		async_wr	=> sys_flash_wrn,
+		async_rd	=> sys_flash_rdn,
+		async_rst	=> sys_flash_rstn
+	);
+
+inst_usb_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 2,
+		data_width		=> 16,
+		async_timespec	=> ts_usb
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_usb,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_usb,
+		SRDY_O		=> SRDY_O_usb,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> usb_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_usb,
+		async_a		=> sys_usb_a,
+		async_d		=> sys_usb_d,
+		async_cs	=> sys_usb_csn,
+		async_wr	=> sys_usb_wrn,
+		async_rd	=> sys_usb_rdn,
+		async_rst	=> open
+	);
+
+inst_uart_wb : uart_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_uart,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_uart,
+		INT_RX_O	=> int_uart_rx,
+		INT_TX_O	=> open,
+		ser_rx		=> sys_rx,
+		ser_tx		=> sys_tx
+	);
+
+
+inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
+	GENERIC MAP
+	(
+		BL			=> BURST_LEN,
+		f_sysclk	=> ddr_frequency_hz,
+		fifo_depth	=> 6
+	)
+	PORT MAP
+	(
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		CLK270_I		=> clk270,
+		CLK270VAR_I		=> clk270var,
+		
+		CYC_I			=> CYC_I_sdram,
+		STB_I			=> STB_O,
+		SEL_I			=> SEL_O,
+		WE_I			=> WE_O,
+		ACK_O			=> ACK_O_sdram,
+		MRDY_I			=> MRDY_O,
+		SRDY_O			=> SRDY_O_sdram,
+		ADDR_I			=> ADDR_O,
+		DAT_I			=> MDAT_O,
+		DAT_O			=> SDAT_O_sdram,
+
+		-- SDRAM signals
+		sd_clk_p		=> sys_sdr_clk_p,
+		sd_clk_n		=> sys_sdr_clk_n,
+		sd_cke			=> sys_sdr_cke_q,
+		sd_cs_n			=> sys_sdr_cs_qn,
+		sd_cas_n		=> sys_sdr_cas_qn,
+		sd_ras_n		=> sys_sdr_ras_qn,
+		sd_we_n			=> sys_sdr_we_qn,
+		sd_addr			=> sys_sdr_a_q,
+		sd_ba			=> sys_sdr_ba_q,
+		sd_dm			=> sys_sdr_dm_q,
+		sd_dqs			=> sys_sdr_dqs_q,
+		sd_data			=> sys_sdr_data
+		
+	);
+
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst_in,   -- external async reset, low active
+		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> open
+	);
+
+inst_vga_frontend : vga_frontend
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 1860,
+		fifo_almost_empty_thresh	=> 256,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> rst,
+		CLK_I			=> clk,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_O_vga,
+		STB_O			=> STB_O_vga,
+		WE_O			=> WE_O_vga,
+		SEL_O			=> SEL_O_vga,
+		ACK_I			=> ACK_I_vga,
+		SRDY_I			=> SRDY_I_vga,
+		MRDY_O			=> MRDY_O_vga,
+		ADDR_O			=> ADDR_O_vga,
+		MDAT_I			=> MDAT_I,
+		MDAT_O			=> MDAT_O_vga,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_I_vga,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_O_vga,
+		SRDY_O			=> SRDY_O_vga,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> MDAT_O,
+		SDAT_O			=> SDAT_O_vga,
+		
+		-- VGA signals
+		vga_clk_out		=> sys_vga_clk,
+		vga_red			=> sys_vga_red,
+		vga_green		=> sys_vga_green,
+		vga_blue		=> sys_vga_blue,
+		vga_blank_n		=> sys_vga_blank_n,
+		vga_sync_n		=> sys_vga_sync_n,
+		vga_hsync		=> sys_vga_hsync,
+		vga_vsync		=> sys_vga_vsync	
+	);
+
+	------------------------------------------------------------------
+END;

projects/mips_sys/src/mips_sys_cfg.vhd

@@ -0,0 +1,19 @@
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+configuration cpu_irom of cpu_embedded is
+	for rtl 
+		for inst_irom : irom
+			use entity work.irom(loadable);
+		end for;
+	end for;
+end configuration cpu_irom;
+
+configuration system_xrom of systest is
+	for behavior 
+		for inst_xrom : xrom
+			use entity work.xrom(loadable);
+		end for;
+	end for;
+end configuration system_xrom;

projects/mips_sys/src/mips_sys_sim.vhd

@@ -0,0 +1,878 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+library work;
+use work.mips_types.all;
+--use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.vga_types.all;
+use work.sys_types.all;
+
+
+ENTITY mips_sys IS
+GENERIC
+(
+	sys_freq			: integer		    := 100E6;
+	ddr_phaseshift		: integer			:= 0;
+	ddr_frequency_hz	: integer			:= 100E6
+);
+PORT
+(
+	sys_rst_n_in		: in std_logic;
+	sys_clk_in			: in std_logic;
+
+	-- Buttons and LEDs
+	sys_btn				: in unsigned(4 downto 0);
+	sys_dip				: in unsigned(7 downto 0);
+	sys_led				: out unsigned(8 downto 0);
+
+	-- UART
+	sys_rx				: in std_logic;
+	sys_tx				: out std_logic;
+
+	-- User ROM
+	sys_user_rom_addr	: out word_t;
+	sys_user_rom_din	: in  word_t;
+	sys_user_rom_clk	: out std_logic;
+	sys_user_rom_en		: out std_logic;
+
+	-- LCD
+	sys_lcd_d			: inout unsigned(3 downto 0);
+	sys_lcd_e			: out std_logic;
+	sys_lcd_rs			: out std_logic;
+	sys_lcd_rw			: out std_logic;
+
+	-- DDR SDRAM
+	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
+	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
+	sys_sdr_cke_q		: out std_logic;    -- clock enable
+	sys_sdr_cs_qn		: out std_logic;    -- /chip select
+	sys_sdr_ras_qn		: out std_logic;    -- /ras
+	sys_sdr_cas_qn		: out std_logic;    -- /cas
+	sys_sdr_we_qn		: out std_logic;    -- /write enable
+	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
+	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
+	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
+	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
+	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
+	sys_sdr_clk_fb		: in std_logic;
+	
+	-- VGA
+	sys_vga_clk			: out std_logic;
+	sys_vga_red			: out unsigned(7 downto 0);
+	sys_vga_green		: out unsigned(7 downto 0);
+	sys_vga_blue		: out unsigned(7 downto 0);
+	sys_vga_blank_n		: out std_logic;
+	sys_vga_sync_n		: out std_logic;
+	sys_vga_hsync		: out std_logic;
+	sys_vga_vsync		: out std_logic;
+
+	sys_usb_d			: inout unsigned(15 downto 0);
+	sys_usb_a			: out unsigned(1 downto 0);
+	sys_usb_csn			: out std_logic;
+	sys_usb_wrn			: out std_logic;
+	sys_usb_rdn			: out std_logic;
+	sys_usb_rstn		: out std_logic;
+	sys_usb_int			: in std_logic;
+
+	sys_flash_d			: inout unsigned(31 downto 0);
+	sys_flash_a			: out unsigned(24 downto 0);
+	sys_flash_ce		: out std_logic;
+	sys_flash_wrn		: out std_logic;
+	sys_flash_rdn		: out std_logic;
+	sys_flash_rstn		: out std_logic;
+	sys_flash_byten		: out std_logic;	
+	sys_error			: out unsigned(1 downto 0) -- indicates Errors
+	
+);
+--	attribute BUFFER_TYPE : string;
+--	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
+--	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
+
+END mips_sys;
+
+ARCHITECTURE behavior OF mips_sys IS 
+
+	COMPONENT mips_top
+	Port 
+	(
+		debug		: out unsigned(1 downto 0);
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		DAT_O		: out word_t;
+		WE_O		: out STD_LOGIC;
+		SEL_O		: out unsigned(3 downto 0);
+		CYC_O		: out STD_LOGIC;
+		STB_O		: out STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
+		INT			: in  unsigned (5 downto 0)
+		
+	);
+	END COMPONENT;
+	
+	COMPONENT rom_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT ram_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT lcd_port
+	PORT 
+	(
+		rst			: in std_logic;
+		clk			: in std_logic;
+		we			: in std_logic;
+		din			: in unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		lcd_d		: inout unsigned(3 downto 0);
+		lcd_e		: out std_logic;
+		lcd_rs		: out std_logic;
+		lcd_rw		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT async_port_wb
+	GENERIC
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		async_timespec	: async_timespec_t
+	);
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_rst	: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT uart_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		INT_RX_O	: out STD_LOGIC;
+		INT_TX_O	: out STD_LOGIC;
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT gpio_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+
+		sys_gpo0	: out unsigned(31 downto 0);
+		sys_gpo1	: out unsigned(31 downto 0);
+		sys_gpi0	: in  unsigned(31 downto 0);
+		sys_gpi1	: in  unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT vga_frontend
+	GENERIC
+	(
+		sys_freq					: integer;
+		fifo_depth					: integer;
+		fifo_almost_full_thresh		: natural;
+		fifo_almost_empty_thresh	: natural;
+		tsvga						: vga_timespec_t
+	);
+	PORT
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(31 downto 0);
+		MDAT_O			: out unsigned(31 downto 0);
+
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+	END COMPONENT;
+
+	signal rst			: std_logic;
+	signal clk			: std_logic;
+	signal clk270		: std_logic;
+	signal clk270var	: std_logic;
+	signal rst_in		: std_logic;
+	signal int_uart_rx	: std_logic;
+	signal locked		: std_logic;
+	signal usb_addr 	: unsigned(31 downto 0);
+	signal flash_addr	: unsigned(31 downto 0);
+
+	-- Arbiter
+	constant ARB_MAX_MASTER	: natural := 2;
+	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	
+	-- J-Bus signals
+	signal INT	 		: unsigned(5 downto 0);
+	signal MDAT_I		: word_t;
+	signal MDAT_O 		: word_t;
+	signal ADDR_O 		: word_t;
+	signal SEL_O 		: unsigned(3 downto 0);
+	signal WE_O 		: std_logic;
+	signal CYC_O 		: std_logic;
+	signal STB_O 		: std_logic;
+	signal ACK_I		: std_logic;
+	signal SRDY_I		: std_logic;
+	signal MRDY_O		: std_logic;
+
+	-- CPU Master
+	signal MRDY_O_cpu	: std_logic;
+	signal MDAT_O_cpu	: word_t;
+	signal ADDR_O_cpu	: word_t;
+	signal SEL_O_cpu	: unsigned(3 downto 0);
+	signal WE_O_cpu		: std_logic;
+	signal CYC_O_cpu	: std_logic;
+	signal STB_O_cpu	: std_logic;
+	signal SRDY_I_cpu	: std_logic;
+	signal ACK_I_cpu	: std_logic;
+
+	-- VGA Master
+	signal MRDY_O_vga	: std_logic;
+	signal MDAT_O_vga	: word_t;
+	signal ADDR_O_vga	: word_t;
+	signal SEL_O_vga	: unsigned(3 downto 0);
+	signal WE_O_vga		: std_logic;
+	signal CYC_O_vga	: std_logic;
+	signal STB_O_vga	: std_logic;
+	signal SRDY_I_vga	: std_logic;
+	signal ACK_I_vga	: std_logic;
+
+	-- Slaves
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal SDAT_O_flash	: unsigned(31 downto 0);
+
+	signal CYC_I_usb	: std_logic;
+	signal ACK_O_usb	: std_logic;
+	signal SRDY_O_usb	: std_logic;
+	signal SDAT_O_usb	: unsigned(31 downto 0);
+
+	signal CYC_I_sdram	: std_logic;
+	signal ACK_O_sdram	: std_logic;
+	signal SRDY_O_sdram	: std_logic;
+	signal SDAT_O_sdram	: unsigned(31 downto 0);
+
+	signal CYC_I_ram	: std_logic;
+	signal ACK_O_ram	: std_logic;
+	signal SRDY_O_ram	: std_logic;
+	signal SDAT_O_ram	: unsigned(31 downto 0);
+
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal SDAT_O_rom	: unsigned(31 downto 0);
+
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal SDAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_urom	: std_logic;
+	signal ACK_O_urom	: std_logic;
+	signal SRDY_O_urom	: std_logic;
+	signal SDAT_O_urom	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal SDAT_O_uart	: unsigned(31 downto 0);
+
+	signal CYC_I_vga	: std_logic;
+	signal ACK_O_vga	: std_logic;
+	signal SRDY_O_vga	: std_logic;
+	signal SDAT_O_vga	: unsigned(31 downto 0);
+
+	signal gpo0			: unsigned(31 downto 0);
+	signal gpo1			: unsigned(31 downto 0);
+	signal gpi0			: unsigned(31 downto 0);
+	signal gpi1			: unsigned(31 downto 0);
+
+	signal debug		: unsigned(1 downto 0);
+
+	-- DDR SDRAM
+	constant BURST_LEN		: natural := 2;
+
+	
+--	attribute rom_style: string;
+--	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
+
+	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
+	signal mem_area : mem_area_t;
+
+BEGIN
+
+	gpi0(4 downto 0)	<= sys_btn;
+	gpi1(7 downto 0)	<= sys_dip;
+	sys_led				<= gpo0(8 downto 0);
+	sys_error			<= debug;
+	rst_in 				<= not sys_rst_n_in;
+	rst					<= not locked;
+	sys_usb_rstn		<= not gpo1(0);
+	sys_flash_byten		<= '1';
+	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
+	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
+
+
+	---------------------------------------------------------------
+	-- Arbiter
+	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
+	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
+	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
+	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
+	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
+	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
+	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
+	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
+	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
+	ACK_I_cpu	<= ACK_I and arb_gnt(0);
+	ACK_I_vga	<= ACK_I and arb_gnt(1);
+	
+	arb_req(0)	<= CYC_O_cpu;
+	arb_req(1)	<= CYC_O_vga;
+	
+	
+arbiter_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				arb_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif arb_req(arb_idx) = '0' then
+				if arb_idx /= ARB_MAX_MASTER-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				arb_gnt	<= (others => '0');
+				arb_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+	
+int_sample:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4);
+		end if;
+	end process;
+	
+mem_mux:
+	process(ADDR_O)
+	begin
+		mem_area	<= mem_dead;
+		if ADDR_O(31 downto 28) = X"0" then
+			mem_area	<= mem_urom;
+		elsif ADDR_O(31 downto 28) = X"A" then
+			if ADDR_O(26) = '1' then
+				mem_area	<= mem_flash;
+			elsif ADDR_O(17 downto 16) = "00" then
+				mem_area	<= mem_gpio;
+			elsif ADDR_O(17 downto 16) = "01" then
+				mem_area	<= mem_uart;
+			elsif ADDR_O(17 downto 16) = "10" then
+				mem_area	<= mem_usb;
+			elsif ADDR_O(17 downto 16) = "11" then
+				mem_area	<= mem_vga;
+			end if;	
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
+			mem_area	<= mem_rom;
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
+			mem_area	<= mem_ram;
+		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
+			mem_area	<= mem_sdram;
+		end if;
+	end process;	
+
+signal_mux:
+	process(mem_area, CYC_O)
+	begin
+	
+		CYC_I_urom		<= '0';
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_usb		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_ram		<= '0';
+		CYC_I_sdram		<= '0';
+		CYC_I_vga		<= '0';
+		
+		case mem_area is
+
+		when mem_urom =>
+			CYC_I_urom		<= CYC_O;
+			
+		when mem_gpio =>
+			CYC_I_gpio		<= CYC_O;
+
+		when mem_uart =>
+			CYC_I_uart		<= CYC_O;
+
+		when mem_flash =>
+			CYC_I_flash		<= CYC_O;
+
+		when mem_usb =>
+			CYC_I_usb		<= CYC_O;
+
+		when mem_rom =>
+			CYC_I_rom		<= CYC_O;
+
+		when mem_ram =>
+			CYC_I_ram		<= CYC_O;
+
+		when mem_sdram =>
+			CYC_I_sdram		<= CYC_O;
+		
+		when mem_vga =>
+			CYC_I_vga		<= CYC_O;
+
+		when others => null;
+		
+		end case;
+		
+	end process;
+
+	sys_user_rom_addr	<= ADDR_O;
+	sys_user_rom_clk	<= clk;
+	sys_user_rom_en		<= CYC_I_urom and STB_O;
+	SDAT_O_urom			<= sys_user_rom_din;
+	SRDY_O_urom			<= CYC_I_urom;
+	
+urom_ack_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ACK_O_urom	<= CYC_I_urom and STB_O;
+		end if;
+	end process;
+	
+------------------------------------------------------------------
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
+ 	MDAT_I		<=	SDAT_O_sdram when CYC_I_sdram = '1' else
+					SDAT_O_ram when CYC_I_ram = '1' else
+					SDAT_O_rom when CYC_I_rom = '1' else
+					SDAT_O_urom when CYC_I_urom = '1' else
+					SDAT_O_flash when CYC_I_flash = '1' else
+					SDAT_O_usb when CYC_I_usb = '1' else
+					SDAT_O_uart when CYC_I_uart = '1' else
+					SDAT_O_vga when CYC_I_vga = '1' else
+					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
+
+------------------------------------------------------------------
+inst_mips_top: mips_top
+	PORT MAP
+	(
+		debug			=> debug,
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		ACK_I			=> ACK_I_cpu,
+		SRDY_I			=> SRDY_I_cpu,
+		MRDY_O			=> MRDY_O_cpu,
+		CYC_O			=> CYC_O_cpu,
+		STB_O			=> STB_O_cpu,
+		WE_O			=> WE_O_cpu,
+		SEL_O			=> SEL_O_cpu,
+		DAT_I			=> MDAT_I,
+		DAT_O			=> MDAT_O_cpu,
+		ADDR_O			=> ADDR_O_cpu,
+		INT				=> INT
+	);
+
+inst_ram_wb : ram_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_ram,
+		STB_I	=> STB_O,
+		SEL_I	=> SEL_O,
+		WE_I	=> WE_O,
+		ACK_O	=> ACK_O_ram,
+		SRDY_O	=> SRDY_O_ram,
+		MRDY_I	=> MRDY_O,
+		ADDR_I	=> ADDR_O,
+		DAT_I	=> MDAT_O,
+		DAT_O	=> SDAT_O_ram
+	);
+
+inst_rom_wb : rom_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_rom,
+		STB_I	=> STB_O,
+		ACK_O	=> ACK_O_rom,
+		MRDY_I	=> MRDY_O,
+		SRDY_O	=> SRDY_O_rom,
+		ADDR_I	=> ADDR_O,
+		DAT_O	=> SDAT_O_rom
+	);
+
+
+inst_lcd_port: lcd_port
+	PORT MAP
+	(
+		clk => clk,
+		rst => rst,
+		we => '0',
+		din => X"00",
+		dout => open,
+		lcd_d => sys_lcd_d,
+		lcd_e => sys_lcd_e,
+		lcd_rs => sys_lcd_rs,
+		lcd_rw => sys_lcd_rw
+	);
+	
+inst_gpio_wb : gpio_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_gpio,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_gpio,
+
+		sys_gpo0	=> gpo0,
+		sys_gpo1	=> gpo1,
+		sys_gpi0	=> gpi0,
+		sys_gpi1	=> gpi1
+	);
+
+
+inst_flash_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 25,
+		data_width		=> 32,
+		async_timespec	=> ts_flash
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_flash,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> flash_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_flash,
+		async_a		=> sys_flash_a,
+		async_d		=> sys_flash_d,
+		async_cs	=> sys_flash_ce,
+		async_wr	=> sys_flash_wrn,
+		async_rd	=> sys_flash_rdn,
+		async_rst	=> sys_flash_rstn
+	);
+
+inst_usb_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 2,
+		data_width		=> 16,
+		async_timespec	=> ts_usb
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_usb,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_usb,
+		SRDY_O		=> SRDY_O_usb,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> usb_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_usb,
+		async_a		=> sys_usb_a,
+		async_d		=> sys_usb_d,
+		async_cs	=> sys_usb_csn,
+		async_wr	=> sys_usb_wrn,
+		async_rd	=> sys_usb_rdn,
+		async_rst	=> open
+	);
+
+inst_uart_wb : uart_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_uart,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_uart,
+		INT_RX_O	=> int_uart_rx,
+		INT_TX_O	=> open,
+		ser_rx		=> sys_rx,
+		ser_tx		=> sys_tx
+	);
+
+
+inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
+	GENERIC MAP
+	(
+		BL			=> BURST_LEN,
+		f_sysclk	=> ddr_frequency_hz,
+		fifo_depth	=> 6
+	)
+	PORT MAP
+	(
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		CLK270_I		=> clk270,
+		CLK270VAR_I		=> clk270var,
+		
+		CYC_I			=> CYC_I_sdram,
+		STB_I			=> STB_O,
+		SEL_I			=> SEL_O,
+		WE_I			=> WE_O,
+		ACK_O			=> ACK_O_sdram,
+		MRDY_I			=> MRDY_O,
+		SRDY_O			=> SRDY_O_sdram,
+		ADDR_I			=> ADDR_O,
+		DAT_I			=> MDAT_O,
+		DAT_O			=> SDAT_O_sdram,
+
+		-- SDRAM signals
+		sd_clk_p		=> sys_sdr_clk_p,
+		sd_clk_n		=> sys_sdr_clk_n,
+		sd_cke			=> sys_sdr_cke_q,
+		sd_cs_n			=> sys_sdr_cs_qn,
+		sd_cas_n		=> sys_sdr_cas_qn,
+		sd_ras_n		=> sys_sdr_ras_qn,
+		sd_we_n			=> sys_sdr_we_qn,
+		sd_addr			=> sys_sdr_a_q,
+		sd_ba			=> sys_sdr_ba_q,
+		sd_dm			=> sys_sdr_dm_q,
+		sd_dqs			=> sys_sdr_dqs_q,
+		sd_data			=> sys_sdr_data
+		
+	);
+
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst_in,   -- external async reset, low active
+		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> open
+	);
+
+inst_vga_frontend : vga_frontend
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 2000,
+		fifo_almost_empty_thresh	=> 1600,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> rst,
+		CLK_I			=> clk,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_O_vga,
+		STB_O			=> STB_O_vga,
+		WE_O			=> WE_O_vga,
+		SEL_O			=> SEL_O_vga,
+		ACK_I			=> ACK_I_vga,
+		SRDY_I			=> SRDY_I_vga,
+		MRDY_O			=> MRDY_O_vga,
+		ADDR_O			=> ADDR_O_vga,
+		MDAT_I			=> MDAT_I,
+		MDAT_O			=> MDAT_O_vga,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_I_vga,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_O_vga,
+		SRDY_O			=> SRDY_O_vga,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> MDAT_O,
+		SDAT_O			=> SDAT_O_vga,
+
+		-- VGA signals
+		vga_clk_out		=> sys_vga_clk,
+		vga_red			=> sys_vga_red,
+		vga_green		=> sys_vga_green,
+		vga_blue		=> sys_vga_blue,
+		vga_blank_n		=> sys_vga_blank_n,
+		vga_sync_n		=> sys_vga_sync_n,
+		vga_hsync		=> sys_vga_hsync,
+		vga_vsync		=> sys_vga_vsync	
+	);
+
+	------------------------------------------------------------------
+END;

projects/mips_sys/src/ram_ld.vhd

@@ -0,0 +1,173 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY ram IS
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	COMPONENT dpram_2w2r
+	Generic 
+	(
+		addr_width : integer;
+		data_width : integer
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+	
+	signal jtag_clk		: STD_LOGIC;
+	signal jtag_we		: unsigned(3 downto 0);
+	signal jtag_addr	: unsigned (15 downto 0);
+	signal jtag_dout	: unsigned (31 downto 0);
+	signal jtag_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	
+BEGIN
+
+gen_sram:
+	for i in 0 to 3 generate
+	begin
+	inst_dpram_2w2r : dpram_2w2r
+		GENERIC MAP
+		(
+			addr_width	=> 11,
+			data_width	=> 8
+		)
+		PORT MAP
+		(
+			clk_a		=> clk,
+			en_a		=> ce,
+			we_a		=> we(i),
+			addr_a		=> addr(12 downto 2),
+			din_a		=> din((i+1)*8-1 downto i*8),
+			dout_a		=> dout((i+1)*8-1 downto i*8),
+
+			clk_b		=> jtag_clk,
+			en_b		=> jtag_we(i),
+			we_b		=> jtag_we(i),
+			addr_b		=> jtag_addr(10 downto 0),
+			din_b		=> jtag_din((i+1)*8-1 downto i*8),
+			dout_b		=> jtag_dout((i+1)*8-1 downto i*8)
+		);
+	end generate;
+	
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_addr	<= user_regi(user_regi'left downto jtag_dout'length);
+	jtag_din	<= user_regi(jtag_dout'length-1 downto 0);
+	jtag_clk	<= bs_update1;
+	jtag_we		<= (3 downto 0 => bs_sel);
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+end behavior;

projects/mips_sys/src/ram_sim.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram(index)(7 downto 0)		<= din(7 downto 0);
+			end if;	
+			if we(1) = '1' then
+				sram(index)(15 downto 8)	<= din(15 downto 8);
+			end if;	
+			if we(2) = '1' then
+				sram(index)(23 downto 16)	<= din(23 downto 16);
+			end if;	
+			if we(3) = '1' then
+				sram(index)(31 downto 24)	<= din(31 downto 24);
+			end if;	
+			dout <= sram(index);
+		end if;	
+	end process;
+	
+end behavior;

projects/mips_sys/src/sdram_config.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+	
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+	
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+	
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 5;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 222; -- µs
+
+	subtype user_tag_t is unsigned(3 downto 0);
+
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

projects/mips_sys/src/sdram_config_sim.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+	
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+	
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+	
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 5;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 22; -- µs
+
+	subtype user_tag_t is unsigned(3 downto 0);
+
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

projects/mips_sys/src/tb_mips_sys.vhd

@@ -0,0 +1,258 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+ENTITY tb_mips_sys IS
+END tb_mips_sys;
+
+ARCHITECTURE behavior OF tb_mips_sys IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal sys_rst_n_in : std_logic := '0';
+	signal sys_clk_in : std_logic := '1';
+	signal dip  : unsigned(7 downto 0) := (others => '0');
+	signal btn  : unsigned(4 downto 0) := (others => '0');
+	signal led : unsigned(8 downto 0);
+	signal sys_rx : std_logic := '1';
+	signal sys_tx : std_logic;
+	
+	signal sys_lcd_d			: unsigned(3 downto 0);
+	signal sys_lcd_e			: std_logic;
+	signal sys_lcd_rs			: std_logic;
+	signal sys_lcd_rw			: std_logic;
+
+	signal refresh        : boolean:= true;
+
+	signal sys_sdr_clk_p		: std_logic;    -- ddr_sdram_clock
+	signal sys_sdr_clk_n		: std_logic;    -- /ddr_sdram_clock
+	signal sys_sdr_cke_q		: std_logic;    -- clock enable
+	signal sys_sdr_cs_qn		: std_logic;    -- /chip select
+	signal sys_sdr_ras_qn		: std_logic;    -- /ras
+	signal sys_sdr_cas_qn		: std_logic;    -- /cas
+	signal sys_sdr_we_qn		: std_logic;    -- /write enable
+	signal sys_sdr_dm_q			: unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
+	signal sys_sdr_dqs_q		: unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
+	signal sys_sdr_ba_q			: unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
+	signal sys_sdr_a_q			: unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
+	signal sys_sdr_data			: unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
+
+	signal sys_error			: unsigned(1 downto 0); -- indicates DCM Errors
+	signal sys_sdr_clk_fb		: std_logic;
+
+	constant UROM_ADDR_WIDTH	: integer := 18;
+	signal sys_user_rom_clk		: std_logic;   
+	signal sys_user_rom_en		: std_logic;   
+	signal sys_user_rom_din		: word_t;  
+	signal sys_user_rom_addr	: word_t;   
+
+	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
+	signal sys_usb_a			: unsigned(1 downto 0);
+	signal sys_usb_csn			: std_logic;
+	signal sys_usb_wrn			: std_logic;
+	signal sys_usb_rdn			: std_logic;
+	signal sys_usb_rstn			: std_logic;
+	signal sys_usb_int			: std_logic := '0';
+	
+	signal sys_flash_d			: word_t;
+	signal sys_flash_a			: unsigned(24 downto 0);
+	signal sys_flash_ce			: std_logic;
+	signal sys_flash_wrn		: std_logic;
+	signal sys_flash_rdn		: std_logic;
+	signal sys_flash_rstn		: std_logic;
+	signal sys_flash_byten		: std_logic;
+	signal flash_reg			: word_t;
+
+	type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
+	signal urom_data : urom_data_t;
+	
+BEGIN
+
+uut: entity work.mips_sys
+--	GENERIC MAP
+--	(
+--		ddr_phaseshift => 90,
+--		ddr_frequency_hz => 100E6
+--	)
+	PORT MAP
+	(
+		sys_rst_n_in => sys_rst_n_in,
+		sys_clk_in => sys_clk_in,
+		sys_btn => btn,
+		sys_dip => dip,
+		sys_led => led,
+
+		sys_rx => sys_rx,
+		sys_tx => sys_tx,
+
+		sys_lcd_d => sys_lcd_d,
+		sys_lcd_e => sys_lcd_e,
+		sys_lcd_rs => sys_lcd_rs,
+		sys_lcd_rw => sys_lcd_rw,
+
+		sys_user_rom_addr => sys_user_rom_addr,
+		sys_user_rom_din => sys_user_rom_din,
+		sys_user_rom_en => sys_user_rom_en,
+		sys_user_rom_clk => sys_user_rom_clk,
+
+		sys_sdr_clk_p => sys_sdr_clk_p,
+		sys_sdr_clk_n => sys_sdr_clk_n,
+		sys_sdr_cke_q => sys_sdr_cke_q,
+		sys_sdr_clk_fb => sys_sdr_clk_fb,
+		sys_sdr_cs_qn => sys_sdr_cs_qn,
+		sys_sdr_ras_qn => sys_sdr_ras_qn,
+		sys_sdr_cas_qn => sys_sdr_cas_qn,
+		sys_sdr_we_qn => sys_sdr_we_qn,
+		sys_sdr_dm_q => sys_sdr_dm_q,
+		sys_sdr_dqs_q => sys_sdr_dqs_q,
+		sys_sdr_ba_q => sys_sdr_ba_q,
+		sys_sdr_a_q => sys_sdr_a_q,
+		sys_sdr_data => sys_sdr_data,
+
+		sys_usb_d		=> sys_usb_d,
+		sys_usb_a		=> sys_usb_a,
+		sys_usb_csn		=> sys_usb_csn,
+		sys_usb_wrn		=> sys_usb_wrn,
+		sys_usb_rdn		=> sys_usb_rdn,
+		sys_usb_rstn	=> sys_usb_rstn,
+		sys_usb_int		=> sys_usb_int,
+
+		sys_flash_d		=> sys_flash_d,
+		sys_flash_a		=> sys_flash_a,
+		sys_flash_ce	=> sys_flash_ce,
+		sys_flash_wrn	=> sys_flash_wrn,
+		sys_flash_rdn	=> sys_flash_rdn,
+		sys_flash_rstn	=> sys_flash_rstn,
+		sys_flash_byten	=> sys_flash_byten,
+
+		sys_error => sys_error
+	);
+
+   -- MICRON DDR SDRAM Simulation Model
+   i_mt46v16m16_0 : entity work.mt46v16m16 
+      port map (
+         dq    => std_logic_vector(sys_sdr_data(15 downto 0)),
+         dqs   => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
+         addr  => std_logic_vector(sys_sdr_a_q),
+         ba    => std_logic_vector(sys_sdr_ba_q),
+         clk   => sys_sdr_clk_p,
+         clk_n => sys_sdr_clk_n,
+         cke   => sys_sdr_cke_q,
+         cs_n  => sys_sdr_cs_qn,
+         ras_n => sys_sdr_ras_qn,
+         cas_n => sys_sdr_cas_qn,
+         we_n  => sys_sdr_we_qn,
+         dm    => std_logic_vector(sys_sdr_dm_q(1 downto 0))
+         );
+
+   -- MICRON DDR SDRAM Simulation Model
+   i_mt46v16m16_1 : entity work.mt46v16m16 
+      port map (
+         dq    => std_logic_vector(sys_sdr_data(31 downto 16)),
+         dqs   => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
+         addr  => std_logic_vector(sys_sdr_a_q),
+         ba    => std_logic_vector(sys_sdr_ba_q),
+         clk   => sys_sdr_clk_p,
+         clk_n => sys_sdr_clk_n,
+         cke   => sys_sdr_cke_q,
+         cs_n  => sys_sdr_cs_qn,
+         ras_n => sys_sdr_ras_qn,
+         cas_n => sys_sdr_cas_qn,
+         we_n  => sys_sdr_we_qn,
+         dm    => std_logic_vector(sys_sdr_dm_q(3 downto 2))
+         );
+
+	sys_sdr_clk_fb   <= sys_sdr_clk_p after 2300 ps;
+	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
+
+	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		sys_clk_in <= not sys_clk_in;
+	end process;
+
+UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
+	type file_t is file of integer;
+	file load_urom : file_t open read_mode is "test_bui.bin";
+	variable instr : integer;
+	variable index : natural;
+	variable temp : signed(31 downto 0);
+	begin
+		if sys_rst_n_in = '0' then
+			index := 0;
+			while not endfile(load_urom) loop
+				read(load_urom, instr);
+				temp	:= to_signed(instr, word_t'length);
+				urom_data(index) <= unsigned(temp);
+				index := index + 1;
+			end loop;
+		elsif rising_edge(sys_user_rom_clk) and sys_user_rom_en = '1' then
+			index := to_integer(sys_user_rom_addr(UROM_ADDR_WIDTH+1 downto 2));
+			sys_user_rom_din <= urom_data(index);
+		end if;	
+	end process;
+
+FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
+	begin
+		if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
+			flash_reg <= sys_flash_d;
+		end if;
+	end process;
+		
+FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
+	begin
+		sys_flash_d <= (others => 'Z') after 10 ns;
+		if sys_flash_rdn = '0' and sys_flash_ce = '1' then
+			sys_flash_d <= flash_reg after 10 ns;
+		end if;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		sys_rst_n_in <= '1';
+		wait for 200000*CLK_PERIOD;
+		
+		loop
+		wait for 251*CLK_PERIOD;
+		btn(4)		<= '1';			
+		wait for 311*CLK_PERIOD;
+		btn(4)		<= '0';			
+		end loop;
+		wait; 
+	
+	end process;
+	
+END;

projects/mips_sys/tools/insrom.rb

@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2008 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end

projects/mips_sys/tools/irom.vhd.tpl

@@ -0,0 +1,29 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- ROM_INSERT_HERE
+

projects/mips_sys/tools/irom_ld.vhd.tpl

@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

projects/mips_sys/tools/make

@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip

projects/mips_sys/tools/rom.tcl.tpl

@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

projects/mips_sys/tools/src/ramgen.c

@@ -0,0 +1,385 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"ram"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 2\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom_tcl[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+

projects/mips_sys/tools/src/romgen.c

@@ -0,0 +1,368 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"rom"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 1\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+	char name_rom_tcl[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+