Compare commits
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jens
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4f6b9e2082 |
@@ -4,7 +4,7 @@ TOOLS_DIR=../../../tools
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CFLAGS=-Os -I. -I../ -msoft-float -march=r3000
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LFLAGS=-M -T bootloader.ld
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LIB_DIRS=-L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
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LIBS=-lc -lm -lgcc
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LIBS=-lc -lgcc
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CC=mipsel-elf-gcc
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LD=mipsel-elf-ld
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@@ -145,13 +145,9 @@ void Exec_at(void *pEntry)
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__asm
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(
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"jr %[pEntry]\n" // jump entry
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:
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: [pEntry] "r" (pEntry)
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);
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__asm
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(
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"lw $v0, 16($sp)\n"
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"nop\n"
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"jr $v0\n" // jump entry
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"rfe\n"
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);
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@@ -160,7 +156,6 @@ void Exec_at(void *pEntry)
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".set reorder\n"
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);
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}
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void PrintCPUinfo(void)
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{
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int result, rev_id;
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@@ -1,10 +1,10 @@
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MEMORY
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{
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rom : ORIGIN = 0xBFC00000, LENGTH = 0x00002000 /* 8K */
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sram : ORIGIN = 0x40000000, LENGTH = 0x02000000 /* 32M */
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ram : ORIGIN = 0x40000000, LENGTH = 0x00002000 /* 8K */
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}
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stack_ptr = 0x7FFFFFF0;
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stack_ptr = 0x7FFFEFF0;
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baudrate = 0x0D;
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sys_led_port = 0xA0000000;
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sys_uart_data = 0xA0010000;
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@@ -40,8 +40,9 @@ SECTIONS
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*(.rodata*)
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} > rom
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.data ORIGIN(rom) :
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.data ORIGIN(ram) :
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{
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*(.data)
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} > rom
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*(.*data) *(.*bss) *(.*common)
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} > ram
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}
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@@ -20,10 +20,11 @@ _exc_handler:
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# Set Error LED and ExcCode LEDs
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# Get Cause
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mfc0 $26, $13
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la $27, sys_led_port
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li $27, 0xC0000000
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srl $26, 2
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andi $26, 0x000F
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or $26, $27
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la $27, sys_led_port
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sw $26, 0($27)
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# wait for all interrupts = 0
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@@ -9,9 +9,9 @@ _init:
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.set noreorder
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# set uart
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la $8, sys_uart_baud
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addiu $9, $0, baudrate
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sb $9, 0($8)
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# la $8, sys_uart_baud
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# addiu $9, $0, baudrate
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# sb $9, 0($8)
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# set stack pointer
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la $sp, stack_ptr
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Vendored
+1
-1
@@ -2,7 +2,7 @@
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PROJECT="mips_top"
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DIST_FILE="./files.dist"
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DIST_DIR="./release/mips.r10"
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DIST_DIR="./release/mips.r10a"
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# ---------------------------------------------------------------
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mkdir -p $DIST_DIR/src
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@@ -31,9 +31,11 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
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add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
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add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
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add wave -noupdate -format Literal /tb_mips_top/flash_be_n
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add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
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add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
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add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
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add wave -noupdate -format Literal /tb_mips_top/sram_be_n
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add wave -noupdate -divider ALU
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
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||||
@@ -49,8 +51,13 @@ add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_rst
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/run_en
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
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WaveRestoreCursors {{Cursor 1} {1375665640 ps} 0}
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configure wave -namecolwidth 188
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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@@ -64,4 +71,4 @@ configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {1260 us}
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WaveRestoreZoom {0 ps} {1680 us}
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@@ -40,6 +40,7 @@ package async_defs is
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pol_cs => '0',
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pol_oe => '0',
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pol_we => '0',
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||||
pol_be => '0',
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pol_rst => '0'
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||||
);
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||||
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||||
@@ -54,6 +55,7 @@ package async_defs is
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pol_cs => '0',
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pol_oe => '0',
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pol_we => '0',
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pol_be => '0',
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pol_rst => '0'
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||||
);
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||||
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||||
@@ -159,7 +159,6 @@ END COMPONENT;
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signal tram_dout : tram_data_t;
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signal tram_addr_wr : unsigned(cache_index_width-1 downto 0);
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signal tram_din : tram_data_t;
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signal tram_re : std_logic;
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signal tram_we : std_logic;
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signal fill_count : natural range 0 to 2**word_index_width-1;
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||||
@@ -255,7 +254,7 @@ inst_tag_ram : dpram_1w1r
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clka => CLK_I,
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clkb => CLK_I,
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en_a => '1',
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en_b => tram_re,
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en_b => '1',
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we_a => tram_we,
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addr_a => tram_addr_wr,
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addr_b => tram_addr_rd,
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@@ -327,7 +326,6 @@ cache_state:
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request_count_rst <= '0';
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CYC_O <= '0';
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STB_O <= '0';
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tram_re <= '0';
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was_miss <= '0';
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cache_fill <= '0';
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tram_addr_wr <= to_unsigned(flush_index_count, cache_index_width);
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@@ -342,7 +340,6 @@ cache_state:
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when ready =>
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cache_busy <= '0';
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cpu_reg_en <= '1';
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tram_re <= cpu_en;
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if cpu_en2 = '1' then
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if cache_hit = '0' and cpu_we_reg = '0' then
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sn <= mem_request;
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@@ -361,7 +358,6 @@ cache_state:
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sn <= ready;
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if cpu_en = '1' then
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cpu_reg_en <= '1';
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tram_re <= '1';
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end if;
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end if;
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when mem_request =>
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@@ -395,7 +391,6 @@ cache_state:
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cache_entry_in.valid <= '1';
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sn <= rd_cache;
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when rd_cache =>
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tram_re <= '1';
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was_miss <= '1';
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sn <= ready;
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||||
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@@ -124,7 +124,6 @@ END COMPONENT;
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signal tag_ram_data_rd : tag_ram_data_t;
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signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
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signal tag_ram_data_wr : tag_ram_data_t;
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signal tag_ram_re : std_logic;
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signal tag_ram_we : std_logic;
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signal ram_index_count : natural range 0 to 2**word_index_width-1;
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@@ -165,7 +164,7 @@ inst_tag_ram : dpram_1w1r
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clka => CLK_I,
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clkb => CLK_I,
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en_a => '1',
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en_b => tag_ram_re,
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en_b => '1',
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we_a => tag_ram_we,
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||||
addr_a => tag_ram_addr_wr,
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addr_b => tag_ram_addr_rd,
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||||
@@ -230,7 +229,6 @@ cache_state:
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CYC_O <= '0';
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STB_O <= '0';
|
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data_ram_re <= '0';
|
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tag_ram_re <= '0';
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was_miss <= '0';
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data_write <= '0';
|
||||
tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
|
||||
@@ -253,7 +251,6 @@ cache_state:
|
||||
elsif cpu_en = '1' then
|
||||
cpu_reg_en <= '1';
|
||||
data_ram_re <= '1';
|
||||
tag_ram_re <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when flush =>
|
||||
@@ -267,7 +264,6 @@ cache_state:
|
||||
if cpu_en = '1' then
|
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cpu_reg_en <= '1';
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||||
data_ram_re <= '1';
|
||||
tag_ram_re <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when mem_request =>
|
||||
@@ -302,7 +298,6 @@ cache_state:
|
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sn <= rd_cache;
|
||||
|
||||
when rd_cache =>
|
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tag_ram_re <= '1';
|
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data_ram_re <= '1';
|
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was_miss <= '1';
|
||||
sn <= ready;
|
||||
|
||||
@@ -147,6 +147,7 @@ architecture behavior of biu is
|
||||
signal DAT_I_dmem_rd : word_t;
|
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signal DAT_O_dmem_wr : word_t;
|
||||
signal SEL_O_dmem_wr : unsigned(3 downto 0);
|
||||
signal SEL_O_dmem_rd : unsigned(3 downto 0);
|
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signal dcached : std_logic;
|
||||
signal dcache_en : std_logic;
|
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signal uncached_access : std_logic;
|
||||
@@ -308,7 +309,9 @@ inst_bout_fifo: entity work.fifo_sync_dist
|
||||
ADDR_O_dcache when dcache_mem_gnt = '1' else
|
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ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
|
||||
|
||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
|
||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
||||
SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
|
||||
|
||||
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
@@ -382,6 +385,7 @@ dmem_rd_regs:
|
||||
if rising_edge(CLK_I) then
|
||||
if cpu_dmem_en = '1' and busy = '0' then
|
||||
ADDR_O_dmem_rd <= cpu_dmem_addr;
|
||||
SEL_O_dmem_rd <= cpu_dmem_be;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@@ -33,7 +33,7 @@ entity pipeline is
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
@@ -174,13 +174,11 @@ architecture Behavioral of pipeline is
|
||||
signal clk_2, clk_1 : STD_LOGIC;
|
||||
signal hdu : hdu_t;
|
||||
signal sdu : sdu_t;
|
||||
signal cpu_rst : STD_LOGIC;
|
||||
signal reg_a : word_t;
|
||||
signal reg_b : word_t;
|
||||
signal ctrl_lines : ctrl_lines_t;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
signal branch_ce : STD_LOGIC;
|
||||
signal run_en : STD_LOGIC;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
signal mul_dep : STD_LOGIC;
|
||||
signal imem_dep : STD_LOGIC;
|
||||
signal dmem_dep : STD_LOGIC;
|
||||
@@ -213,7 +211,7 @@ begin
|
||||
|
||||
clk_1 <= clk;
|
||||
clk_2 <= not clk;
|
||||
cpu_run <= run_en;
|
||||
cpu_run <= ce;
|
||||
|
||||
-- Stall Detection Unit ---------------------------------------------------
|
||||
sdu.ID_nop <= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
|
||||
@@ -238,7 +236,7 @@ begin
|
||||
inst_muldiv: muldiv
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
hilo_we => EX_stage.ctrl.mul_hilo_we,
|
||||
din_hi => EX_stage.reg_a,
|
||||
@@ -257,7 +255,7 @@ inst_muldiv: muldiv
|
||||
inst_cop: cop
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
sdu => sdu,
|
||||
events => MEM_stage.events,
|
||||
@@ -362,25 +360,6 @@ proc_stage_branch:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(rst, clk_1)
|
||||
variable reset_delay : unsigned (5 downto 0);
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if rst = '1' then
|
||||
reset_delay := (others => '1');
|
||||
cpu_rst <= '1';
|
||||
run_en <= '0';
|
||||
elsif reset_delay /= (5 downto 0 => '0') then
|
||||
reset_delay := reset_delay - 1;
|
||||
else
|
||||
cpu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(reset_delay'left-1) = '0' then
|
||||
run_en <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ID stage
|
||||
--------------------------------------------------------------------------
|
||||
@@ -625,7 +604,7 @@ proc_stage_DMEM_ADDR:
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
|
||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
|
||||
dmem_we <= EX_stage.ctrl.dmem_we;
|
||||
dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||
dmem_addr <= EX_stage.va;
|
||||
@@ -867,7 +846,9 @@ proc_stage_WB_p:
|
||||
if rising_edge(clk_1) then
|
||||
if rst = '1' then
|
||||
WB_stage.op <= NOP;
|
||||
WB_stage.wreg_we <= '0';
|
||||
WB_stage.wreg_we <= '1';
|
||||
WB_stage.reg_wptr <= (others => '0');
|
||||
WB_stage.data <= (others => '0');
|
||||
elsif sdu.WB_stall = '0' then
|
||||
WB_stage.op <= MEM_stage.op;
|
||||
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
||||
|
||||
@@ -51,16 +51,7 @@ architecture Behavioral of reg_dual is
|
||||
constant depth : integer := 2**addr_width;
|
||||
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
|
||||
function mem_clear(depth : natural) return mem_t is
|
||||
variable result : mem_t;
|
||||
begin
|
||||
for i in 0 to depth-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end mem_clear;
|
||||
|
||||
signal reg_mem : mem_t := mem_clear(depth);
|
||||
signal reg_mem : mem_t;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
@@ -61,7 +61,7 @@ architecture rtl of mips_top is
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int : in unsigned (5 downto 0);
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
@@ -92,6 +92,9 @@ architecture rtl of mips_top is
|
||||
signal dmem_din : word_t;
|
||||
signal dmem_be : unsigned(3 downto 0);
|
||||
|
||||
signal cpu_rst : STD_LOGIC;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
|
||||
COMPONENT biu
|
||||
GENERIC
|
||||
(
|
||||
@@ -134,12 +137,31 @@ begin
|
||||
debug(0) <= imem_err;
|
||||
debug(1) <= dmem_err;
|
||||
|
||||
process(CLK_I)
|
||||
variable reset_delay : unsigned (5 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
reset_delay := (others => '1');
|
||||
cpu_rst <= '1';
|
||||
cpu_run <= '0';
|
||||
elsif reset_delay /= (5 downto 0 => '0') then
|
||||
reset_delay := reset_delay - 1;
|
||||
else
|
||||
cpu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(reset_delay'left-1) = '0' then
|
||||
cpu_run <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_pipeline: pipeline
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
rst => cpu_rst,
|
||||
clk => CLK_I,
|
||||
halt => '0',
|
||||
ce => cpu_run,
|
||||
int => INT,
|
||||
imem_err => imem_err,
|
||||
imem_rdy => imem_rdy,
|
||||
@@ -164,7 +186,7 @@ inst_biu: biu
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => RST_I,
|
||||
RST_I => cpu_rst,
|
||||
CLK_I => CLK_I,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
|
||||
@@ -86,8 +86,10 @@ ARCHITECTURE behavior OF tb_mips_top IS
|
||||
|
||||
signal flash_cs_n : std_logic;
|
||||
signal flash_oe_n : std_logic;
|
||||
signal flash_be_n : unsigned(3 downto 0);
|
||||
signal sram_cs_n : std_logic;
|
||||
signal sram_wr_n : unsigned(3 downto 0);
|
||||
signal sram_be_n : unsigned(3 downto 0);
|
||||
signal sram_wr_n : std_logic;
|
||||
signal sram_oe_n : std_logic;
|
||||
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
||||
signal sram_d : unsigned(31 downto 0);
|
||||
@@ -254,7 +256,7 @@ inst_flash_port : entity work.async_port_wb
|
||||
(
|
||||
addr_width => FLASH_ADDR_WIDTH,
|
||||
data_width => 32,
|
||||
byte_sel_width => 1,
|
||||
byte_sel_width => 4,
|
||||
async_timespec => ts_flash
|
||||
)
|
||||
PORT MAP
|
||||
@@ -276,6 +278,7 @@ inst_flash_port : entity work.async_port_wb
|
||||
async_cs => flash_cs_n,
|
||||
async_wr => open,
|
||||
async_rd => flash_oe_n,
|
||||
async_be => flash_be_n,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
@@ -306,6 +309,7 @@ inst_sram_port : entity work.async_port_wb
|
||||
async_cs => sram_cs_n,
|
||||
async_wr => sram_wr_n,
|
||||
async_rd => sram_oe_n,
|
||||
async_be => sram_be_n,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
@@ -332,39 +336,46 @@ inst_uart : entity work.uart_wb
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRAM_READ:
|
||||
process(sram_a, sram_cs_n, sram_oe_n)
|
||||
process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
|
||||
begin
|
||||
sram_d <= (others => 'Z');
|
||||
sram_d <= (others => 'Z') after 10 ns;
|
||||
if sram_oe_n = '0' then
|
||||
if sram_cs_n = '0' then
|
||||
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
|
||||
if sram_be_n(0) = '0' then
|
||||
sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(1) = '0' then
|
||||
sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(2) = '0' then
|
||||
sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(3) = '0' then
|
||||
sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SRAM_WRITE:
|
||||
process(sram_a, sram_cs_n, sram_wr_n)
|
||||
process(sram_wr_n)
|
||||
begin
|
||||
if rising_edge(sram_wr_n(0)) then
|
||||
if rising_edge(sram_wr_n) then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(0) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(1)) then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(1) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(2)) then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(2) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(3)) then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(3) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
@@ -386,9 +397,22 @@ FLASH_READ:
|
||||
end loop;
|
||||
else
|
||||
flash_d <= (others => 'Z') after 10 ns;
|
||||
if flash_oe_n = '0' and flash_cs_n = '0' then
|
||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
||||
flash_d <= flash_data(index) after 10 ns;
|
||||
if flash_oe_n = '0' then
|
||||
if flash_cs_n = '0' then
|
||||
if flash_be_n(0) = '0' then
|
||||
flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after 10 ns;
|
||||
end if;
|
||||
if flash_be_n(1) = '0' then
|
||||
flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after 10 ns;
|
||||
end if;
|
||||
if flash_be_n(2) = '0' then
|
||||
flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after 10 ns;
|
||||
end if;
|
||||
if flash_be_n(3) = '0' then
|
||||
flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@@ -269,7 +269,8 @@ int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pE
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
char tpl[] =
|
||||
{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.4 2009-01-18 21:44:57 Jens Exp $
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.5 2009-02-08 17:34:18 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -32,8 +32,9 @@ entity async_port_wb is
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
end async_port_wb;
|
||||
@@ -209,7 +210,8 @@ architecture Behavioral of async_port_wb is
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
async_wr <= ((byte_sel_width-1 downto 0 => as.wr) and byte_en) xor (byte_sel_width-1 downto 0 => not async_timespec.pol_we);
|
||||
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and byte_en);
|
||||
async_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
|
||||
@@ -37,6 +37,7 @@ package async_types is
|
||||
pol_cs : std_logic;
|
||||
pol_oe : std_logic;
|
||||
pol_we : std_logic;
|
||||
pol_be : std_logic;
|
||||
pol_rst : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
@@ -18,12 +18,10 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
@@ -38,7 +36,6 @@ vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/ram_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
|
||||
|
||||
@@ -18,12 +18,10 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
@@ -38,7 +36,6 @@ vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
|
||||
|
||||
@@ -19,10 +19,10 @@ vcom -explicit -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
|
||||
|
||||
# CPU
|
||||
@@ -38,9 +38,7 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
|
||||
vcom -explicit -93 "../src/ram_sim.vhd"
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/ram_wb.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
|
||||
|
||||
# VGA
|
||||
|
||||
@@ -59,19 +59,10 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_data_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
|
||||
@@ -96,7 +87,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -divider {VGA Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
@@ -111,47 +101,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
|
||||
add wave -noupdate -divider BUI
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dcache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_rd
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_wr
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_icache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dcache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_rd
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_wr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/uncached_access
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_out
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_in
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
|
||||
add wave -noupdate -divider USB
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
@@ -239,7 +188,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ru
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
|
||||
@@ -254,20 +202,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
|
||||
add wave -noupdate -divider {CPU DMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -divider {CPU IMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
|
||||
add wave -noupdate -divider {User ROM}
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
@@ -292,56 +228,8 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cp
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
|
||||
add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
|
||||
add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
|
||||
add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
|
||||
add wave -noupdate -divider D-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_index_count
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/word_index_reg
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_word_index
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_hit_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
|
||||
configure wave -namecolwidth 187
|
||||
@@ -357,4 +245,4 @@ configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {37535226330 ps}
|
||||
WaveRestoreZoom {381220785 ps} {2601775328 ps}
|
||||
|
||||
+1175
-1175
File diff suppressed because it is too large
Load Diff
+1175
-1175
File diff suppressed because it is too large
Load Diff
@@ -32,7 +32,6 @@ use UNISIM.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
--use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.vga_types.all;
|
||||
@@ -160,24 +159,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT lcd_port
|
||||
PORT
|
||||
(
|
||||
@@ -218,8 +199,9 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
@@ -331,8 +313,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal flash_addr : unsigned(31 downto 0);
|
||||
signal ac97_rstn : std_logic;
|
||||
signal flash_rstn : std_logic;
|
||||
signal usb_wrn : unsigned(0 downto 0);
|
||||
signal flash_wrn : unsigned(0 downto 0);
|
||||
|
||||
-- Arbiter
|
||||
constant ARB_MAX_MASTER : natural := 2;
|
||||
@@ -394,11 +374,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal SDAT_I_sdram : unsigned(63 downto 0);
|
||||
signal SEL_I_sdram : unsigned(7 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal SDAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
@@ -441,7 +416,7 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
BEGIN
|
||||
@@ -461,8 +436,6 @@ BEGIN
|
||||
SEL_I_sdram <= "0000" & SEL_O;
|
||||
|
||||
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
|
||||
sys_usb_wrn <= usb_wrn(0);
|
||||
sys_flash_wrn <= flash_wrn(0);
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- Arbiter
|
||||
@@ -535,8 +508,7 @@ mem_mux:
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
@@ -551,7 +523,6 @@ signal_mux:
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_usb <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
CYC_I_sdram <= '0';
|
||||
CYC_I_vga <= '0';
|
||||
CYC_I_ac97 <= '0';
|
||||
@@ -573,9 +544,6 @@ signal_mux:
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when mem_sdram =>
|
||||
CYC_I_sdram <= CYC_O;
|
||||
|
||||
@@ -592,10 +560,9 @@ signal_mux:
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
|
||||
SDAT_O_ram when CYC_I_ram = '1' else
|
||||
SDAT_O_rom when CYC_I_rom = '1' else
|
||||
SDAT_O_flash when CYC_I_flash = '1' else
|
||||
SDAT_O_usb when CYC_I_usb = '1' else
|
||||
@@ -624,23 +591,6 @@ inst_mips_top: mips_top
|
||||
INT => INT
|
||||
);
|
||||
|
||||
inst_ram_wb : ram_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ram
|
||||
);
|
||||
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
@@ -717,8 +667,9 @@ inst_flash_port : async_port_wb
|
||||
async_a => sys_flash_a,
|
||||
async_d => sys_flash_d,
|
||||
async_cs => sys_flash_ce,
|
||||
async_wr => flash_wrn,
|
||||
async_wr => sys_flash_wrn,
|
||||
async_rd => sys_flash_rdn,
|
||||
async_be => open,
|
||||
async_rst => flash_rstn
|
||||
);
|
||||
|
||||
@@ -747,8 +698,9 @@ inst_usb_port : async_port_wb
|
||||
async_a => sys_usb_a,
|
||||
async_d => sys_usb_d,
|
||||
async_cs => sys_usb_csn,
|
||||
async_wr => usb_wrn,
|
||||
async_wr => sys_usb_wrn,
|
||||
async_rd => sys_usb_rdn,
|
||||
async_be => open,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
|
||||
@@ -170,24 +170,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT lcd_port
|
||||
PORT
|
||||
(
|
||||
@@ -228,8 +210,9 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
@@ -388,7 +371,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal flash_we_n : std_logic;
|
||||
signal flash_d_drv : std_logic;
|
||||
signal flash_bsy : std_logic;
|
||||
signal usb_wrn : unsigned(0 downto 0);
|
||||
|
||||
-- Arbiter
|
||||
constant ARB_MAX_MASTER : natural := 2;
|
||||
@@ -450,11 +432,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal SDAT_I_sdram : unsigned(63 downto 0);
|
||||
signal SEL_I_sdram : unsigned(7 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal SDAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
@@ -503,7 +480,7 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
BEGIN
|
||||
@@ -515,7 +492,6 @@ BEGIN
|
||||
rst_in <= not sys_rst_n_in;
|
||||
rst <= not locked;
|
||||
sys_usb_rstn <= not gpo1(0);
|
||||
sys_usb_wrn <= usb_wrn(0);
|
||||
sys_flash_byten <= '1';
|
||||
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
|
||||
ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0';
|
||||
@@ -624,9 +600,8 @@ mem_mux:
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
-- mem_area <= mem_ssram;
|
||||
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
-- kernel sram
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
@@ -641,7 +616,6 @@ signal_mux:
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_usb <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
CYC_I_sdram <= '0';
|
||||
CYC_I_vga <= '0';
|
||||
CYC_I_ssram <= '0';
|
||||
@@ -664,9 +638,6 @@ signal_mux:
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when mem_sdram =>
|
||||
CYC_I_sdram <= CYC_O;
|
||||
|
||||
@@ -686,11 +657,10 @@ signal_mux:
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
|
||||
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
|
||||
SDAT_O_ram when CYC_I_ram = '1' else
|
||||
SDAT_O_rom when CYC_I_rom = '1' else
|
||||
SDAT_O_flash when CYC_I_flash = '1' else
|
||||
SDAT_O_usb when CYC_I_usb = '1' else
|
||||
@@ -719,23 +689,6 @@ inst_mips_top: mips_top
|
||||
INT => INT
|
||||
);
|
||||
|
||||
inst_ram_wb : ram_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ram
|
||||
);
|
||||
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
@@ -844,8 +797,9 @@ inst_usb_port : async_port_wb
|
||||
async_a => sys_usb_a,
|
||||
async_d => sys_usb_d,
|
||||
async_cs => sys_usb_csn,
|
||||
async_wr => usb_wrn,
|
||||
async_wr => sys_usb_wrn,
|
||||
async_rd => sys_usb_rdn,
|
||||
async_be => open,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
|
||||
@@ -40,6 +40,7 @@ package async_defs is
|
||||
pol_cs => '1',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
@@ -54,6 +55,7 @@ package async_defs is
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user