This commit was manufactured by cvs2svn to create tag 'MIPS_R10b'.

git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R10b@342 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld

@@ -1,9 +1,10 @@
 MEMORY
 {
   rom          : ORIGIN = 0xBFC00000, LENGTH = 0x00002000  /*   8K    */
+  ram          : ORIGIN = 0x40000000, LENGTH = 0x00002000  /*   8K    */
 }
 
-stack_ptr = 0x7FFFFFF0;
+stack_ptr = 0x7FFFEFF0;
 baudrate = 0x0D;
 sys_led_port = 0xA0000000;
 sys_uart_data = 0xA0010000;
@@ -39,4 +40,9 @@ SECTIONS
      *(.rodata*)
    }  > rom
 
+   .data ORIGIN(ram) :
+   {
+     *(.*data) *(.*bss) *(.*common)
+   }  > ram
+
 }

lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S

@@ -20,10 +20,11 @@ _exc_handler:
 		# Set Error LED and ExcCode LEDs
 		# Get Cause
 		mfc0	$26, $13
-		la 		$27, sys_led_port
+		li 		$27, 0xC0000000
 		srl		$26, 2
 		andi	$26, 0x000F
 		or 		$26, $27
+		la 		$27, sys_led_port
 		sw 		$26, 0($27)
 
 		# wait for all interrupts = 0

lib/CPUs/MIPS/bsp/examples/init.S

@@ -9,9 +9,9 @@ _init:
 		.set	noreorder
 
 		# set uart
-		la	$8, sys_uart_baud
-		addiu	$9, $0, baudrate
-		sb	$9, 0($8)
+#		la	$8, sys_uart_baud
+#		addiu	$9, $0, baudrate
+#		sb	$9, 0($8)
 		
 		# set stack pointer 
 		la $sp, stack_ptr

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -159,7 +159,6 @@ END COMPONENT;
 	signal  tram_dout			: tram_data_t;
 	signal  tram_addr_wr		: unsigned(cache_index_width-1 downto 0);
 	signal  tram_din			: tram_data_t;
-	signal	tram_re				: std_logic;
 	signal	tram_we				: std_logic;
 	
 	signal	fill_count			: natural range 0 to 2**word_index_width-1;
@@ -255,7 +254,7 @@ inst_tag_ram : dpram_1w1r
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
-		en_b	=> tram_re,
+		en_b	=> '1',
 		we_a	=> tram_we,
 		addr_a	=> tram_addr_wr,
 		addr_b	=> tram_addr_rd,
@@ -327,7 +326,6 @@ cache_state:
 		request_count_rst		<= '0';
 		CYC_O					<= '0';
 		STB_O					<= '0';
-		tram_re					<= '0';
 		was_miss				<= '0';
 		cache_fill				<= '0';
 		tram_addr_wr			<= to_unsigned(flush_index_count, cache_index_width);
@@ -342,7 +340,6 @@ cache_state:
 		when ready =>
 			cache_busy 		<= '0';
 			cpu_reg_en		<= '1';
-			tram_re			<= cpu_en;
 			if cpu_en2 = '1' then
 				if cache_hit = '0' and cpu_we_reg = '0' then
 					sn						<= mem_request;
@@ -361,7 +358,6 @@ cache_state:
 				sn	<= ready;
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
-					tram_re				<= '1';
 				end if;
 			end if;
 		when mem_request =>
@@ -395,7 +391,6 @@ cache_state:
 			cache_entry_in.valid	<= '1';
 			sn						<= rd_cache;
 		when rd_cache =>
-			tram_re					<= '1';
 			was_miss				<= '1';
 			sn	<= ready;
 

lib/CPUs/MIPS/src/core/icache.vhd

@@ -124,7 +124,6 @@ END COMPONENT;
 	signal  tag_ram_data_rd		: tag_ram_data_t;
 	signal  tag_ram_addr_wr		: unsigned(cache_index_width-1 downto 0);
 	signal  tag_ram_data_wr		: tag_ram_data_t;
-	signal	tag_ram_re			: std_logic;
 	signal	tag_ram_we			: std_logic;
 	
 	signal	ram_index_count			: natural range 0 to 2**word_index_width-1;
@@ -165,7 +164,7 @@ inst_tag_ram : dpram_1w1r
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
-		en_b	=> tag_ram_re,
+		en_b	=> '1',
 		we_a	=> tag_ram_we,
 		addr_a	=> tag_ram_addr_wr,
 		addr_b	=> tag_ram_addr_rd,
@@ -230,7 +229,6 @@ cache_state:
 		CYC_O					<= '0';
 		STB_O					<= '0';
 		data_ram_re				<= '0';
-		tag_ram_re				<= '0';
 		was_miss				<= '0';
 		data_write				<= '0';
 		tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
@@ -253,7 +251,6 @@ cache_state:
 				elsif cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
-					tag_ram_re			<= '1';
 				end if;	
 			end if;	
 		when flush =>
@@ -267,7 +264,6 @@ cache_state:
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
-					tag_ram_re			<= '1';
 				end if;
 			end if;
 		when mem_request =>
@@ -302,7 +298,6 @@ cache_state:
 			sn						<= rd_cache;
 			
 		when rd_cache =>
-			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';
 			sn	<= ready;

lib/CPUs/MIPS/src/core/mips_pipeline.vhd

@@ -33,7 +33,7 @@ entity pipeline is
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		halt		: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
 		int			: in  unsigned(5 downto 0);
 		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
@@ -174,13 +174,11 @@ architecture Behavioral of pipeline is
 	signal clk_2, clk_1		: STD_LOGIC;
 	signal hdu				: hdu_t;
 	signal sdu				: sdu_t;
-	signal cpu_rst			: STD_LOGIC;
 	signal reg_a			: word_t;
 	signal reg_b			: word_t;
 	signal ctrl_lines		: ctrl_lines_t;
-	signal cpu_run			: STD_LOGIC;
 	signal branch_ce		: STD_LOGIC;
-	signal run_en			: STD_LOGIC;
+	signal cpu_run			: STD_LOGIC;
 	signal mul_dep			: STD_LOGIC;
 	signal imem_dep			: STD_LOGIC;
 	signal dmem_dep			: STD_LOGIC;
@@ -213,7 +211,7 @@ begin
 	
 	clk_1					<= clk;
 	clk_2					<= not clk;
-	cpu_run					<= run_en;
+	cpu_run					<= ce;
 	
 	-- Stall Detection Unit ---------------------------------------------------
 	sdu.ID_nop				<= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
@@ -238,7 +236,7 @@ begin
 inst_muldiv: muldiv
 	PORT MAP
 	(
-		rst			=> cpu_rst,
+		rst			=> rst,
 		clk			=> clk,
 		hilo_we		=> EX_stage.ctrl.mul_hilo_we,
 		din_hi		=> EX_stage.reg_a,
@@ -257,7 +255,7 @@ inst_muldiv: muldiv
 inst_cop: cop
 	PORT MAP
 	(
-		rst			=> cpu_rst,
+		rst			=> rst,
 		clk			=> clk,
 		sdu			=> sdu,
 		events		=> MEM_stage.events,
@@ -362,25 +360,6 @@ proc_stage_branch:
 		end if;	
 	end process;
 
-	process(rst, clk_1)
-	variable reset_delay : unsigned (5 downto 0);
-	begin
-		if rising_edge(clk_1) then
-			if rst = '1' then
-				reset_delay := (others => '1');
-				cpu_rst <= '1';
-				run_en	<= '0';
-			elsif reset_delay /= (5 downto 0 => '0') then
-				reset_delay := reset_delay - 1;
-			else
-				cpu_rst <= '0';
-			end if;	
-			if reset_delay(reset_delay'left-1) = '0' then
-				run_en	<= '1';
-			end if;	
-		end if;
-	end process;
-
 --------------------------------------------------------------------------
 -- ID stage
 --------------------------------------------------------------------------

lib/CPUs/MIPS/src/core/mips_top.vhd

@@ -61,7 +61,7 @@ architecture rtl of mips_top is
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		halt		: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
 		int			: in  unsigned (5 downto 0);
 		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
@@ -92,6 +92,9 @@ architecture rtl of mips_top is
 	signal dmem_din			: word_t;
 	signal dmem_be			: unsigned(3 downto 0);
 
+	signal cpu_rst			: STD_LOGIC;
+	signal cpu_run			: STD_LOGIC;
+
 	COMPONENT biu
 	GENERIC
 	(
@@ -134,12 +137,31 @@ begin
 	debug(0)		<= imem_err;
 	debug(1)		<= dmem_err;
 	
+	process(CLK_I)
+	variable reset_delay : unsigned (5 downto 0);
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				reset_delay := (others => '1');
+				cpu_rst <= '1';
+				cpu_run	<= '0';
+			elsif reset_delay /= (5 downto 0 => '0') then
+				reset_delay := reset_delay - 1;
+			else
+				cpu_rst <= '0';
+			end if;	
+			if reset_delay(reset_delay'left-1) = '0' then
+				cpu_run	<= '1';
+			end if;	
+		end if;
+	end process;
+
 inst_pipeline: pipeline
 	PORT MAP
 	(
-		rst			=> RST_I,
+		rst			=> cpu_rst,
 		clk			=> CLK_I,
-		halt		=> '0',
+		ce			=> cpu_run,
 		int			=> INT,
 		imem_err	=> imem_err,
 		imem_rdy	=> imem_rdy,
@@ -164,7 +186,7 @@ inst_biu: biu
 	)
 	PORT MAP
 	(
-		RST_I			=> RST_I,
+		RST_I			=> cpu_rst,
 		CLK_I			=> CLK_I,
 		ACK_I			=> ACK_I,
 		SRDY_I			=> SRDY_I,