Bus-out FIFO improved timing so much and leads to 300 less Slice - FIFOs are great!
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/
git-svn-id: http://moon:8086/svn/vhdl/trunk@666 cc03376c-175c-47c8-b038-4cd826a8556b
- fb_front is writable by host only if msten = '0'. fb_back is writable by host every time.
- fb_front and fb_back are changed after complete frame. Controller can issue buffer-change Interrupt
- packed resx, resy and fps into one 32-bit register
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/
git-svn-id: http://moon:8086/svn/vhdl/trunk@650 cc03376c-175c-47c8-b038-4cd826a8556b
- added INT_O on buffer change
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/
git-svn-id: http://moon:8086/svn/vhdl/trunk@641 cc03376c-175c-47c8-b038-4cd826a8556b
- added new regsiter features: status/ctrl register cursor position, screen resolution
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/
git-svn-id: http://moon:8086/svn/vhdl/trunk@604 cc03376c-175c-47c8-b038-4cd826a8556b
- control signals derived from register file are noe registered for better timing
- mem_offset updated from vga_mem_offset wehn new frame begins
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/
git-svn-id: http://moon:8086/svn/vhdl/trunk@459 cc03376c-175c-47c8-b038-4cd826a8556b
jens