jens
51f9d7849f
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@673 cc03376c-175c-47c8-b038-4cd826a8556b
896 lines
23 KiB
VHDL
896 lines
23 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:25:45 10/15/05
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-- Design Name:
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-- Module Name: vga_backend - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.utils_pkg.all;
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use work.vga_types.all;
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entity vga_frontend64 is
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Generic
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(
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fifo_depth : integer := 2048;
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fifo_almost_full_thresh : natural := 2000;
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fifo_almost_empty_thresh : natural := 48;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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Port
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(
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-- System signals
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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-- JBUS Master signals
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(7 downto 0);
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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ADDR_O : out unsigned(31 downto 0);
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MDAT_I : in unsigned(63 downto 0);
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MDAT_O : out unsigned(63 downto 0);
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-- JBUS Slave signals
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INT_O : out STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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SDAT_I : in unsigned(31 downto 0);
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SDAT_O : out unsigned(31 downto 0);
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-- VGA signals
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vga_clk_in : in std_logic;
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vga_clk_ce : in std_logic;
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vga_red : out unsigned(7 downto 0);
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vga_green : out unsigned(7 downto 0);
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vga_blue : out unsigned(7 downto 0);
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vga_blank_n : out std_logic;
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vga_sync_n : out std_logic;
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vga_hsync : out std_logic;
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vga_vsync : out std_logic
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);
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end vga_frontend64;
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architecture Behavioral of vga_frontend64 is
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-- Color FIFO signals
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_almost_empty : std_logic;
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signal fifo_almost_full : std_logic;
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signal fifo_color_re : std_logic;
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signal fifo_color_we : std_logic;
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signal fifo_color_out : unsigned(63 downto 0);
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signal fifo_color_in : unsigned(63 downto 0);
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-- Backend signals
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signal scan_rdy : std_logic;
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signal ctrl_scan_en : std_logic;
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signal color_in : color_array_t;
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signal color_op : color_op_t;
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signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
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signal stat_vga_rdy : std_logic;
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signal stat_hready : std_logic;
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signal stat_vready : std_logic;
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signal stat_scan : std_logic;
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signal stat_hscan : std_logic;
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signal stat_vscan : std_logic;
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signal stat_hsync : std_logic;
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signal stat_vsync : std_logic;
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signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
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signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
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-- CG signals
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signal cg_en : std_logic;
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signal cg_rdy : std_logic;
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signal cg_draw : std_logic;
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signal cg_clr_screen : std_logic;
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signal cg_clr_line : std_logic;
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signal cg_din : unsigned(7 downto 0);
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signal cg_dout : unsigned(7 downto 0);
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signal cg_ascii_we : std_logic;
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signal cg_posy_we : std_logic;
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signal cg_posx_we : std_logic;
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signal cg_color : color_t;
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signal cg_csr_pos_x : natural range 0 to 80-1;
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signal cg_csr_pos_y : natural range 0 to 32-1;
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-- Bus master signals
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constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
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signal bufchg : std_logic;
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signal bufchg_irq_en : std_logic;
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signal bufchg_flag : std_logic;
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signal bufchg_flag_ack : std_logic;
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signal vga_fb_back : unsigned(31 downto 0);
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signal vga_fb_front : unsigned(31 downto 0);
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signal host_fb_front : unsigned(31 downto 0);
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signal host_fb_back : unsigned(31 downto 0);
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signal blit_addr_src_0 : unsigned(31 downto 0);
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signal blit_addr_src_1 : unsigned(31 downto 0);
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signal blit_addr_dst : unsigned(31 downto 0);
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signal blit_dimx_src_0 : unsigned(31 downto 0);
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signal blit_dimx_src_1 : unsigned(31 downto 0);
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signal blit_dimx_dst : unsigned(31 downto 0);
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signal host_blit_nx : unsigned(31 downto 0);
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signal blit_nx : unsigned(31 downto 0);
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signal blit_ny : unsigned(31 downto 0);
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signal blit_func_sel : unsigned(3 downto 0);
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signal blit_comb_sel : unsigned(3 downto 0);
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signal blit_request : std_logic;
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signal blit_request_set : std_logic;
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signal blit_request_clr : std_logic;
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signal blit_complete : std_logic;
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signal blit_complete_ack : std_logic;
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signal blit_complete_inten : std_logic;
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signal vga_scan_rdy : std_logic;
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signal vga_master_en : std_logic;
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signal request_cnt_rst : std_logic;
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signal request_en : std_logic;
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signal pixel_cnt_rst : std_logic;
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signal read_bus_en : std_logic;
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signal request_cnt : unsigned(28 downto 0);
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signal read_cnt : unsigned(28 downto 0);
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signal bus_read_fin : std_logic;
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signal CYC_O_scan : std_logic;
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signal STB_O_scan : std_logic;
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signal ADDR_O_scan : unsigned(31 downto 0);
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signal pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1;
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signal front : unsigned(31 downto 0);
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signal back : unsigned(31 downto 0);
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-- Blitter vars
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constant BLIT_CHUNK_SIZE : natural := 32;
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signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
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-- Blitter FIFO signals
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signal blitfifo_full : std_logic;
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signal blitfifo_empty : std_logic;
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signal blitfifo_almost_empty : std_logic;
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signal blitfifo_almost_full : std_logic;
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signal blitfifo_color_re : std_logic;
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signal blitfifo_color_we : std_logic;
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signal blitfifo_color_out : unsigned(63 downto 0);
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signal blitfifo_color_in : unsigned(63 downto 0);
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signal blit_reset : std_logic;
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signal blit_src_cnt_x : unsigned(31 downto 0);
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signal blit_src_cnt_y : unsigned(31 downto 0);
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signal blit_src_off_y : unsigned(31 downto 0);
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signal blit_src_offset : unsigned(31 downto 0);
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signal blit_src_finish : std_logic;
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signal CYC_O_blit_src : std_logic;
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signal STB_O_blit_src : std_logic;
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signal ADDR_O_blit_src : unsigned(31 downto 0);
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signal blit_dst_cnt_x : unsigned(31 downto 0);
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signal blit_dst_cnt_y : unsigned(31 downto 0);
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signal blit_dst_off_y : unsigned(31 downto 0);
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signal blit_dst_offset : unsigned(31 downto 0);
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signal blit_dst_finish : std_logic;
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signal CYC_O_blit_dst : std_logic;
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signal STB_O_blit_dst : std_logic;
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signal ADDR_O_blit_dst : unsigned(31 downto 0);
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signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
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-- Bus FIFO
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signal bus_fifo_din : unsigned(104 downto 0);
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signal bus_fifo_dout : unsigned(104 downto 0);
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signal bus_fifo_re : std_logic;
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signal bus_fifo_we : std_logic;
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signal bus_fifo_full : std_logic;
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signal bus_fifo_empty : std_logic;
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signal bus_rdy : std_logic;
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alias bus_fifo_addr_in is bus_fifo_din(31 downto 0);
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alias bus_fifo_data_in is bus_fifo_din(95 downto 32);
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alias bus_fifo_sel_in is bus_fifo_din(103 downto 96);
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alias bus_fifo_we_in is bus_fifo_din(104);
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alias bus_fifo_addr_out is bus_fifo_dout(31 downto 0);
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alias bus_fifo_data_out is bus_fifo_dout(95 downto 32);
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alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
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alias bus_fifo_we_out is bus_fifo_dout(104);
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type vm_state_t is (init, idle, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, blit_dst_bus_fin);
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signal s, sn : vm_state_t;
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begin
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proc_bufchg_irq:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if pixel_cnt_rst = '1' or bufchg_flag_ack = '1' then
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bufchg_flag <= '0';
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elsif bufchg = '1' then
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bufchg_flag <= '1';
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end if;
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INT_O <= bufchg_flag and bufchg_irq_en;
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end if;
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end process;
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proc_blit_request_flags:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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blit_reset <= '0';
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if pixel_cnt_rst = '1' then
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blit_request <= '0';
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blit_reset <= '1';
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elsif blit_request = '0' then
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if blit_request_set = '1' then
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blit_request <= '1';
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blit_reset <= '1';
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end if;
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elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
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blit_request <= '0';
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end if;
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end if;
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end process;
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proc_blit_complete_flag:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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blit_complete <= '0';
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elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
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blit_complete <= '1';
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elsif blit_complete_ack = '1' then
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blit_complete <= '0';
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end if;
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end if;
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end process;
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inst_vga_backend : entity work.vga_backend
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GENERIC MAP
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(
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tsvga => tsvga
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)
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PORT MAP
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(
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-- System signals
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sys_rst => RST_I,
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sys_clk => CLK_I,
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-- Color channels
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color_in => color_in,
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color_op => color_op,
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color_en => color_en,
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-- Control signals
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ctrl_scan_en => ctrl_scan_en,
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-- Status signals
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stat_vga_rdy => stat_vga_rdy,
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stat_scan => stat_scan,
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stat_hsync => stat_hsync,
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stat_vsync => stat_vsync,
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stat_hready => stat_hready,
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stat_vready => stat_vready,
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stat_hscan => stat_hscan,
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stat_vscan => stat_vscan,
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stat_hpos => stat_hpos,
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stat_vpos => stat_vpos,
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-- VGA domain signals
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vga_clk_in => vga_clk_in,
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vga_clk_ce => vga_clk_ce,
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vga_red => vga_red,
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vga_green => vga_green,
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vga_blue => vga_blue,
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vga_blank_n => vga_blank_n,
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vga_sync_n => vga_sync_n,
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vga_hsync => vga_hsync,
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vga_vsync => vga_vsync
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);
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SRDY_O <= CYC_I; -- and cg_rdy;
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MRDY_O <= not fifo_full;
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STB_O <= not bus_fifo_empty;
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ADDR_O <= bus_fifo_addr_out;
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MDAT_O <= bus_fifo_data_out;
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SEL_O <= bus_fifo_sel_out;
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WE_O <= bus_fifo_we_out;
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odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
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ctrl_scan_en <= '1';
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color_en(0) <= not fifo_empty;
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color_en(1) <= cg_draw;
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color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
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color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque
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color_op <= op_over;
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vga_scan_rdy <= stat_hready and stat_vready;
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inst_linefifo: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(fifo_depth),
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data_width => 64,
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almost_full_thresh => fifo_almost_full_thresh,
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almost_empty_thresh => fifo_almost_empty_thresh
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)
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PORT MAP
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(
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rst => RST_I,
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clk_w => CLK_I,
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clk_r => vga_clk_in,
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we => fifo_color_we,
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re => fifo_color_re,
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data_w => fifo_color_in,
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data_r => fifo_color_out,
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fifo_full => fifo_full,
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fifo_empty => fifo_empty,
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fifo_afull => fifo_almost_full,
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fifo_aempty => fifo_almost_empty
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);
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fifo_color_in <= MDAT_I;
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fifo_color_re <= stat_scan and odd_pixel(0);
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fifo_color_we <= ACK_I and read_bus_en and CYC_O_scan; -- TODO:
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inst_blitfifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(32),
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data_width => 64,
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almost_full_thresh => 24,
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almost_empty_thresh => 8
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)
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PORT MAP
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(
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rst => RST_I,
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clk => CLK_I,
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we => blitfifo_color_we,
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re => blitfifo_color_re,
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data_w => blitfifo_color_in,
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data_r => blitfifo_color_out,
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fifo_full => blitfifo_full,
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fifo_empty => blitfifo_empty,
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fifo_afull => blitfifo_almost_full,
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fifo_aempty => blitfifo_almost_empty
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);
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blitfifo_color_in <= MDAT_I;
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blitfifo_color_re <= CYC_O_blit_dst and bus_rdy;
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blitfifo_color_we <= ACK_I and read_bus_en and CYC_O_blit_src; -- TODO:
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-- Instantiate synchronous FIFO
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inst_bus_fifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => 2,
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data_width => 105
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)
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PORT MAP
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(
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rst => RST_I,
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clk => CLK_I,
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we => bus_fifo_we,
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re => bus_fifo_re,
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fifo_full => bus_fifo_full,
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fifo_empty => bus_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_w => bus_fifo_din,
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data_r => bus_fifo_dout
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);
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bus_rdy <= not bus_fifo_full;
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bus_fifo_re <= not bus_fifo_empty and SRDY_I;
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bus_fifo_we <= request_en;
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bus_fifo_data_in <= blitfifo_color_out;
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bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
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ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
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ADDR_O_scan;
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bus_fifo_sel_in <= (others => '1');
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bus_fifo_we_in <= CYC_O_blit_dst;
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ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
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CYC_O <= CYC_O_scan or CYC_O_blit_src or CYC_O_blit_dst;
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vga_master_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= init;
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else
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s <= sn;
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end if;
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end if;
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end process;
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vga_master:
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process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_empty, blit_chunk_cnt)
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begin
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CYC_O_scan <= '0';
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STB_O_scan <= '0';
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CYC_O_blit_src <= '0';
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STB_O_blit_src <= '0';
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CYC_O_blit_dst <= '0';
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STB_O_blit_dst <= '0';
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pixel_cnt_rst <= '0';
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request_cnt_rst <= '0';
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request_en <= '0';
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read_bus_en <= '0';
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sn <= s;
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case s is
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when init =>
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if stat_vga_rdy = '1' then
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sn <= idle;
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end if;
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when idle =>
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pixel_cnt_rst <= '1';
|
|
if vga_master_en = '1' and vga_scan_rdy = '1' then
|
|
sn <= rdy;
|
|
end if;
|
|
|
|
when rdy =>
|
|
request_cnt_rst <= '1';
|
|
if fifo_almost_empty = '1' then
|
|
sn <= scan_bus_request;
|
|
elsif blit_request = '1' then
|
|
if blitfifo_empty = '1' then
|
|
sn <= blit_src_bus_request;
|
|
else
|
|
sn <= blit_dst_bus_request;
|
|
end if;
|
|
end if;
|
|
|
|
when scan_bus_request =>
|
|
CYC_O_scan <= '1';
|
|
STB_O_scan <= '1';
|
|
request_en <= '1';
|
|
read_bus_en <= '1';
|
|
if fifo_almost_full = '1' then
|
|
sn <= scan_bus_read;
|
|
end if;
|
|
|
|
when scan_bus_read =>
|
|
CYC_O_scan <= '1';
|
|
read_bus_en <= '1';
|
|
if bus_read_fin = '1' then
|
|
sn <= rdy;
|
|
if vga_master_en = '0' then
|
|
sn <= idle;
|
|
end if;
|
|
end if;
|
|
|
|
when blit_src_bus_request =>
|
|
CYC_O_blit_src <= '1';
|
|
STB_O_blit_src <= '1';
|
|
request_en <= '1';
|
|
read_bus_en <= '1';
|
|
if blit_chunk_cnt = 0 then
|
|
sn <= blit_src_bus_read;
|
|
end if;
|
|
|
|
when blit_src_bus_read =>
|
|
CYC_O_blit_src <= '1';
|
|
read_bus_en <= '1';
|
|
if bus_read_fin = '1' then
|
|
sn <= rdy;
|
|
end if;
|
|
|
|
when blit_dst_bus_request =>
|
|
CYC_O_blit_dst <= '1';
|
|
STB_O_blit_dst <= '1';
|
|
request_en <= '1';
|
|
if blit_chunk_cnt = 0 then
|
|
sn <= blit_dst_bus_fin;
|
|
end if;
|
|
|
|
when blit_dst_bus_fin =>
|
|
CYC_O_blit_dst <= '1';
|
|
if bus_fifo_empty = '1' then
|
|
sn <= rdy;
|
|
end if;
|
|
|
|
when others =>
|
|
sn <= idle;
|
|
|
|
end case;
|
|
end process;
|
|
|
|
proc_bus_request_counter:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
if request_cnt_rst = '1' then
|
|
request_cnt <= (others => '0');
|
|
elsif request_en = '1' and bus_rdy = '1' then
|
|
request_cnt <= request_cnt + 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
proc_bus_read_counter:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
if request_cnt_rst = '1' then
|
|
read_cnt <= (others => '0');
|
|
elsif read_bus_en = '1' and ACK_I = '1' then
|
|
read_cnt <= read_cnt + 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
proc_bus_read_finish:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
bus_read_fin <= '0';
|
|
if read_cnt = request_cnt then
|
|
bus_read_fin <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
proc_scan_addr:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
bufchg <= '0';
|
|
if pixel_cnt_rst = '1' then
|
|
pixel_cnt <= 0;
|
|
front <= host_fb_front;
|
|
elsif STB_O_scan = '1' and bus_rdy = '1' then
|
|
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
|
|
pixel_cnt <= pixel_cnt + 1;
|
|
else
|
|
pixel_cnt <= 0;
|
|
front <= host_fb_back;
|
|
bufchg <= '1';
|
|
end if;
|
|
end if;
|
|
vga_fb_front <= front;
|
|
vga_fb_back <= back;
|
|
end if;
|
|
end process;
|
|
|
|
ADDR_O_blit_src <= blit_addr_src_0 + blit_src_offset;
|
|
|
|
proc_blit_chunk_counter:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
if request_en = '0' then
|
|
blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
|
|
elsif blit_chunk_cnt /= 0 and bus_rdy = '1' and (STB_O_blit_src = '1' or STB_O_blit_dst = '1') then
|
|
blit_chunk_cnt <= blit_chunk_cnt - 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
proc_blit_addr_src:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
if blit_reset = '1' then
|
|
blit_src_cnt_x <= (others => '0');
|
|
blit_src_cnt_y <= (others => '0');
|
|
blit_src_offset <= (others => '0');
|
|
blit_src_off_y <= blit_dimx_src_0;
|
|
blit_src_finish <= '0';
|
|
elsif STB_O_blit_src = '1' and bus_rdy = '1' then
|
|
if blit_src_cnt_x /= blit_nx then
|
|
blit_src_cnt_x <= blit_src_cnt_x + 1;
|
|
blit_src_offset <= blit_src_offset + 8;
|
|
else
|
|
if blit_src_cnt_y /= blit_ny then
|
|
blit_src_cnt_x <= (others => '0');
|
|
blit_src_offset <= blit_src_off_y;
|
|
blit_src_cnt_y <= blit_src_cnt_y + 1;
|
|
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
|
|
else
|
|
blit_src_finish <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
ADDR_O_blit_dst <= blit_addr_dst + blit_dst_offset;
|
|
|
|
proc_blit_addr_dst:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
if blit_reset = '1' then
|
|
blit_dst_cnt_x <= (others => '0');
|
|
blit_dst_cnt_y <= (others => '0');
|
|
blit_dst_offset <= (others => '0');
|
|
blit_dst_off_y <= blit_dimx_dst;
|
|
blit_dst_finish <= '0';
|
|
elsif STB_O_blit_dst = '1' and bus_rdy = '1' then
|
|
if blit_dst_cnt_x /= blit_nx then
|
|
blit_dst_cnt_x <= blit_dst_cnt_x + 1;
|
|
blit_dst_offset <= blit_dst_offset + 8;
|
|
else
|
|
if blit_dst_cnt_y /= blit_ny then
|
|
blit_dst_cnt_x <= (others => '0');
|
|
blit_dst_offset <= blit_dst_off_y;
|
|
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
|
|
blit_dst_off_y <= blit_dst_off_y + blit_dimx_dst;
|
|
else
|
|
blit_dst_finish <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
inst_char_gen : entity work.char_gen
|
|
GENERIC MAP
|
|
(
|
|
tsvga => tsvga,
|
|
CHARACTER_SCALE => 1,
|
|
CHAR_ROM_SIZE_X => 8, -- Pixels
|
|
CHAR_ROM_SIZE_Y => 16, -- Pixels
|
|
CHAR_ROM_DEPTH => 256, -- Chars
|
|
MAX_CHAR_PER_LINE => 80, -- Chars
|
|
MAX_LINE_PER_FRAME => 32, -- Chars
|
|
CHAR_SPACING_X => 0, -- Pixels
|
|
CHAR_SPACING_Y => 0, -- Pixels
|
|
SCREEN_OFFSET_X => 16, -- Pixels
|
|
SCREEN_OFFSET_Y => 16 -- Pixels
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => RST_I,
|
|
sys_clk => CLK_I,
|
|
vga_clk => vga_clk_in,
|
|
ce => cg_en,
|
|
frame_pulse => scan_rdy,
|
|
clr_screen => cg_clr_screen,
|
|
clr_line => cg_clr_line,
|
|
din => cg_din,
|
|
dout => cg_dout,
|
|
ascii_we => cg_ascii_we,
|
|
posy_we => cg_posy_we,
|
|
posx_we => cg_posx_we,
|
|
ready => cg_rdy,
|
|
scan_pos_x_in => stat_hpos,
|
|
scan_pos_y_in => stat_vpos,
|
|
csr_pos_x_out => cg_csr_pos_x,
|
|
csr_pos_y_out => cg_csr_pos_y,
|
|
char_draw_en => cg_draw
|
|
);
|
|
scan_rdy <= stat_hready and stat_vready;
|
|
cg_en <= stat_scan;
|
|
|
|
|
|
registers_read:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
ACK_O <= '0';
|
|
if (STB_I and CYC_I) = '1' then
|
|
ACK_O <= not WE_I;
|
|
SDAT_O <= (others => '0');
|
|
case ADDR_I(5 downto 2) is
|
|
|
|
-- sys_vga_ctrl 0
|
|
when "0000" =>
|
|
SDAT_O(0) <= cg_rdy;
|
|
SDAT_O(1) <= vga_master_en;
|
|
SDAT_O(2) <= bufchg_irq_en;
|
|
SDAT_O(3) <= bufchg_flag;
|
|
SDAT_O(8) <= blit_request;
|
|
SDAT_O(9) <= blit_complete;
|
|
SDAT_O(10) <= blit_complete_inten;
|
|
SDAT_O(23 downto 20) <= blit_comb_sel;
|
|
SDAT_O(19 downto 16) <= blit_func_sel;
|
|
|
|
-- sys_vga_ascii 4
|
|
when "0001" =>
|
|
SDAT_O(7 downto 0) <= cg_dout;
|
|
|
|
-- sys_vga_posx 8
|
|
when "0010" =>
|
|
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_x, 8);
|
|
|
|
-- sys_vga_posy 12
|
|
when "0011" =>
|
|
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_y, 8);
|
|
|
|
-- sys_vga_cgcol 16
|
|
when "0100" =>
|
|
SDAT_O <= to_unsigned(cg_color);
|
|
|
|
-- sys_vga_res 20
|
|
when "0101" =>
|
|
SDAT_O <= to_unsigned(tsvga.nfps, 8) & to_unsigned(tsvga.ts_v.ncyc_scan, 12) & to_unsigned(tsvga.ts_h.ncyc_scan, 12);
|
|
|
|
-- sys_vga_fb_front 24
|
|
when "0110" =>
|
|
SDAT_O <= vga_fb_front;
|
|
|
|
-- sys_vga_fb_back 28
|
|
when "0111" =>
|
|
SDAT_O <= vga_fb_back;
|
|
|
|
-- sys_blit_addr_src_0 32
|
|
when "1000" =>
|
|
SDAT_O <= blit_addr_src_0;
|
|
|
|
-- sys_blit_addr_src_1 36
|
|
when "1001" =>
|
|
SDAT_O <= blit_addr_src_1;
|
|
|
|
-- sys_blit_addr_dst 40
|
|
when "1010" =>
|
|
SDAT_O <= blit_addr_dst;
|
|
|
|
-- sys_blit_dimx_src_0 44
|
|
when "1011" =>
|
|
SDAT_O <= blit_dimx_src_0;
|
|
|
|
-- sys_blit_dimx_src_1 48
|
|
when "1100" =>
|
|
SDAT_O <= blit_dimx_src_1;
|
|
|
|
-- sys_blit_dimx_dst 52
|
|
when "1101" =>
|
|
SDAT_O <= blit_dimx_dst;
|
|
|
|
-- sys_blit_nx 56
|
|
when "1110" =>
|
|
SDAT_O <= host_blit_nx;
|
|
|
|
-- sys_blit_ny 60
|
|
when "1111" =>
|
|
SDAT_O <= blit_ny;
|
|
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
registers_write:
|
|
process(CLK_I)
|
|
begin
|
|
if rising_edge(CLK_I) then
|
|
cg_ascii_we <= '0';
|
|
cg_posy_we <= '0';
|
|
cg_posx_we <= '0';
|
|
cg_clr_screen <= '0';
|
|
cg_clr_line <= '0';
|
|
bufchg_flag_ack <= '0';
|
|
blit_request_set <= '0';
|
|
blit_complete_ack <= '0';
|
|
if RST_I = '1' then
|
|
cg_din <= (others => '0');
|
|
vga_master_en <= '0';
|
|
bufchg_irq_en <= '0';
|
|
blit_complete_inten <= '0';
|
|
blit_func_sel <= (others => '0');
|
|
blit_comb_sel <= (others => '0');
|
|
host_fb_front <= X"40000000";
|
|
host_fb_back <= X"40010000";
|
|
cg_color <= (X"FF", X"FF", X"FF", X"FF");
|
|
elsif (STB_I and CYC_I and WE_I) = '1' then
|
|
case ADDR_I(5 downto 2) is
|
|
|
|
-- sys_vga_ctrl 0
|
|
when "0000" =>
|
|
vga_master_en <= SDAT_I(1);
|
|
bufchg_irq_en <= SDAT_I(2);
|
|
bufchg_flag_ack <= SDAT_I(3);
|
|
cg_clr_screen <= SDAT_I(4);
|
|
cg_clr_line <= SDAT_I(5);
|
|
blit_request_set <= SDAT_I(8);
|
|
blit_complete_ack <= SDAT_I(9);
|
|
blit_complete_inten <= SDAT_I(10);
|
|
blit_func_sel <= SDAT_I(19 downto 16);
|
|
blit_comb_sel <= SDAT_I(23 downto 20);
|
|
|
|
-- sys_vga_ascii 4
|
|
when "0001" =>
|
|
cg_ascii_we <= '1';
|
|
cg_din <= SDAT_I(7 downto 0);
|
|
|
|
-- sys_vga_posx 8
|
|
when "0010" =>
|
|
cg_posx_we <= '1';
|
|
cg_din <= SDAT_I(7 downto 0);
|
|
|
|
-- sys_vga_posy 12
|
|
when "0011" =>
|
|
cg_posy_we <= '1';
|
|
cg_din <= SDAT_I(7 downto 0);
|
|
|
|
-- sys_vga_cgcol 16
|
|
when "0100" =>
|
|
cg_color <= to_color_t(SDAT_I(31 downto 0));
|
|
|
|
-- sys_vga_fb_front 24
|
|
when "0110" =>
|
|
host_fb_front <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_vga_fb_back 28
|
|
when "0111" =>
|
|
bufchg_flag_ack <= '1';
|
|
host_fb_back <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_addr_src_0 32
|
|
when "1000" =>
|
|
blit_addr_src_0 <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_addr_src_1 36
|
|
when "1001" =>
|
|
blit_addr_src_1 <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_addr_dst 40
|
|
when "1010" =>
|
|
blit_addr_dst <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_dimx_src_0 44
|
|
when "1011" =>
|
|
blit_dimx_src_0 <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_dimx_src_1 48
|
|
when "1100" =>
|
|
blit_dimx_src_1 <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_dimx_dst 52
|
|
when "1101" =>
|
|
blit_dimx_dst <= SDAT_I(31 downto 3) & "000";
|
|
|
|
-- sys_blit_nx 56
|
|
when "1110" =>
|
|
host_blit_nx <= SDAT_I;
|
|
blit_nx <= '0' & SDAT_I(31 downto 1);
|
|
|
|
-- sys_blit_ny 60
|
|
when "1111" =>
|
|
blit_ny <= SDAT_I;
|
|
|
|
when others => null;
|
|
end case;
|
|
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
---------------------------------------------------------------------------------------------
|
|
|
|
end Behavioral;
|