jens 584ac47a8a - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. ...

Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy.
  Consectutive load instructions without nops using same target register (which is legal) like
   lw $1, 0(mem)
   lwl $1, 1(mem)
  or
   lwl $1, 0(mem)
   lwr $1, 1(mem)
  or similar, lead to incorrect result. Now it's fixed.


git-svn-id: http://moon:8086/svn/vhdl/trunk@519 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-17 12:58:28 +00:00

..

bsp

added second UART

2009-10-14 22:06:19 +00:00

dist

update

2009-10-17 12:58:15 +00:00

doc

- detailed EX_stage according to implementation

2009-08-08 17:25:09 +00:00

sim

- added pin non-maskable interrupt (NMI).

2009-10-03 17:01:36 +00:00

src

- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.

2009-10-17 12:58:28 +00:00

syn/ise101

- removed reference to fifo_sync_dist.

2009-05-06 10:36:58 +00:00

tools

- added switch EB/EL to switch endianess

2009-04-15 13:56:58 +00:00

todo.txt

update

2009-08-09 16:53:45 +00:00