jens 584ac47a8a - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. ...

Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy.
  Consectutive load instructions without nops using same target register (which is legal) like
   lw $1, 0(mem)
   lwl $1, 1(mem)
  or
   lwl $1, 0(mem)
   lwr $1, 1(mem)
  or similar, lead to incorrect result. Now it's fixed.


git-svn-id: http://moon:8086/svn/vhdl/trunk@519 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-17 12:58:28 +00:00

..

core

- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.

2009-10-17 12:58:28 +00:00

async_defs.vhd

- added async_be

2009-02-08 17:34:18 +00:00

bootloader.ROM.vhd

- new build

2009-02-07 11:40:11 +00:00

tb_mips_muldiv.vhd

- fixed some bugs

2008-10-26 23:17:57 +00:00

tb_mips_top.vhd

- added pin non-maskable interrupt (NMI).

2009-10-03 16:41:26 +00:00