jens 584ac47a8a - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. ...

Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy.
  Consectutive load instructions without nops using same target register (which is legal) like
   lw $1, 0(mem)
   lwl $1, 1(mem)
  or
   lwl $1, 0(mem)
   lwr $1, 1(mem)
  or similar, lead to incorrect result. Now it's fixed.


git-svn-id: http://moon:8086/svn/vhdl/trunk@519 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-17 12:58:28 +00:00

..

ac97_ctrl

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

CPUs

- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.

2009-10-17 12:58:28 +00:00

FIFO

- renamed

2009-01-30 21:22:25 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

del

2009-08-07 12:04:54 +00:00

PCK_FIO-1.16

Initial import

2008-08-23 08:20:30 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

radio

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SDRAM

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

- added tx-complete and tx-empty to ports

2009-10-13 21:21:57 +00:00

VGA_ctrl

- added test color register base + 0x80

2009-05-01 19:26:43 +00:00