jens 4e66c8c1c8 - better reset values for pipe regs ...

- WB_stall is stall_all. More WB signal are stalled, may have functional impact or not

git-svn-id: http://moon:8086/svn/vhdl/trunk@1093 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-16 17:02:11 +00:00

Common

- added

2014-07-23 20:34:41 +00:00

lib

- better reset values for pipe regs

2015-05-16 17:02:11 +00:00

projects/mips_sys

- no change, only touched

2015-02-07 08:04:55 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%