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- better reset values for pipe regs

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- WB_stall is stall_all. More WB signal are stalled, may have functional impact or not

git-svn-id: http://moon:8086/svn/vhdl/trunk@1093 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 17:02:11 +00:00
parent 02e2f89308
commit 4e66c8c1c8
1 changed files with 22 additions and 15 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+22 -15
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@@ -188,7 +188,7 @@ begin
sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit;
sdu.EX_stall <= sdu.stall_all;
sdu.MEM_stall <= sdu.stall_all;
sdu.WB_stall <= '0';
sdu.WB_stall <= sdu.stall_all;
sdu.mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
sdu.imem_dep <= not imem_rdy;
@@ -305,9 +305,9 @@ proc_stage_pc_next:
end process;
proc_stage_branch:
process(clk_2)
process(clk_1)
begin
if rising_edge(clk_2) then
if falling_edge(clk_1) then
if branch_ce = '1' then
pc.branch_take <= '0';
if EX_stage.ctrl.branch = '1' then
@@ -491,7 +491,8 @@ proc_stage_ID_EX_1:
EX_stage.reg_write <= '0';
EX_stage.epc <= (others => '0');
EX_stage.pcn <= (others => '0');
EX_stage.events_in <= events_clr;
EX_stage.events_in <= events_clr;
EX_stage.nop <= '1';
elsif sdu.EX_stall = '0' then
EX_stage.reg_a <= ID_stage.reg_a;
EX_stage.reg_b <= ID_stage.reg_b;
@@ -750,11 +751,17 @@ proc_stage_MEM_n:
begin
if rising_edge(clk_1) then
if stage_rst(2) = '1' then
MEM_stage.op <= op_nop;
MEM_stage.wreg_we <= '0';
MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0');
MEM_stage.va <= (others => '0');
MEM_stage.pcn <= (others => '0');
MEM_stage.ex_result <= (others => '0');
MEM_stage.epc <= (others => '0');
MEM_stage.op <= op_nop;
MEM_stage.wreg_we <= '0';
MEM_stage.reg_wptr <= (others => '0');
MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0');
MEM_stage.events_in <= events_clr;
MEM_stage.nop <= '1';
elsif sdu.MEM_stall = '0' then
MEM_stage.events_in <= EX_stage.events;
MEM_stage.op <= EX_stage.op;
@@ -841,24 +848,24 @@ proc_stage_WB_p:
begin
if rising_edge(clk_1) then
if stage_rst(3) = '1' then
WB_stage.nop <= '1';
WB_stage.op <= op_nop;
WB_stage.wreg_we <= '1';
WB_stage.reg_wptr <= (others => '0');
WB_stage.data <= (others => '0');
WB_stage.events <= events_clr;
WB_stage.events <= events_clr;
WB_stage.bd <= '0';
elsif sdu.WB_stall = '0' then
WB_stage.nop <= sdu.WB_nop;
WB_stage.op <= MEM_stage.op;
WB_stage.wreg_we <= MEM_stage.wreg_we;
WB_stage.reg_wptr <= MEM_stage.reg_wptr;
WB_stage.data <= MEM_stage.data;
WB_stage.exc <= '0';
if sdu.stall_all = '0' then
WB_stage.exc <= MEM_stage.exc;
if MEM_stage.exc = '1' then
WB_stage.events <= MEM_stage.events;
end if;
WB_stage.exc <= MEM_stage.exc;
if MEM_stage.exc = '1' then
WB_stage.events <= MEM_stage.events;
end if;
WB_stage.nop <= sdu.WB_nop;
if sdu.WB_nop = '1' then
WB_stage.op <= op_nop;
WB_stage.wreg_we <= '0';