jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- no change, only touched

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1076 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-02-07 08:04:55 +00:00
parent 2d7ca921d4
commit 7649454e46
10 changed files with 2292 additions and 2292 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/ise92/mips_sys/mips_sys.prj
+43 -43
View File
@@ -1,43 +1,43 @@
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/sdram_config.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../../src/sys_types.vhd"
vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd"
vhdl work "../../../../lib/uart/uart_tx.vhd"
vhdl work "../../../../lib/uart/uart_rx.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/misc/rom_wb.vhd"
vhdl work "../../../../lib/misc/ram_wb.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../../../lib/misc/gpio_wb.vhd"
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
vhdl work "../../../../lib/misc/async_port_wb.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
vhdl work "../../src/mips_sys.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/sdram_config.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../../src/sys_types.vhd"
vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd"
vhdl work "../../../../lib/uart/uart_tx.vhd"
vhdl work "../../../../lib/uart/uart_rx.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/misc/rom_wb.vhd"
vhdl work "../../../../lib/misc/ram_wb.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../../../lib/misc/gpio_wb.vhd"
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
vhdl work "../../../../lib/misc/async_port_wb.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
vhdl work "../../src/mips_sys.vhd"
projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+43 -43
View File
@@ -1,43 +1,43 @@
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
projects/mips_sys/ise92/mips_sys/ucf/systest.ucf
+469 -469
View File
@@ -1,469 +1,469 @@
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
CONFIG STEPPING = "ES";
# Bus clock nets
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
NET sys_rst_n_in PULLUP;
NET "sys_rst_n_in" TIG;
NET "rst" TIG;
# Locate DCM/BUFG - Tools can probably figure them out automatically
# but just LOC them down to be safe
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
# GOOD
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
////////////////////////////////////////////////////////////////////////////
// Misc Board Signals
////////////////////////////////////////////////////////////////////////////
NET sys_error<0> LOC = V6;
NET sys_error<1> LOC = L24;
NET sys_error<*> IOSTANDARD = LVCMOS33;
NET sys_error<*> DRIVE = 2;
NET sys_error<*> TIG;
////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
NET "sys_btn<*>" PULLDOWN;
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" PULLDOWN;
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e SLEW = SLOW;
NET sys_lcd_e DRIVE = 2;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs SLEW = SLOW;
NET sys_lcd_rs DRIVE = 2;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw SLEW = SLOW;
NET sys_lcd_rw DRIVE = 2;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> SLEW = SLOW;
NET sys_lcd_d<*> DRIVE = 2;
NET sys_lcd_d<*> PULLDOWN;
NET sys_lcd_d<*> TIG;
#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for DDR Controllers
#------------------------------------------------------------------------------
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
NET sys_sdr_data<0> LOC = H20; # DDR_D0
NET sys_sdr_data<1> LOC = E23; # DDR_D1
NET sys_sdr_data<2> LOC = H26; # DDR_D2
NET sys_sdr_data<3> LOC = H22; # DDR_D3
NET sys_sdr_data<4> LOC = E25; # DDR_D4
NET sys_sdr_data<5> LOC = E26; # DDR_D5
NET sys_sdr_data<6> LOC = F26; # DDR_D6
NET sys_sdr_data<7> LOC = E24; # DDR_D7
NET sys_sdr_data<8> LOC = E20; # DDR_D8
NET sys_sdr_data<9> LOC = A22; # DDR_D9
NET sys_sdr_data<10> LOC = C23; # DDR_D10
NET sys_sdr_data<11> LOC = C24; # DDR_D11
NET sys_sdr_data<12> LOC = A20; # DDR_D12
NET sys_sdr_data<13> LOC = A21; # DDR_D13
NET sys_sdr_data<14> LOC = D24; # DDR_D14
NET sys_sdr_data<15> LOC = E18; # DDR_D15
NET sys_sdr_data<16> LOC = F18; # DDR_D16
NET sys_sdr_data<17> LOC = A19; # DDR_D17
NET sys_sdr_data<18> LOC = F19; # DDR_D18
NET sys_sdr_data<19> LOC = B23; # DDR_D19
NET sys_sdr_data<20> LOC = E21; # DDR_D20
NET sys_sdr_data<21> LOC = D22; # DDR_D21
NET sys_sdr_data<22> LOC = D23; # DDR_D22
NET sys_sdr_data<23> LOC = B24; # DDR_D23
NET sys_sdr_data<24> LOC = E22; # DDR_D24
NET sys_sdr_data<25> LOC = F20; # DDR_D25
NET sys_sdr_data<26> LOC = H23; # DDR_D26
NET sys_sdr_data<27> LOC = G25; # DDR_D27
NET sys_sdr_data<28> LOC = G26; # DDR_D28
NET sys_sdr_data<29> LOC = H25; # DDR_D29
NET sys_sdr_data<30> LOC = H24; # DDR_D30
NET sys_sdr_data<31> LOC = H21; # DDR_D31
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
NET sys_sdr_a_q<*> FAST;
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
NET sys_sdr_ba_q<*> FAST;
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn FAST;
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
NET sys_sdr_cke_q FAST;
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_p FAST;
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
NET sys_sdr_clk_fb IOBDELAY = NONE;
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_n FAST;
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn FAST;
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cs_qn FAST;
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_ras_qn FAST;
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_we_qn FAST;
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
NET sys_sdr_dqs_q<*> FAST;
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
NET sys_sdr_dm_q<*> FAST;
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_data<*> IOBDELAY = NONE;
NET sys_sdr_data<*> FAST;
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
# Timing Constraint for DDR Feedback Clock
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
# USB
NET sys_usb_a<0> LOC = Y10;
NET sys_usb_a<1> LOC = AA10;
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
NET sys_usb_d<0> LOC = AB7;
NET sys_usb_d<1> LOC = AC9;
NET sys_usb_d<2> LOC = AB9;
NET sys_usb_d<3> LOC = AE6;
NET sys_usb_d<4> LOC = AD6;
NET sys_usb_d<5> LOC = AF9;
NET sys_usb_d<6> LOC = AE9;
NET sys_usb_d<7> LOC = AD8;
NET sys_usb_d<8> LOC = AC8;
NET sys_usb_d<9> LOC = AF4;
NET sys_usb_d<10> LOC = AE4;
NET sys_usb_d<11> LOC = AD3;
NET sys_usb_d<12> LOC = AC3;
NET sys_usb_d<13> LOC = AF6;
NET sys_usb_d<14> LOC = AF5;
NET sys_usb_d<15> LOC = AA7;
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
NET sys_usb_d<*> SLEW = FAST;
NET sys_usb_d<*> DRIVE = 8;
NET sys_usb_d<*> PULLDOWN;
NET sys_usb_rdn LOC = AA8;
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
NET sys_usb_rdn SLEW = FAST;
NET sys_usb_rdn DRIVE = 8;
NET sys_usb_wrn LOC = Y8;
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
NET sys_usb_wrn SLEW = FAST;
NET sys_usb_wrn DRIVE = 8;
NET sys_usb_csn LOC = AF10;
NET sys_usb_csn IOSTANDARD = LVCMOS33;
NET sys_usb_csn SLEW = FAST;
NET sys_usb_csn DRIVE = 8;
NET sys_usb_rstn LOC = A7;
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
NET sys_usb_rstn TIG;
NET sys_usb_int LOC = V5;
NET sys_usb_int IOSTANDARD = LVCMOS33;
NET sys_usb_int PULLDOWN;
NET sys_usb_int TIG;
# FLASH
NET sys_flash_a<24> LOC = T21;
NET sys_flash_a<23> LOC = U20;
NET sys_flash_a<22> LOC = T19;
NET sys_flash_a<21> LOC = AC5;
NET sys_flash_a<20> LOC = AB5;
NET sys_flash_a<19> LOC = AC4;
NET sys_flash_a<18> LOC = AB4;
NET sys_flash_a<17> LOC = AB3;
NET sys_flash_a<16> LOC = AA4;
NET sys_flash_a<15> LOC = AA3;
NET sys_flash_a<14> LOC = W5;
NET sys_flash_a<13> LOC = W6;
NET sys_flash_a<12> LOC = W3;
NET sys_flash_a<11> LOC = AF3;
NET sys_flash_a<10> LOC = AE3;
NET sys_flash_a<9> LOC = AD2;
NET sys_flash_a<8> LOC = AD1;
NET sys_flash_a<7> LOC = AC2;
NET sys_flash_a<6> LOC = AC1;
NET sys_flash_a<5> LOC = AB2;
NET sys_flash_a<4> LOC = AB1;
NET sys_flash_a<3> LOC = AA1;
NET sys_flash_a<2> LOC = Y2;
NET sys_flash_a<1> LOC = Y1;
NET sys_flash_a<0> LOC = T20;
NET sys_flash_d<31> LOC = F14;
NET sys_flash_d<30> LOC = F13;
NET sys_flash_d<29> LOC = F12;
NET sys_flash_d<28> LOC = F11;
NET sys_flash_d<27> LOC = F16;
NET sys_flash_d<26> LOC = F15;
NET sys_flash_d<25> LOC = D14;
NET sys_flash_d<24> LOC = D13;
NET sys_flash_d<23> LOC = D15;
NET sys_flash_d<22> LOC = E14;
NET sys_flash_d<21> LOC = C11;
NET sys_flash_d<20> LOC = D11;
NET sys_flash_d<19> LOC = D16;
NET sys_flash_d<18> LOC = C16;
NET sys_flash_d<17> LOC = E13;
NET sys_flash_d<16> LOC = D12;
NET sys_flash_d<15> LOC = AA14;
NET sys_flash_d<14> LOC = AB14;
NET sys_flash_d<13> LOC = AC12;
NET sys_flash_d<12> LOC = AC11;
NET sys_flash_d<11> LOC = AA16;
NET sys_flash_d<10> LOC = AA15;
NET sys_flash_d<9> LOC = AB13;
NET sys_flash_d<8> LOC = AA13;
NET sys_flash_d<7> LOC = AC14;
NET sys_flash_d<6> LOC = AD14;
NET sys_flash_d<5> LOC = AA12;
NET sys_flash_d<4> LOC = AA11;
NET sys_flash_d<3> LOC = AC16;
NET sys_flash_d<2> LOC = AC15;
NET sys_flash_d<1> LOC = AC13;
NET sys_flash_d<0> LOC = AD13;
NET sys_flash_rdn LOC = AC6;
NET sys_flash_wrn LOC = AB6;
NET sys_flash_ce LOC = W7;
NET sys_flash_rstn LOC = AD10;
NET sys_flash_byten LOC = N22;
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
NET sys_flash_a<*> SLEW = FAST;
NET sys_flash_a<*> DRIVE = 8;
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
NET sys_flash_d<*> DRIVE = 12;
NET sys_flash_d<*> SLEW = FAST;
NET sys_flash_d<*> PULLDOWN;
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
NET sys_flash_rdn SLEW = FAST;
NET sys_flash_rdn DRIVE = 8;
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
NET sys_flash_wrn SLEW = FAST;
NET sys_flash_wrn DRIVE = 8;
NET sys_flash_ce IOSTANDARD = LVDCI_33;
NET sys_flash_ce SLEW = FAST;
NET sys_flash_ce DRIVE = 8;
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
NET sys_flash_rstn DRIVE = 8;
NET sys_flash_rstn SLEW = FAST;
NET sys_flash_rstn TIG;
NET sys_flash_byten IOSTANDARD = LVCMOS33;
NET sys_flash_byten DRIVE = 8;
NET sys_flash_byten SLEW = FAST;
NET sys_flash_byten TIG;
# VGA
NET sys_vga_blue<0> LOC = M21; # VGA_B0
NET sys_vga_blue<1> LOC = M26; # VGA_B1
NET sys_vga_blue<2> LOC = L26; # VGA_B2
NET sys_vga_blue<3> LOC = C5; # VGA_B3
NET sys_vga_blue<4> LOC = C7; # VGA_B4
NET sys_vga_blue<5> LOC = B7; # VGA_B5
NET sys_vga_blue<6> LOC = G8; # VGA_B6
NET sys_vga_blue<7> LOC = F8; # VGA_B7
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<*> SLEW = FAST;
NET sys_vga_blue<*> DRIVE = 8;
NET sys_vga_clk LOC = AF8;
NET sys_vga_clk IOSTANDARD = LVDCI_33;
NET sys_vga_clk SLEW = FAST;
NET sys_vga_clk DRIVE = 8;
NET sys_vga_green<0> LOC = M22; # VGA_G0
NET sys_vga_green<1> LOC = M23; # VGA_G1
NET sys_vga_green<2> LOC = M20; # VGA_G2
NET sys_vga_green<3> LOC = E4; # VGA_G3
NET sys_vga_green<4> LOC = D3; # VGA_G4
NET sys_vga_green<5> LOC = H7; # VGA_G5
NET sys_vga_green<6> LOC = H8; # VGA_G6
NET sys_vga_green<7> LOC = C1; # VGA_G7
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
NET sys_vga_green<*> SLEW = FAST;
NET sys_vga_green<*> DRIVE = 8;
NET sys_vga_hsync LOC = C10;
NET sys_vga_hsync SLEW = FAST;
NET sys_vga_hsync DRIVE = 8;
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
NET sys_vga_red<0> LOC = N23; #VGA_R0
NET sys_vga_red<1> LOC = N24; #VGA_R1
NET sys_vga_red<2> LOC = N25; #VGA_R2
NET sys_vga_red<3> LOC = C2; #VGA_R3
NET sys_vga_red<4> LOC = G7; #VGA_R4
NET sys_vga_red<5> LOC = F7; #VGA_R5
NET sys_vga_red<6> LOC = E5; #VGA_R6
NET sys_vga_red<7> LOC = E6; #VGA_R7
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
NET sys_vga_red<*> SLEW = FAST;
NET sys_vga_red<*> DRIVE = 8;
NET sys_vga_vsync LOC = A8;
NET sys_vga_vsync SLEW = FAST;
NET sys_vga_vsync DRIVE = 8;
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
NET sys_vga_blank_n LOC = M24;
NET sys_vga_blank_n SLEW = FAST;
NET sys_vga_blank_n DRIVE = 8;
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
NET sys_vga_sync_n LOC = L23;
NET sys_vga_sync_n SLEW = FAST;
NET sys_vga_sync_n DRIVE = 8;
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
CONFIG STEPPING = "ES";
# Bus clock nets
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
NET sys_rst_n_in PULLUP;
NET "sys_rst_n_in" TIG;
NET "rst" TIG;
# Locate DCM/BUFG - Tools can probably figure them out automatically
# but just LOC them down to be safe
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
# GOOD
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
////////////////////////////////////////////////////////////////////////////
// Misc Board Signals
////////////////////////////////////////////////////////////////////////////
NET sys_error<0> LOC = V6;
NET sys_error<1> LOC = L24;
NET sys_error<*> IOSTANDARD = LVCMOS33;
NET sys_error<*> DRIVE = 2;
NET sys_error<*> TIG;
////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
NET "sys_btn<*>" PULLDOWN;
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" PULLDOWN;
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e SLEW = SLOW;
NET sys_lcd_e DRIVE = 2;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs SLEW = SLOW;
NET sys_lcd_rs DRIVE = 2;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw SLEW = SLOW;
NET sys_lcd_rw DRIVE = 2;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> SLEW = SLOW;
NET sys_lcd_d<*> DRIVE = 2;
NET sys_lcd_d<*> PULLDOWN;
NET sys_lcd_d<*> TIG;
#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for DDR Controllers
#------------------------------------------------------------------------------
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
NET sys_sdr_data<0> LOC = H20; # DDR_D0
NET sys_sdr_data<1> LOC = E23; # DDR_D1
NET sys_sdr_data<2> LOC = H26; # DDR_D2
NET sys_sdr_data<3> LOC = H22; # DDR_D3
NET sys_sdr_data<4> LOC = E25; # DDR_D4
NET sys_sdr_data<5> LOC = E26; # DDR_D5
NET sys_sdr_data<6> LOC = F26; # DDR_D6
NET sys_sdr_data<7> LOC = E24; # DDR_D7
NET sys_sdr_data<8> LOC = E20; # DDR_D8
NET sys_sdr_data<9> LOC = A22; # DDR_D9
NET sys_sdr_data<10> LOC = C23; # DDR_D10
NET sys_sdr_data<11> LOC = C24; # DDR_D11
NET sys_sdr_data<12> LOC = A20; # DDR_D12
NET sys_sdr_data<13> LOC = A21; # DDR_D13
NET sys_sdr_data<14> LOC = D24; # DDR_D14
NET sys_sdr_data<15> LOC = E18; # DDR_D15
NET sys_sdr_data<16> LOC = F18; # DDR_D16
NET sys_sdr_data<17> LOC = A19; # DDR_D17
NET sys_sdr_data<18> LOC = F19; # DDR_D18
NET sys_sdr_data<19> LOC = B23; # DDR_D19
NET sys_sdr_data<20> LOC = E21; # DDR_D20
NET sys_sdr_data<21> LOC = D22; # DDR_D21
NET sys_sdr_data<22> LOC = D23; # DDR_D22
NET sys_sdr_data<23> LOC = B24; # DDR_D23
NET sys_sdr_data<24> LOC = E22; # DDR_D24
NET sys_sdr_data<25> LOC = F20; # DDR_D25
NET sys_sdr_data<26> LOC = H23; # DDR_D26
NET sys_sdr_data<27> LOC = G25; # DDR_D27
NET sys_sdr_data<28> LOC = G26; # DDR_D28
NET sys_sdr_data<29> LOC = H25; # DDR_D29
NET sys_sdr_data<30> LOC = H24; # DDR_D30
NET sys_sdr_data<31> LOC = H21; # DDR_D31
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
NET sys_sdr_a_q<*> FAST;
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
NET sys_sdr_ba_q<*> FAST;
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn FAST;
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
NET sys_sdr_cke_q FAST;
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_p FAST;
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
NET sys_sdr_clk_fb IOBDELAY = NONE;
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_n FAST;
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn FAST;
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_cs_qn FAST;
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_ras_qn FAST;
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
NET sys_sdr_we_qn FAST;
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
NET sys_sdr_dqs_q<*> FAST;
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
NET sys_sdr_dm_q<*> FAST;
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_data<*> IOBDELAY = NONE;
NET sys_sdr_data<*> FAST;
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
# Timing Constraint for DDR Feedback Clock
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
# USB
NET sys_usb_a<0> LOC = Y10;
NET sys_usb_a<1> LOC = AA10;
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
NET sys_usb_d<0> LOC = AB7;
NET sys_usb_d<1> LOC = AC9;
NET sys_usb_d<2> LOC = AB9;
NET sys_usb_d<3> LOC = AE6;
NET sys_usb_d<4> LOC = AD6;
NET sys_usb_d<5> LOC = AF9;
NET sys_usb_d<6> LOC = AE9;
NET sys_usb_d<7> LOC = AD8;
NET sys_usb_d<8> LOC = AC8;
NET sys_usb_d<9> LOC = AF4;
NET sys_usb_d<10> LOC = AE4;
NET sys_usb_d<11> LOC = AD3;
NET sys_usb_d<12> LOC = AC3;
NET sys_usb_d<13> LOC = AF6;
NET sys_usb_d<14> LOC = AF5;
NET sys_usb_d<15> LOC = AA7;
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
NET sys_usb_d<*> SLEW = FAST;
NET sys_usb_d<*> DRIVE = 8;
NET sys_usb_d<*> PULLDOWN;
NET sys_usb_rdn LOC = AA8;
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
NET sys_usb_rdn SLEW = FAST;
NET sys_usb_rdn DRIVE = 8;
NET sys_usb_wrn LOC = Y8;
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
NET sys_usb_wrn SLEW = FAST;
NET sys_usb_wrn DRIVE = 8;
NET sys_usb_csn LOC = AF10;
NET sys_usb_csn IOSTANDARD = LVCMOS33;
NET sys_usb_csn SLEW = FAST;
NET sys_usb_csn DRIVE = 8;
NET sys_usb_rstn LOC = A7;
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
NET sys_usb_rstn TIG;
NET sys_usb_int LOC = V5;
NET sys_usb_int IOSTANDARD = LVCMOS33;
NET sys_usb_int PULLDOWN;
NET sys_usb_int TIG;
# FLASH
NET sys_flash_a<24> LOC = T21;
NET sys_flash_a<23> LOC = U20;
NET sys_flash_a<22> LOC = T19;
NET sys_flash_a<21> LOC = AC5;
NET sys_flash_a<20> LOC = AB5;
NET sys_flash_a<19> LOC = AC4;
NET sys_flash_a<18> LOC = AB4;
NET sys_flash_a<17> LOC = AB3;
NET sys_flash_a<16> LOC = AA4;
NET sys_flash_a<15> LOC = AA3;
NET sys_flash_a<14> LOC = W5;
NET sys_flash_a<13> LOC = W6;
NET sys_flash_a<12> LOC = W3;
NET sys_flash_a<11> LOC = AF3;
NET sys_flash_a<10> LOC = AE3;
NET sys_flash_a<9> LOC = AD2;
NET sys_flash_a<8> LOC = AD1;
NET sys_flash_a<7> LOC = AC2;
NET sys_flash_a<6> LOC = AC1;
NET sys_flash_a<5> LOC = AB2;
NET sys_flash_a<4> LOC = AB1;
NET sys_flash_a<3> LOC = AA1;
NET sys_flash_a<2> LOC = Y2;
NET sys_flash_a<1> LOC = Y1;
NET sys_flash_a<0> LOC = T20;
NET sys_flash_d<31> LOC = F14;
NET sys_flash_d<30> LOC = F13;
NET sys_flash_d<29> LOC = F12;
NET sys_flash_d<28> LOC = F11;
NET sys_flash_d<27> LOC = F16;
NET sys_flash_d<26> LOC = F15;
NET sys_flash_d<25> LOC = D14;
NET sys_flash_d<24> LOC = D13;
NET sys_flash_d<23> LOC = D15;
NET sys_flash_d<22> LOC = E14;
NET sys_flash_d<21> LOC = C11;
NET sys_flash_d<20> LOC = D11;
NET sys_flash_d<19> LOC = D16;
NET sys_flash_d<18> LOC = C16;
NET sys_flash_d<17> LOC = E13;
NET sys_flash_d<16> LOC = D12;
NET sys_flash_d<15> LOC = AA14;
NET sys_flash_d<14> LOC = AB14;
NET sys_flash_d<13> LOC = AC12;
NET sys_flash_d<12> LOC = AC11;
NET sys_flash_d<11> LOC = AA16;
NET sys_flash_d<10> LOC = AA15;
NET sys_flash_d<9> LOC = AB13;
NET sys_flash_d<8> LOC = AA13;
NET sys_flash_d<7> LOC = AC14;
NET sys_flash_d<6> LOC = AD14;
NET sys_flash_d<5> LOC = AA12;
NET sys_flash_d<4> LOC = AA11;
NET sys_flash_d<3> LOC = AC16;
NET sys_flash_d<2> LOC = AC15;
NET sys_flash_d<1> LOC = AC13;
NET sys_flash_d<0> LOC = AD13;
NET sys_flash_rdn LOC = AC6;
NET sys_flash_wrn LOC = AB6;
NET sys_flash_ce LOC = W7;
NET sys_flash_rstn LOC = AD10;
NET sys_flash_byten LOC = N22;
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
NET sys_flash_a<*> SLEW = FAST;
NET sys_flash_a<*> DRIVE = 8;
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
NET sys_flash_d<*> DRIVE = 12;
NET sys_flash_d<*> SLEW = FAST;
NET sys_flash_d<*> PULLDOWN;
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
NET sys_flash_rdn SLEW = FAST;
NET sys_flash_rdn DRIVE = 8;
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
NET sys_flash_wrn SLEW = FAST;
NET sys_flash_wrn DRIVE = 8;
NET sys_flash_ce IOSTANDARD = LVDCI_33;
NET sys_flash_ce SLEW = FAST;
NET sys_flash_ce DRIVE = 8;
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
NET sys_flash_rstn DRIVE = 8;
NET sys_flash_rstn SLEW = FAST;
NET sys_flash_rstn TIG;
NET sys_flash_byten IOSTANDARD = LVCMOS33;
NET sys_flash_byten DRIVE = 8;
NET sys_flash_byten SLEW = FAST;
NET sys_flash_byten TIG;
# VGA
NET sys_vga_blue<0> LOC = M21; # VGA_B0
NET sys_vga_blue<1> LOC = M26; # VGA_B1
NET sys_vga_blue<2> LOC = L26; # VGA_B2
NET sys_vga_blue<3> LOC = C5; # VGA_B3
NET sys_vga_blue<4> LOC = C7; # VGA_B4
NET sys_vga_blue<5> LOC = B7; # VGA_B5
NET sys_vga_blue<6> LOC = G8; # VGA_B6
NET sys_vga_blue<7> LOC = F8; # VGA_B7
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<*> SLEW = FAST;
NET sys_vga_blue<*> DRIVE = 8;
NET sys_vga_clk LOC = AF8;
NET sys_vga_clk IOSTANDARD = LVDCI_33;
NET sys_vga_clk SLEW = FAST;
NET sys_vga_clk DRIVE = 8;
NET sys_vga_green<0> LOC = M22; # VGA_G0
NET sys_vga_green<1> LOC = M23; # VGA_G1
NET sys_vga_green<2> LOC = M20; # VGA_G2
NET sys_vga_green<3> LOC = E4; # VGA_G3
NET sys_vga_green<4> LOC = D3; # VGA_G4
NET sys_vga_green<5> LOC = H7; # VGA_G5
NET sys_vga_green<6> LOC = H8; # VGA_G6
NET sys_vga_green<7> LOC = C1; # VGA_G7
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
NET sys_vga_green<*> SLEW = FAST;
NET sys_vga_green<*> DRIVE = 8;
NET sys_vga_hsync LOC = C10;
NET sys_vga_hsync SLEW = FAST;
NET sys_vga_hsync DRIVE = 8;
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
NET sys_vga_red<0> LOC = N23; #VGA_R0
NET sys_vga_red<1> LOC = N24; #VGA_R1
NET sys_vga_red<2> LOC = N25; #VGA_R2
NET sys_vga_red<3> LOC = C2; #VGA_R3
NET sys_vga_red<4> LOC = G7; #VGA_R4
NET sys_vga_red<5> LOC = F7; #VGA_R5
NET sys_vga_red<6> LOC = E5; #VGA_R6
NET sys_vga_red<7> LOC = E6; #VGA_R7
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
NET sys_vga_red<*> SLEW = FAST;
NET sys_vga_red<*> DRIVE = 8;
NET sys_vga_vsync LOC = A8;
NET sys_vga_vsync SLEW = FAST;
NET sys_vga_vsync DRIVE = 8;
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
NET sys_vga_blank_n LOC = M24;
NET sys_vga_blank_n SLEW = FAST;
NET sys_vga_blank_n DRIVE = 8;
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
NET sys_vga_sync_n LOC = L23;
NET sys_vga_sync_n SLEW = FAST;
NET sys_vga_sync_n DRIVE = 8;
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
projects/mips_sys/sim/tb_mips_sys.fdo
+118 -118
View File
@@ -1,118 +1,118 @@
## NOTE: Do not edit this file.
##
vlib work
# Configs
vcom -explicit -93 "../src/sdram_config_sim.vhd"
# Packages
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# RAMs
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd"
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ra_sim.vhd"
#vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
# FIFOS
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
# CPU
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/bootloader_flash.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
# UART
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
# PS2
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
# GPIO
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
# LCD
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
# Flash and USB
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
vcom -explicit -93 "../src/async_defs_sim.vhd"
# Sync SRAM
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
# AC-97
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Ethernet MAC
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
# Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd"
vsim -t 1ps -lib work tb_mips_sys
do {tb_mips_sys.wdo}
view wave
view structure
view signals
run 10 ms
## NOTE: Do not edit this file.
##
vlib work
# Configs
vcom -explicit -93 "../src/sdram_config_sim.vhd"
# Packages
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# RAMs
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd"
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ra_sim.vhd"
#vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
# FIFOS
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
# CPU
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/bootloader_flash.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
# UART
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
# PS2
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
# GPIO
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
# LCD
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
# Flash and USB
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
vcom -explicit -93 "../src/async_defs_sim.vhd"
# Sync SRAM
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
# AC-97
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Ethernet MAC
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
# Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd"
vsim -t 1ps -lib work tb_mips_sys
do {tb_mips_sys.wdo}
view wave
view structure
view signals
run 10 ms
projects/mips_sys/sim/tb_mips_sys.wdo
+457 -457
View File
@@ -1,457 +1,457 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
add wave -noupdate -format Literal /tb_mips_sys/dip
add wave -noupdate -format Literal /tb_mips_sys/btn
add wave -noupdate -format Literal /tb_mips_sys/led
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
add wave -noupdate -format Logic /tb_mips_sys/refresh
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/sys_error
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {Clock Gen}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
add wave -noupdate -divider AC97
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
add wave -noupdate -format Logic /tb_mips_sys/ac_synced
add wave -noupdate -divider {CPU Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
add wave -noupdate -divider {VGA Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/read_cycle
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/ack
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/dat
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle
add wave -noupdate -divider VGA-Slave
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/mrdy_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/stb_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
add wave -noupdate -divider <NULL>
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_ny
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_const_color
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_func
add wave -noupdate -divider <NULL>
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_const_color_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request_set
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_en
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_avail
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_nx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_ny
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_cc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_func
add wave -noupdate -divider USB
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
add wave -noupdate -divider {Sync SRAM}
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
add wave -noupdate -divider {MIPS TOP}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -divider {CPU DMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {CPU IMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {User ROM}
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
add wave -noupdate -divider I-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_cache_index
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_word_index
add wave -noupdate -divider D-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/mrdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_data_reg
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we2
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_hit_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_word_index
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {9216870000 ps} 0} {{Cursor 100} {98503600 ps} 0} {{Cursor 3} {15592084279 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {15591849308 ps} {15592330693 ps}
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
add wave -noupdate -format Literal /tb_mips_sys/dip
add wave -noupdate -format Literal /tb_mips_sys/btn
add wave -noupdate -format Literal /tb_mips_sys/led
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
add wave -noupdate -format Logic /tb_mips_sys/refresh
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/sys_error
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {Clock Gen}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
add wave -noupdate -divider AC97
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
add wave -noupdate -format Logic /tb_mips_sys/ac_synced
add wave -noupdate -divider {CPU Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
add wave -noupdate -divider {VGA Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/read_cycle
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/ack
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/dat
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle
add wave -noupdate -divider VGA-Slave
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/mrdy_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/stb_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
add wave -noupdate -divider <NULL>
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_ny
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_const_color
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_func
add wave -noupdate -divider <NULL>
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_const_color_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request_set
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_en
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_avail
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_dst
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_nx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_ny
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_cc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_func
add wave -noupdate -divider USB
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
add wave -noupdate -divider {Sync SRAM}
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
add wave -noupdate -divider {MIPS TOP}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -divider {CPU DMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {CPU IMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {User ROM}
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
add wave -noupdate -divider I-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_cache_index
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_word_index
add wave -noupdate -divider D-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/mrdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dat_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cyc_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/sn
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_data_reg
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we2
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_hit_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_tag
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_cache_index
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_word_index
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {9216870000 ps} 0} {{Cursor 100} {98503600 ps} 0} {{Cursor 3} {15592084279 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {15591849308 ps} {15592330693 ps}
projects/mips_sys/sim/tb_mips_sys_emac.fdo
+116 -116
View File
@@ -1,116 +1,116 @@
## NOTE: Do not edit this file.
##
vlib work
# Configs
vcom -explicit -93 "../src/sdram_config_sim.vhd"
# Packages
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# RAMs
vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
# FIFOS
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
# CPU
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/bootloader.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
# UART
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
# PS2
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
# GPIO
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
# LCD
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
# Flash and USB
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
vcom -explicit -93 "../src/async_defs_sim.vhd"
# Sync SRAM
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
# AC-97
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Ethernet MAC
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
# Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd"
vsim -t 1ps -lib work tb_mips_sys
do {tb_mips_sys_emac.wdo}
view wave
view structure
view signals
run 40 ms
## NOTE: Do not edit this file.
##
vlib work
# Configs
vcom -explicit -93 "../src/sdram_config_sim.vhd"
# Packages
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# RAMs
vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
# FIFOS
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
# CPU
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/bootloader.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
# UART
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
# PS2
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
# GPIO
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
# LCD
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
# Flash and USB
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
vcom -explicit -93 "../src/async_defs_sim.vhd"
# Sync SRAM
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
# AC-97
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
# Ethernet MAC
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
# Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd"
vsim -t 1ps -lib work tb_mips_sys
do {tb_mips_sys_emac.wdo}
view wave
view structure
view signals
run 40 ms
projects/mips_sys/sim/tb_mips_sys_emac.wdo
+185 -185
View File
@@ -1,185 +1,185 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
add wave -noupdate -format Literal /tb_mips_sys/dip
add wave -noupdate -format Literal /tb_mips_sys/btn
add wave -noupdate -format Literal /tb_mips_sys/led
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_dv
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_en
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_tx
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_gtx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_crs
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_col
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
add wave -noupdate -format Logic /tb_mips_sys/refresh
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/sys_error
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {Clock Gen}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
add wave -noupdate -divider {EMAC TX}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_out
add wave -noupdate -divider {EMAC RX}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_out
add wave -noupdate -divider {CPU Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
add wave -noupdate -divider {MIPS TOP}
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_addr
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_dout
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {2312967085 ps} 0} {{Cursor 100} {4871595869 ps} 0} {{Cursor 3} {4495154370 ps} 0} {{Cursor 7} {6077658830 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {41227735500 ps}
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
add wave -noupdate -format Literal /tb_mips_sys/dip
add wave -noupdate -format Literal /tb_mips_sys/btn
add wave -noupdate -format Literal /tb_mips_sys/led
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_dv
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_en
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_tx
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_gtx_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_crs
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_col
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
add wave -noupdate -format Logic /tb_mips_sys/refresh
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/sys_error
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -divider {Clock Gen}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
add wave -noupdate -divider Arbiter
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
add wave -noupdate -divider {EMAC TX}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_out
add wave -noupdate -divider {EMAC RX}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_out
add wave -noupdate -divider {CPU Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
add wave -noupdate -divider {MIPS TOP}
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_addr
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_dout
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {2312967085 ps} 0} {{Cursor 100} {4871595869 ps} 0} {{Cursor 3} {4495154370 ps} 0} {{Cursor 7} {6077658830 ps} 0}
configure wave -namecolwidth 187
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {41227735500 ps}
projects/mips_sys/tools/src/flashgen.c
+114 -114
View File
@@ -1,117 +1,117 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define INT8 char
#define INT16 short
#define INT32 long
#define UINT8 unsigned char
#define UINT16 unsigned short
#define UINT32 unsigned long
#define INT int
#define UINT unsigned int
#define FLOAT32 float
#define FLOAT64 double
#define SDRAM_BASE 0x40000000
#define FLASH_OFFSET 0x00000000
// --------------------------------------------------------------
typedef struct _sflash_img_hdr_t
{
UINT8 magic[4];
UINT32 target_addr;
UINT32 img_offset;
UINT32 img_size;
UINT32 hdr_next;
UINT8 img_name[128];
UINT8 res[108];
} flash_img_hdr_t;
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
// --------------------------------------------------------------
int main(int argc, char *argv[])
{
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define INT8 char
#define INT16 short
#define INT32 long
#define UINT8 unsigned char
#define UINT16 unsigned short
#define UINT32 unsigned long
#define INT int
#define UINT unsigned int
#define FLOAT32 float
#define FLOAT64 double
#define SDRAM_BASE 0x40000000
#define FLASH_OFFSET 0x00000000
// --------------------------------------------------------------
typedef struct _sflash_img_hdr_t
{
UINT8 magic[4];
UINT32 target_addr;
UINT32 img_offset;
UINT32 img_size;
UINT32 hdr_next;
UINT8 img_name[128];
UINT8 res[108];
} flash_img_hdr_t;
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
// --------------------------------------------------------------
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_flash[1024];
char name_prj[1024];
char name_prj[1024];
char *pBuf;
flash_img_hdr_t img_hdr = {0};
FILE *pFile;
int filesize;
long start, end;
int i;
if (argc < 2)
{
fprintf(stderr, "Usage: flashgen <input file>\n");
return 1;
}
pFilenameIn = argv[1];
pFile = fopen(pFilenameIn, "rb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
basename(pFilenameIn, name_prj);
sprintf(name_flash, "%s.flash.bin", name_prj);
// determine filesize
fseek(pFile, 0, SEEK_SET);
start = ftell(pFile);
fseek(pFile, 0, SEEK_END);
end = ftell(pFile);
fseek(pFile, 0, SEEK_SET);
filesize = (end-start);
pBuf = (char*)malloc(filesize);
fread(pBuf, 1, filesize, pFile);
fclose(pFile);
pFile = fopen(name_flash, "wb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", name_flash);
return 1;
}
img_hdr.magic[0] = 'J';
img_hdr.magic[1] = 'F';
img_hdr.magic[2] = 'I';
img_hdr.magic[3] = '1';
img_hdr.target_addr = SDRAM_BASE;
img_hdr.img_size = filesize;
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
img_hdr.hdr_next = FLASH_OFFSET;
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
fwrite(pBuf, 1, filesize, pFile);
fclose(pFile);
return 0;
}
flash_img_hdr_t img_hdr = {0};
FILE *pFile;
int filesize;
long start, end;
int i;
if (argc < 2)
{
fprintf(stderr, "Usage: flashgen <input file>\n");
return 1;
}
pFilenameIn = argv[1];
pFile = fopen(pFilenameIn, "rb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
basename(pFilenameIn, name_prj);
sprintf(name_flash, "%s.flash.bin", name_prj);
// determine filesize
fseek(pFile, 0, SEEK_SET);
start = ftell(pFile);
fseek(pFile, 0, SEEK_END);
end = ftell(pFile);
fseek(pFile, 0, SEEK_SET);
filesize = (end-start);
pBuf = (char*)malloc(filesize);
fread(pBuf, 1, filesize, pFile);
fclose(pFile);
pFile = fopen(name_flash, "wb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", name_flash);
return 1;
}
img_hdr.magic[0] = 'J';
img_hdr.magic[1] = 'F';
img_hdr.magic[2] = 'I';
img_hdr.magic[3] = '1';
img_hdr.target_addr = SDRAM_BASE;
img_hdr.img_size = filesize;
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
img_hdr.hdr_next = FLASH_OFFSET;
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
fwrite(pBuf, 1, filesize, pFile);
fclose(pFile);
return 0;
}
projects/mips_sys/tools/src/ramgen.c
+382 -382
View File
@@ -1,385 +1,385 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "ram"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 2\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "ram"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 2\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom_tcl[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
char name_rom_tcl[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
projects/mips_sys/tools/src/romgen.c
+365 -365
View File
@@ -1,368 +1,368 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "rom"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 1\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "rom"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 1\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
char name_rom_tcl[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
char name_rom[1024];
char name_rom_v4ld[1024];
char name_rom_tcl[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}