jens 4e66c8c1c8 - better reset values for pipe regs ...

- WB_stall is stall_all. More WB signal are stalled, may have functional impact or not

git-svn-id: http://moon:8086/svn/vhdl/trunk@1093 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-16 17:02:11 +00:00

..

ac97_ctrl

- commit local changes after CVS2SVN

2014-07-20 13:30:14 +00:00

CPUs

- better reset values for pipe regs

2015-05-16 17:02:11 +00:00

doc

- initial version

2015-02-07 06:35:28 +00:00

emac

- added dist

2015-02-07 06:38:44 +00:00

FIFO

- fixed missing signal

2015-05-16 15:06:18 +00:00

filter

- deleted

2014-07-25 06:47:31 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

- moved real_array_t and natural_array_t

2014-07-23 20:30:42 +00:00

fixed_ja

CRLF

2014-07-23 20:08:46 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

JBUS

- added

2014-07-24 06:31:44 +00:00

misc

- commit local changes after CVS2SVN

2014-07-20 13:30:14 +00:00

netlists

- initial version

2015-02-07 06:35:28 +00:00

PCK_FIO-1.16

Minor changes

2010-03-12 07:35:21 +00:00

PCK_FIO-2002.7

- commit local changes after CVS2SVN

2014-07-20 13:30:14 +00:00

ps2_port

- fixed rounding issue in usec prescaler

2010-02-09 11:46:08 +00:00

radio

- added

2014-07-24 06:47:53 +00:00

rams

- added

2015-05-14 16:14:15 +00:00

SDRAM

- uses now new generic DPRAMs

2013-02-09 10:45:59 +00:00

SSRAM

- added

2014-07-23 20:13:06 +00:00

Standard

- initial version

2015-02-07 06:35:28 +00:00

uart

[uart]

2015-05-14 10:59:18 +00:00

VGA_ctrl

- cleaned up

2013-05-12 17:03:18 +00:00

ChangeLog

- initial version

2015-02-07 06:35:28 +00:00