This commit was manufactured by cvs2svn to create tag 'MIPS_R11'.

git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R11@377 cc03376c-175c-47c8-b038-4cd826a8556b

Common/sim/compile_simprim.do

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+vlib simprim
+
+set XILINX C:/Programme/Xilinx101/ISE
+
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd

Common/sim/compile_unisim.do

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+vlib unisim
+
+set XILINX C:/Programme/Xilinx101/ISE
+
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vital.vhd

Common/ucf/ml402.ucf

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+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#     
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+# Bus clock nets
+NET "sys_clk"  TNM_NET = "sys_clk";
+NET "tft_clk"  TNM_NET = "tft_clk";
+NET sys_clk_in TNM_NET = "sys_clk_in";
+TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
+
+NET sys_clk_in LOC = AE14;
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET sys_rst_in LOC = D6;
+NET sys_rst_in PULLUP;
+NET sys_rst_in TIG;
+
+NET uart_RX LOC = W2;
+NET uart_RX IOSTANDARD = LVCMOS33;
+NET uart_RX TIG;
+NET uart_TX LOC = W1;
+NET uart_TX IOSTANDARD = LVCMOS33;
+NET uart_TX TIG;
+
+NET ext_irq TIG;
+
+# Reset timing ignore - treat as async paths
+NET sys_rst TIG;
+NET opb_v20_0_OPB_Rst TIG;
+NET lmb_v10_1_OPB_Rst TIG;
+NET lmb_v10_0_OPB_Rst TIG;
+NET opb_v20_0_Debug_SYS_Rst TIG;
+NET Debug_Rst TIG;
+NET plb_v34_0_PLB_Rst TIG;
+NET dcm_locked TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
+INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
+INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
+
+INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
+INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
+INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
+
+INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
+INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches 
+////////////////////////////////////////////////////////////////////////////
+
+# GPLED 0-3
+NET gpio<0>  LOC = G5;  #GPLED0
+NET gpio<1>  LOC = G6;  #GPLED1
+NET gpio<2>  LOC = A11; #GPLED2
+NET gpio<3>  LOC = A12; #GPLED3
+# North-East-South-West-Center LEDs
+NET gpio<4>  LOC = C6;  # C LED
+NET gpio<5>  LOC = F9;  # W LED
+NET gpio<6>  LOC = A5;  # S LED
+NET gpio<7>  LOC = E10; # E LED
+NET gpio<8>  LOC = E2;  # N LED
+# North-East-South-West-Center Buttons
+NET gpio<9>  LOC = B6;  # C Button
+NET gpio<10> LOC = E9;  # W Button
+NET gpio<11> LOC = A6;  # S Button
+NET gpio<12> LOC = F10; # E Button
+NET gpio<13> LOC = E7;  # N Button
+# Dip Switches 1-8
+NET gpio<14> LOC = U24; # DIP SW 8
+NET gpio<15> LOC = U25; # DIP SW 7
+NET gpio<16> LOC = V23; # DIP SW 6
+NET gpio<17> LOC = U23; # DIP SW 5
+NET gpio<18> LOC = U26; # DIP SW 4
+NET gpio<19> LOC = T26; # DIP SW 3
+NET gpio<20> LOC = R19; # DIP SW 2
+NET gpio<21> LOC = R20; # DIP SW 1
+NET gpio<14> IOSTANDARD = LVCMOS33;
+NET gpio<15> IOSTANDARD = LVCMOS33;
+NET gpio<16> IOSTANDARD = LVCMOS33;
+NET gpio<17> IOSTANDARD = LVCMOS33;
+NET gpio<18> IOSTANDARD = LVCMOS33;
+NET gpio<19> IOSTANDARD = LVCMOS33;
+NET gpio<20> IOSTANDARD = LVCMOS33;
+NET gpio<21> IOSTANDARD = LVCMOS33;
+#SMA Connectors
+NET gpio<22> LOC = C12; # SMA_IN_N
+NET gpio<23> LOC = C13; # SMA_IN_P
+NET gpio<24> LOC = D7;  # SMA_OUT_N
+NET gpio<25> LOC = D8;  # SMA_OUT_P
+NET gpio<26> LOC = AD12;# USERCLK
+NET gpio<26> IOSTANDARD = LVCMOS33;
+
+NET "gpio<*>" PULLDOWN;
+NET "gpio<*>" TIG;
+NET "gpio<*>" SLEW = SLOW;
+NET "gpio<*>" DRIVE = 2;
+
+NET "gpio<22>" SLEW = FAST;
+NET "gpio<22>" DRIVE = 12;
+NET "gpio<23>" SLEW = FAST;
+NET "gpio<23>" DRIVE = 12;
+NET "gpio<24>" SLEW = FAST;
+NET "gpio<24>" DRIVE = 12;
+NET "gpio<25>" SLEW = FAST;
+NET "gpio<25>" DRIVE = 12;
+
+NET  "gpio2_d_out<*>" TIG;
+NET  "gpio2_t_out<*>" TIG;
+NET  "gpio2_in<*>" TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for PS/2 Ports
+#------------------------------------------------------------------------------
+
+#Keyboard
+NET ps2_keyb_clk  LOC = D2;
+NET ps2_keyb_clk  SLEW = SLOW;
+NET ps2_keyb_clk  DRIVE = 2;
+NET ps2_keyb_clk  TIG;
+NET ps2_keyb_data LOC = G9;
+NET ps2_keyb_data SLEW = SLOW;
+NET ps2_keyb_data DRIVE = 2;
+NET ps2_keyb_data TIG;
+
+#Mouse
+NET ps2_mouse_clk  LOC = B14;
+NET ps2_mouse_clk  SLEW = SLOW;
+NET ps2_mouse_clk  DRIVE = 2;
+NET ps2_mouse_clk  TIG;
+NET ps2_mouse_data LOC = C14;
+NET ps2_mouse_data SLEW = SLOW;
+NET ps2_mouse_data DRIVE = 2;
+NET ps2_mouse_data TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for IIC Controller
+#------------------------------------------------------------------------------
+
+NET iic_scl    LOC = A17;
+NET iic_sda    LOC = B17;
+NET iic_scl    SLEW = SLOW;
+NET iic_scl    DRIVE = 6;
+NET iic_scl    TIG;
+NET iic_sda    SLEW = SLOW;
+NET iic_sda    DRIVE = 6;
+NET iic_sda    TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for AC97 Sound Controller
+#------------------------------------------------------------------------------
+
+NET ac97_bit_clk   LOC = AE10;
+NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
+NET ac97_bit_clk   PERIOD = 80;
+NET ac97_sdata_in  LOC = AD16;
+NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
+NET ac97_reset_n   LOC = AD10;
+NET ac97_reset_n   IOSTANDARD = LVCMOS33;
+NET ac97_reset_n   TIG;
+NET ac97_sdata_out LOC = C8;
+NET ac97_sync      LOC = D9;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for System ACE MPU / USB
+#------------------------------------------------------------------------------
+
+NET sysace_clk_in   LOC        = AF11;
+NET sysace_clk_in   IOSTANDARD = LVCMOS33;
+NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
+# Leave 1 ns margin
+TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
+
+NET sace_usb_a<0>   LOC        = U22;
+NET sace_usb_a<1>   LOC        = Y10;
+NET sace_usb_a<2>   LOC        = AA10;
+NET sace_usb_a<3>   LOC        = AC7;
+NET sace_usb_a<4>   LOC        = Y7;
+NET sace_usb_a<5>   LOC        = AA9;
+NET sace_usb_a<6>   LOC        = Y9;
+NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
+NET sace_usb_a<*>   SLEW       = FAST;
+NET sace_usb_a<*>   DRIVE      = 8;
+NET sace_mpce       LOC        = AD5;
+NET sace_mpce       IOSTANDARD = LVCMOS33;
+NET sace_mpce       SLEW       = FAST;
+NET sace_mpce       DRIVE      = 8;
+NET sace_usb_d<0>   LOC        = AB7;
+NET sace_usb_d<1>   LOC        = AC9;
+NET sace_usb_d<2>   LOC        = AB9;
+NET sace_usb_d<3>   LOC        = AE6;
+NET sace_usb_d<4>   LOC        = AD6;
+NET sace_usb_d<5>   LOC        = AF9;
+NET sace_usb_d<6>   LOC        = AE9;
+NET sace_usb_d<7>   LOC        = AD8;
+NET sace_usb_d<8>   LOC        = AC8;
+NET sace_usb_d<9>   LOC        = AF4;
+NET sace_usb_d<10>  LOC        = AE4;
+NET sace_usb_d<11>  LOC        = AD3;
+NET sace_usb_d<12>  LOC        = AC3;
+NET sace_usb_d<13>  LOC        = AF6;
+NET sace_usb_d<14>  LOC        = AF5;
+NET sace_usb_d<15>  LOC        = AA7;
+NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sace_usb_d<*>   SLEW       = FAST;
+NET sace_usb_d<*>   DRIVE      = 8;
+NET sace_usb_d<*>   PULLDOWN;
+NET sace_usb_oen    LOC        = AA8;
+NET sace_usb_oen    IOSTANDARD = LVCMOS33;
+NET sace_usb_oen    SLEW       = FAST;
+NET sace_usb_oen    DRIVE      = 8;
+NET sace_usb_wen    LOC        = Y8;
+NET sace_usb_wen    IOSTANDARD = LVCMOS33;
+NET sace_usb_wen    SLEW       = FAST;
+NET sace_usb_wen    DRIVE      = 8;
+NET sysace_mpirq    LOC        = AD4;
+NET sysace_mpirq    IOSTANDARD = LVCMOS33;
+NET sysace_mpirq    TIG;
+NET sysace_mpirq    PULLDOWN;
+
+NET usb_csn         LOC        = AF10;
+NET usb_csn         IOSTANDARD = LVCMOS33;
+NET usb_csn         SLEW       = FAST;
+NET usb_csn         DRIVE      = 8;
+NET usb_hpi_reset_n LOC        = A7;
+NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
+NET usb_hpi_reset_n TIG;
+NET usb_hpi_int     LOC        = V5;
+NET usb_hpi_int     IOSTANDARD = LVCMOS33;
+NET usb_hpi_int     TIG;
+NET usb_hpi_int     PULLDOWN;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET ddr_ad<0>  LOC = C26; # DDR_A0
+NET ddr_ad<1>  LOC = E17; # DDR_A1
+NET ddr_ad<2>  LOC = D18; # DDR_A2
+NET ddr_ad<3>  LOC = C19; # DDR_A3
+NET ddr_ad<4>  LOC = F17; # DDR_A4
+NET ddr_ad<5>  LOC = B18; # DDR_A5
+NET ddr_ad<6>  LOC = B20; # DDR_A6
+NET ddr_ad<7>  LOC = C20; # DDR_A7
+NET ddr_ad<8>  LOC = D20; # DDR_A8
+NET ddr_ad<9>  LOC = C21; # DDR_A9
+NET ddr_ad<10> LOC = A18; # DDR_A10
+NET ddr_ad<11> LOC = B21; # DDR_A11
+NET ddr_ad<12> LOC = A24; # DDR_A12
+NET ddr_ba<0>  LOC = B12; # DDR_BA0
+NET ddr_ba<1>  LOC = A16; # DDR_BA1
+NET ddr_casb   LOC = F23; # DDR_CAS_N
+NET ddr_cke    LOC = G22; # DDR_CKE
+NET ddr_csb    LOC = G21; # DDR_CS_N
+NET ddr_rasb   LOC = F24; # DDR_RAS_N
+NET ddr_web    LOC = A23; # DDR_WE_N
+
+NET ddr_clk    LOC = A10; # DDR_CK1_P
+NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET ddr_clkb   LOC = B10; # DDR_CK1_N
+
+NET ddr_dm<0>  LOC = G19; # DDR_DM0
+NET ddr_dm<1>  LOC = G24; # DDR_DM1
+NET ddr_dm<2>  LOC = G20; # DDR_DM2
+NET ddr_dm<3>  LOC = C22; # DDR_DM3
+
+NET ddr_dqs<0> LOC = D25; # DDR_DQS0
+NET ddr_dqs<1> LOC = G18; # DDR_DQS1
+NET ddr_dqs<2> LOC = G17; # DDR_DQS2
+NET ddr_dqs<3> LOC = D26; # DDR_DQS3
+
+NET ddr_dq<0> LOC = H20; # DDR_D0
+NET ddr_dq<1> LOC = E23; # DDR_D1
+NET ddr_dq<2> LOC = H26; # DDR_D2
+NET ddr_dq<3> LOC = H22; # DDR_D3
+NET ddr_dq<4> LOC = E25; # DDR_D4
+NET ddr_dq<5> LOC = E26; # DDR_D5
+NET ddr_dq<6> LOC = F26; # DDR_D6
+NET ddr_dq<7> LOC = E24; # DDR_D7
+NET ddr_dq<8> LOC = E20; # DDR_D8
+NET ddr_dq<9> LOC = A22; # DDR_D9
+NET ddr_dq<10> LOC = C23; # DDR_D10
+NET ddr_dq<11> LOC = C24; # DDR_D11
+NET ddr_dq<12> LOC = A20; # DDR_D12
+NET ddr_dq<13> LOC = A21; # DDR_D13
+NET ddr_dq<14> LOC = D24; # DDR_D14
+NET ddr_dq<15> LOC = E18; # DDR_D15
+NET ddr_dq<16> LOC = F18; # DDR_D16
+NET ddr_dq<17> LOC = A19; # DDR_D17
+NET ddr_dq<18> LOC = F19; # DDR_D18
+NET ddr_dq<19> LOC = B23; # DDR_D19
+NET ddr_dq<20> LOC = E21; # DDR_D20
+NET ddr_dq<21> LOC = D22; # DDR_D21
+NET ddr_dq<22> LOC = D23; # DDR_D22
+NET ddr_dq<23> LOC = B24; # DDR_D23
+NET ddr_dq<24> LOC = E22; # DDR_D24
+NET ddr_dq<25> LOC = F20; # DDR_D25
+NET ddr_dq<26> LOC = H23; # DDR_D26
+NET ddr_dq<27> LOC = G25; # DDR_D27
+NET ddr_dq<28> LOC = G26; # DDR_D28
+NET ddr_dq<29> LOC = H25; # DDR_D29
+NET ddr_dq<30> LOC = H24; # DDR_D30
+NET ddr_dq<31> LOC = H21; # DDR_D31
+
+NET ddr_ad<*>  IOSTANDARD = SSTL2_I;
+NET ddr_ba<*>  IOSTANDARD = SSTL2_I;
+NET ddr_casb   IOSTANDARD = SSTL2_I;
+NET ddr_cke    IOSTANDARD = SSTL2_I;
+NET ddr_clk    IOSTANDARD = SSTL2_I;
+NET ddr_clk_fb IOSTANDARD = LVCMOS25;
+NET ddr_clkb   IOSTANDARD = SSTL2_I;
+NET ddr_casb   IOSTANDARD = SSTL2_I;
+NET ddr_csb    IOSTANDARD = SSTL2_I;
+NET ddr_rasb   IOSTANDARD = SSTL2_I;
+NET ddr_web    IOSTANDARD = SSTL2_I;
+
+NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
+NET ddr_dm<*>  IOSTANDARD = SSTL2_II;
+NET ddr_dq<*>  IOSTANDARD = SSTL2_II;
+
+// Timing Constraint for DDR Feedback Clock
+NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
+TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
+#------------------------------------------------------------------------------
+
+NET tft_lcd_b<0> LOC = L26; # VGA_B2
+NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_b<1> LOC = C5;  # VGA_B3
+NET tft_lcd_b<2> LOC = C7;  # VGA_B4
+NET tft_lcd_b<3> LOC = B7;  # VGA_B5
+NET tft_lcd_b<4> LOC = G8;  # VGA_B6
+NET tft_lcd_b<5> LOC = F8;  # VGA_B7
+NET tft_lcd_b<*> SLEW = FAST;
+NET tft_lcd_b<*> DRIVE = 8;
+
+NET tft_lcd_clk  LOC = AF8;
+NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
+NET tft_lcd_clk  SLEW = FAST;
+NET tft_lcd_clk  DRIVE = 8;
+
+NET tft_lcd_g<0> LOC = M20; # VGA_G2
+NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_g<1> LOC = E4;  # VGA_G3
+NET tft_lcd_g<2> LOC = D3;  # VGA_G4
+NET tft_lcd_g<3> LOC = H7;  # VGA_G5
+NET tft_lcd_g<4> LOC = H8;  # VGA_G6
+NET tft_lcd_g<5> LOC = C1;  # VGA_G7
+NET tft_lcd_g<*> SLEW = FAST;
+NET tft_lcd_g<*> DRIVE = 8;
+
+NET tft_lcd_hsync LOC = C10;
+NET tft_lcd_hsync SLEW = FAST;
+NET tft_lcd_hsync DRIVE = 8;
+
+NET tft_lcd_r<0> LOC = N25; #VGA_R2
+NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_r<1> LOC = C2; #VGA_R3
+NET tft_lcd_r<2> LOC = G7; #VGA_R4
+NET tft_lcd_r<3> LOC = F7; #VGA_R5
+NET tft_lcd_r<4> LOC = E5; #VGA_R6
+NET tft_lcd_r<5> LOC = E6; #VGA_R7
+NET tft_lcd_r<*> SLEW = FAST;
+NET tft_lcd_r<*> DRIVE = 8;
+
+NET tft_lcd_vsync LOC = A8;
+NET tft_lcd_vsync SLEW = FAST;
+NET tft_lcd_vsync DRIVE = 8;
+
+TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
+TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET plb_error LOC = L24;
+NET plb_error IOSTANDARD = LVCMOS33;
+NET plb_error TIG;
+NET opb_error LOC = V6;
+NET opb_error IOSTANDARD = LVCMOS33;
+NET opb_error TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Ethernet
+#------------------------------------------------------------------------------
+
+NET phy_col        LOC = E3;
+NET phy_crs        LOC = D5;
+NET phy_dv         LOC = A9;
+NET phy_rx_clk     LOC = B15;
+NET phy_rx_data<3> LOC = C4;
+NET phy_rx_data<2> LOC = D4;
+NET phy_rx_data<1> LOC = E1;
+NET phy_rx_data<0> LOC = F1;
+
+NET phy_rx_er      LOC = B9;
+NET phy_tx_clk     LOC = C15;
+NET phy_mii_clk    LOC = D1;
+NET phy_mii_int_n  LOC = H4;
+NET phy_rst_n      LOC = D10;
+NET phy_tx_data<3> LOC = G1;
+NET phy_tx_data<2> LOC = H3;
+NET phy_tx_data<1> LOC = H2;
+NET phy_tx_data<0> LOC = H1;
+NET phy_tx_en      LOC = F4;
+NET phy_tx_er      LOC = F3;
+NET phy_mii_data   LOC = G4;
+
+NET phy_mii_int_n  PULLUP;
+
+NET phy_mii_int_n  TIG;
+NET phy_rst_n      TIG;
+
+# Timing Constraints (these are recommended in documentation and
+# are unaltered except for the TIG)
+NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
+NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
+TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
+TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
+
+NET "phy_tx_clk" MAXSKEW= 1.0 ns;
+NET "phy_rx_clk" MAXSKEW= 1.0 ns;
+NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
+NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
+
+NET "phy_rx_data<3>" IOBDELAY=NONE;
+NET "phy_rx_data<2>" IOBDELAY=NONE;
+NET "phy_rx_data<1>" IOBDELAY=NONE;
+NET "phy_rx_data<0>" IOBDELAY=NONE;
+NET "phy_dv" IOBDELAY=NONE;
+NET "phy_rx_er" IOBDELAY=NONE;
+NET "phy_crs" IOBDELAY=NONE;
+NET "phy_col" IOBDELAY=NONE;
+
+# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/DVD_FF"   IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RER_FF"   IOB=FALSE;
+
+# Timing ignores (to specify unconstrained paths)
+TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
+TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
+TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
+TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for SRAM/FLASH
+#------------------------------------------------------------------------------
+
+NET sram_clk            LOC = AF7;
+NET sram_clk_fb         LOC = AD17;
+NET flash_a23           LOC = T21;
+NET sram_flash_addr<22> LOC = U20;
+NET sram_flash_addr<21> LOC = T19;
+NET sram_flash_addr<20> LOC = AC5;
+NET sram_flash_addr<19> LOC = AB5;
+NET sram_flash_addr<18> LOC = AC4;
+NET sram_flash_addr<17> LOC = AB4;
+
+NET sram_flash_addr<16> LOC = AB3;
+NET sram_flash_addr<15> LOC = AA4;
+NET sram_flash_addr<14> LOC = AA3;
+NET sram_flash_addr<13> LOC = W5;
+NET sram_flash_addr<12> LOC = W6;
+NET sram_flash_addr<11> LOC = W3;
+NET sram_flash_addr<10> LOC = AF3;
+NET sram_flash_addr<9>  LOC = AE3;
+NET sram_flash_addr<8>  LOC = AD2;
+NET sram_flash_addr<7>  LOC = AD1;
+NET sram_flash_addr<6>  LOC = AC2;
+NET sram_flash_addr<5>  LOC = AC1;
+NET sram_flash_addr<4>  LOC = AB2;
+NET sram_flash_addr<3>  LOC = AB1;
+NET sram_flash_addr<2>  LOC = AA1;
+NET sram_flash_addr<1>  LOC = Y2;
+NET sram_flash_addr<0>  LOC = Y1;
+NET sram_flash_data<31> LOC = F14;
+NET sram_flash_data<30> LOC = F13;
+NET sram_flash_data<29> LOC = F12;
+NET sram_flash_data<28> LOC = F11;
+NET sram_flash_data<27> LOC = F16;
+NET sram_flash_data<26> LOC = F15;
+NET sram_flash_data<25> LOC = D14;
+NET sram_flash_data<24> LOC = D13;
+NET sram_flash_data<23> LOC = D15;
+NET sram_flash_data<22> LOC = E14;
+NET sram_flash_data<21> LOC = C11;
+NET sram_flash_data<20> LOC = D11;
+NET sram_flash_data<19> LOC = D16;
+NET sram_flash_data<18> LOC = C16;
+NET sram_flash_data<17> LOC = E13;
+NET sram_flash_data<16> LOC = D12;
+NET sram_flash_data<15> LOC = AA14;
+NET sram_flash_data<14> LOC = AB14;
+NET sram_flash_data<13> LOC = AC12;
+NET sram_flash_data<12> LOC = AC11;
+NET sram_flash_data<11> LOC = AA16;
+NET sram_flash_data<10> LOC = AA15;
+NET sram_flash_data<9>  LOC = AB13;
+NET sram_flash_data<8>  LOC = AA13;
+NET sram_flash_data<7>  LOC = AC14;
+NET sram_flash_data<6>  LOC = AD14;
+NET sram_flash_data<5>  LOC = AA12;
+NET sram_flash_data<4>  LOC = AA11;
+NET sram_flash_data<3>  LOC = AC16;
+NET sram_flash_data<2>  LOC = AC15;
+NET sram_flash_data<1>  LOC = AC13;
+NET sram_flash_data<0>  LOC = AD13;
+NET sram_cen            LOC = V7;
+NET sram_flash_oe_n     LOC = AC6;
+NET sram_flash_we_n     LOC = AB6;
+NET sram_bw<3>          LOC = Y3; #Y4; 
+NET sram_bw<2>          LOC = Y4; #Y3;
+NET sram_bw<1>          LOC = Y5; #Y6;
+NET sram_bw<0>          LOC = Y6; #Y5;
+NET flash_ce            LOC = W7;
+NET sram_adv_ld_n       LOC = W4;
+NET sram_mode           LOC = V26;
+
+NET sram_clk           IOSTANDARD = LVCMOS33;
+NET sram_clk           DRIVE = 16;
+NET sram_clk           SLEW = FAST;
+NET sram_clk_fb        IOSTANDARD = LVCMOS33;
+
+NET flash_a23          IOSTANDARD = LVDCI_33;
+NET flash_a23  SLEW = FAST;
+NET flash_a23  DRIVE = 8;
+
+NET sram_mode          IOSTANDARD = LVDCI_33;
+NET sram_mode SLEW = FAST;
+NET sram_mode DRIVE = 8;
+
+NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
+NET sram_flash_addr<*>  SLEW = FAST;
+NET sram_flash_addr<*>  DRIVE = 8;
+
+NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
+NET sram_flash_data<*> DRIVE = 12;
+NET sram_flash_data<*> SLEW = FAST;
+NET sram_flash_data<*> PULLDOWN;
+
+NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
+NET sram_flash_oe_n SLEW = FAST;
+NET sram_flash_oe_n DRIVE = 8;
+
+NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
+NET sram_flash_we_n SLEW = FAST;
+NET sram_flash_we_n DRIVE = 8;
+
+NET sram_bw<*>         IOSTANDARD = LVDCI_33;
+NET sram_bw<*> SLEW = FAST;
+NET sram_bw<*> DRIVE = 8;
+
+NET flash_ce           IOSTANDARD = LVDCI_33;
+NET flash_ce SLEW = FAST;
+NET flash_ce DRIVE = 8;
+
+NET sram_cen           IOSTANDARD = LVDCI_33;
+NET sram_cen SLEW = FAST;
+NET sram_cen DRIVE = 8;
+
+NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
+NET sram_adv_ld_n SLEW = FAST;
+NET sram_adv_ld_n DRIVE = 8;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Expansion Header GPIO
+#------------------------------------------------------------------------------
+
+NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
+NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
+NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
+NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
+NET gpio_exp_hdr1<27> LOC = W20;  # HDR1_44
+NET gpio_exp_hdr1<26> LOC = W21;  # HDR1_48
+NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
+NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
+NET gpio_exp_hdr1<23> LOC = W22;  # HDR1_46
+NET gpio_exp_hdr1<22> LOC = V21;  # HDR1_56
+NET gpio_exp_hdr1<21> LOC = V22;  # HDR1_54
+NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
+NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
+NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
+NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
+NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
+NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
+NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
+NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
+NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
+NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
+NET gpio_exp_hdr1<10> LOC = Y25;  # HDR1_40
+NET gpio_exp_hdr1<9>  LOC = Y26;  # HDR1_38
+NET gpio_exp_hdr1<8>  LOC = W26;  # HDR1_50
+NET gpio_exp_hdr1<7>  LOC = AB23; # HDR1_12
+NET gpio_exp_hdr1<6>  LOC = Y24;  # HDR1_26
+NET gpio_exp_hdr1<5>  LOC = AB24; # HDR1_32
+NET gpio_exp_hdr1<4>  LOC = W25;  # HDR1_52
+NET gpio_exp_hdr1<3>  LOC = AC24; # HDR1_2
+NET gpio_exp_hdr1<2>  LOC = AC25; # HDR1_36
+NET gpio_exp_hdr1<1>  LOC = V20;  # HDR1_42
+NET gpio_exp_hdr1<0>  LOC = AA24; # HDR1_28
+NET gpio_exp_hdr1<*> TIG;
+NET gpio_exp_hdr1<*> PULLDOWN;
+
+NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
+NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
+NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
+NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
+NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
+NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
+NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
+NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
+NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
+NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
+NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
+NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
+NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
+NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
+NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
+NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
+NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
+NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
+NET gpio_exp_hdr2<13> LOC = Y17;  # HDR2_56
+NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
+NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
+NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
+NET gpio_exp_hdr2<9>  LOC = Y22;  # HDR2_8
+NET gpio_exp_hdr2<8>  LOC = Y23;  # HDR2_6
+NET gpio_exp_hdr2<7>  LOC = W23;  # HDR2_12
+NET gpio_exp_hdr2<6>  LOC = W24;  # HDR2_10
+NET gpio_exp_hdr2<5>  LOC = Y20;  # HDR2_20
+NET gpio_exp_hdr2<4>  LOC = Y21;  # HDR2_18
+NET gpio_exp_hdr2<3>  LOC = Y19;  # HDR2_28
+NET gpio_exp_hdr2<2>  LOC = W19;  # HDR2_26
+NET gpio_exp_hdr2<1>  LOC = AA18; # HDR2_4
+NET gpio_exp_hdr2<0>  LOC = Y18;  # HDR2_2
+NET gpio_exp_hdr2<*> TIG;
+NET gpio_exp_hdr2<*> PULLDOWN;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Character LCD GPIO
+#------------------------------------------------------------------------------
+
+NET gpio_char_lcd<6> LOC = AE13; # LCD_E
+NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
+NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
+NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
+NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
+NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
+NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
+NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
+NET gpio_char_lcd<*> TIG;
+NET gpio_char_lcd<*> PULLDOWN;

lib/CPUs/JCpu/src/core/chipreg.vhd

@@ -68,19 +68,13 @@ proc_reg_write:
 			reg_cmem_high <= (others => '0');
 			reg_bank_sel <= (others => '0');
 			reg_int_ctrl.enable		<= '0';
-			reg_int_ctrl.polarity	<= '1';
-			reg_int_ctrl.edge_sens	<= '1';
 		elsif rising_edge(clk) then
-			reg_int_ctrl.request <= '0';
 			if we = '1' then
 				case addr is
 				when X"01" =>
 					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
 				when X"03" =>
 					reg_int_ctrl.enable		<= din(0);
-					reg_int_ctrl.polarity	<= din(1);
-					reg_int_ctrl.edge_sens	<= din(2);
-					reg_int_ctrl.request	<= din(7);
 				when X"04" =>
 					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
 				when X"05" =>
@@ -103,7 +97,7 @@ proc_reg_read:
 			when X"02" =>	-- CPU status
 				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
 			when X"03" =>	-- Interrupt control
-				dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
+				dout <= "0000000" & reg_int_ctrl.enable;
 			when X"04" =>	-- Upper stack bits out
 				dout <= "0000" & reg_cmem_high;
 			when X"05" =>	-- Upper cmem bits out

lib/CPUs/JCpu/src/core/cpu.vhd

@@ -39,7 +39,6 @@ entity cpu is
 		ce			: in  STD_LOGIC;
 		int_in		: in  STD_LOGIC;
 		int_ack		: out STD_LOGIC;
-		xmem_wait	: in  STD_LOGIC;
 		xmem_we		: out STD_LOGIC;
 		xmem_re		: out STD_LOGIC;
 		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
@@ -215,7 +214,6 @@ begin
 	pc_inc <= cpu_active and ctrl.lines.pc_inc;
 	stk_addr <= '0' & stk_ptr;
 	cpu_status.alu <= alu_status;
-	cpu_status.xmem_wait <= xmem_wait;
 	creg_ctrl_in.alu <= alu_status;
 
 	xmem_dout <= mem_data;

lib/CPUs/JCpu/src/core/cpu_pkg.vhd

@@ -49,7 +49,7 @@ package cpu_pkg is
 	constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
 
 	-- Microcode ROM
-	constant MUCODE_ADDR_WIDTH : integer := 10;
+	constant MUCODE_ADDR_WIDTH : integer := 9;
 	
 	-- Stack depth (uses lower half of CHIPRAM)
 	constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
@@ -100,7 +100,6 @@ package cpu_pkg is
 
 	type cpu_status_t is record
 		alu			: alu_status_t;
-		xmem_wait	: STD_LOGIC;
 	end record;
 
 	type ctrl_lines_t is record
@@ -133,9 +132,6 @@ package cpu_pkg is
 	
 	type int_ctrl_in_t is record
 		enable			: std_logic;
-		polarity		: std_logic;
-		edge_sens		: std_logic;
-		request			: std_logic;
 	end record;
 	
 	type creg_ctrl_out_t is record
@@ -334,12 +330,11 @@ package body cpu_pkg is
 
 	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
 	variable result : ctrl_lines_t;
-	variable ze, cy, xmem_wait : STD_LOGIC;
+	variable ze, cy : STD_LOGIC;
 	
 	begin
 		ze			:= status.alu.zero;
 		cy			:= status.alu.carry;
-		xmem_wait	:= status.xmem_wait;
 		
 		result := ctrl_lines_default;
 		if iphase = 0 then
@@ -435,10 +430,6 @@ package body cpu_pkg is
 			if iphase = 0 then
 				result.mem_write := '1';
 			end if;
-			if xmem_wait = '1' then
-				result.mem_write := '1';
-				result.pc_inc := '0';
-			end if;
 		when "MOVX|Ri|K   " => -- [R(a)] <= kk
 			result.mem_access := xmem_access;
 			result.daddr_src_sel := reg_a;
@@ -446,10 +437,6 @@ package body cpu_pkg is
 			if iphase = 0 then
 				result.mem_write := '1';
 			end if;
-			if xmem_wait = '1' then
-				result.mem_write := '1';
-				result.pc_inc := '0';
-			end if;
 		when "XOUT|Ri|K   " => -- [R(a)] <= kk
 			result.mem_access := xio_access;
 			result.daddr_src_sel := reg_a;
@@ -457,55 +444,33 @@ package body cpu_pkg is
 			if iphase = 0 then
 				result.mem_write := '1';
 			end if;
-			if xmem_wait = '1' then
-				result.pc_inc := '0';
-				result.mem_write := '1';
-			end if;
 		when "MOVX|R|Ri   " => -- R(a) <= [R(b)]
 			result.mem_access := xmem_access;
 			result.reg_src_sel := xmem_src;
 			result.daddr_src_sel := reg_b;
 			if iphase = 0 then
 				result.mem_read := '1';
-			end if;
+			elsif iphase = 1 then
-			if xmem_wait = '0' then
-				if iphase = 1 then
 					result.reg_we := '1';
 				end if;
-			else
-				result.pc_inc := '0';
-				result.mem_read := '1';
-			end if;
 		when "MOVX|R|Ki   " => -- R(a) <= [#addr]
 			result.mem_access := xmem_access;
 			result.reg_src_sel := xmem_src;
 			result.daddr_src_sel := const;
 			if iphase = 0 then
 				result.mem_read := '1';
-			end if;
+			elsif iphase = 1 then
-			if xmem_wait = '0' then
-				if iphase = 1 then
 					result.reg_we := '1';
 				end if;
-			else
-				result.pc_inc := '0';
-				result.mem_read := '1';
-			end if;
 		when "XIN|R|Ki    " => -- R(a) <= [#addr]
 			result.mem_access := xio_access;
 			result.reg_src_sel := xmem_src;
 			result.daddr_src_sel := const;
 			if iphase = 0 then
 				result.mem_read := '1';
-			end if;
+			elsif iphase = 1 then
-			if xmem_wait = '0' then
-				if iphase = 1 then
 					result.reg_we := '1';
 				end if;
-			else
-				result.pc_inc := '0';
-				result.mem_read := '1';
-			end if;
 		when "MOVX|Ki|R   " => -- [#addr] <= R(a)
 			result.mem_access := xmem_access;
 			result.daddr_src_sel := const;
@@ -513,10 +478,6 @@ package body cpu_pkg is
 			if iphase = 0 then
 				result.mem_write := '1';
 			end if;
-			if xmem_wait = '1' then
-				result.pc_inc := '0';
-				result.mem_write := '1';
-			end if;
 		when "XOUT|Ki|R   " => -- [#addr] <= R(a)
 			result.mem_access := xio_access;
 			result.daddr_src_sel := const;
@@ -524,10 +485,6 @@ package body cpu_pkg is
 			if iphase = 0 then
 				result.mem_write := '1';
 			end if;
-			if xmem_wait = '1' then
-				result.pc_inc := '0';
-				result.mem_write := '1';
-			end if;
 		when "ADD|R|R     " => -- R(a) <= R(a) + R(b)
 			result.alu_opsel := op1_add_op2;
 			result.alu_op1_src_sel := reg_a;
@@ -855,8 +812,6 @@ package body cpu_pkg is
 			status.alu.zero := addr(pos);
 			pos := pos + 1;
 			status.alu.carry := addr(pos);
-			pos := pos + 1;
-			status.xmem_wait := addr(pos);
 			
 			result(i) := idecoder(opcode, iphase, status);
 		end loop;
@@ -867,7 +822,7 @@ package body cpu_pkg is
 	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
 	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
 	begin
-		addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
+		addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
 		return addr;
 		
 	end get_muromaddr;

lib/CPUs/JCpu/src/core/int_ctrl.vhd

@@ -48,13 +48,11 @@ end int_ctrl;
 architecture Behavioral of int_ctrl is
 
 	type int_state_t is (int_idle, int_inject, int_active, int_release);
-	type pin_state_t is (pin_s0, pin_s1, pin_s2);
 	
 	signal int_state, int_state_next : int_state_t;
-	signal pin_state, pin_state_next : pin_state_t;
 	signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
 	signal int_request : std_logic;
-	signal int_sampled : std_logic;
+	
 	
 begin
 
@@ -74,7 +72,6 @@ irg_ctrl_fsm:
 		pc_load <= '0';
 		stk_push <= '0';
 		stk_pop <= '0';
-
 		case int_state is
 		
 		when int_idle =>
@@ -121,47 +118,11 @@ pin_sample:
 	process (clk)
 	begin
 		if rising_edge(clk) then
-			int_sampled <= int_in xor (not ctrl_in.polarity);
-		end if;
-	end process;
-
------------------------------------------------------------------------
-pin_fsm:
-	process (pin_state, int_sampled, int_ack, ctrl_in)
-	begin
 			int_request <= '0';
-		pin_state_next <= pin_state;
-		case pin_state is
-			when pin_s0 => 
-				if int_sampled = '1' or ctrl_in.request = '1' then
 			if ctrl_in.enable = '1' then
-						pin_state_next <= pin_s1;
+				int_request <= int_in;
 			end if;	
 		end if;
-			when pin_s1 => 
-				int_request <= '1';
-				if int_ack = '1' then
-					pin_state_next <= pin_s2;
-				end if;	
-			when pin_s2 =>
-				if ctrl_in.edge_sens = '0' then
-					pin_state_next <= pin_s0;
-				elsif int_sampled = '0'	then
-					pin_state_next <= pin_s0;
-				end if;
-			when others =>
-				pin_state_next <= pin_s0;
-			end case;	
-	end process;
-			
-pin_states:
-	process (rst, clk, pin_state_next)
-	begin
-		if rst = '1' then
-			pin_state <= pin_s0;
-		elsif rising_edge(clk) then
-			pin_state <= pin_state_next;
-		end if;
 	end process;
 
 -----------------------------------------------------------------------

lib/CPUs/MIPS/bsp/examples/Makefile

@@ -1,8 +1,6 @@
-TOOLS_DIR=../../tools
-
 CFLAGS=-msoft-float -O2 -march=r3000 -I.
 LFLAGS=-M -T link.ld
-LIB_DIRS=-L . -L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
+LIB_DIRS=-L . -L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)
 LIBS=-lc -lm -lgcc
 
 AS=mipsel-elf-as
@@ -11,9 +9,9 @@ CC=mipsel-elf-gcc
 LD=mipsel-elf-ld
 OBJDUMP=mipsel-elf-objdump
 OBJCOPY=mipsel-elf-objcopy
-FLASHGEN=$(TOOLS_DIR)/flashgen_little
+FLASHGEN=flashgen_el
 
-PROG = hello testbench test_irq dhry queens stanford paranoia rmd160_test Bessel whet phrasen dttl richards_benchmark
+PROG = hello testbench test_irq dhry queens stanford paranoia rmd160_test Bessel whet phrasen dttl richards_benchmark test_exception
 
 all: $(PROG)
 
@@ -130,5 +128,13 @@ richards_benchmark: richards_benchmark.c
 	$(OBJCOPY) -O srec $@.elf $@.srec
 	$(FLASHGEN) $@.bin
 
+test_exception: test_exception.c 
+	$(CC) $(CFLAGS) -O1 -c test_exception.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) test_exception.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
 clean:
 	rm -rf *.a *.o *.bin *.map *.dis *.srec *.elf $(PROG) > /dev/null

lib/CPUs/MIPS/bsp/examples/bootloader/Makefile

@@ -1,9 +1,8 @@
 ROM_WORDADDR_WIDTH=11
-TOOLS_DIR=../../../tools
 
 CFLAGS=-Os -I. -I../ -msoft-float -march=r3000
 LFLAGS=-M -T bootloader.ld
-LIB_DIRS=-L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
+LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)
 LIBS=-lc -lgcc
 
 CC=mipsel-elf-gcc
@@ -25,7 +24,7 @@ bootloader: libsys bootloader.c
 	$(OBJDUMP) -d bootloader.elf > bootloader.dis
 	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
 	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	$(TOOLS_DIR)/romgen bootloader.ROM.bin 10
+	romgen bootloader.ROM.bin 10
 
 bootloader_flash: libsys bootloader_with_flash.c 
 	$(CC) $(CFLAGS) -g -c bootloader_with_flash.c
@@ -34,7 +33,7 @@ bootloader_flash: libsys bootloader_with_flash.c
 	$(OBJDUMP) -d bootloader.elf > bootloader.dis
 	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
 	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	$(TOOLS_DIR)/romgen bootloader.ROM.bin 11
+	romgen bootloader.ROM.bin 11
 
 clean:
 	rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld

@@ -1,9 +1,10 @@
 MEMORY
 {
   rom          : ORIGIN = 0xBFC00000, LENGTH = 0x00002000  /*   8K    */
+  ram          : ORIGIN = 0x40000000, LENGTH = 0x00002000  /*   8K    */
 }
 
-stack_ptr = 0x7FFFFFF0;
+stack_ptr = 0x7FFFEFF0;
 baudrate = 0x0D;
 sys_led_port = 0xA0000000;
 sys_uart_data = 0xA0010000;
@@ -39,4 +40,9 @@ SECTIONS
      *(.rodata*)
    }  > rom
 
+   .data ORIGIN(ram) :
+   {
+     *(.*data) *(.*bss) *(.*common)
+   }  > ram
+
 }

lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S

@@ -15,7 +15,7 @@ _init:
 
 		# set stack pointer 
 		la $sp, stack_ptr
-#		j	$jmain
+		j	$jmain
 		
 		# TEST
 		li	$26, +5

lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S

@@ -20,10 +20,11 @@ _exc_handler:
 		# Set Error LED and ExcCode LEDs
 		# Get Cause
 		mfc0	$26, $13
-		la 		$27, sys_led_port
+		li 		$27, 0xC0000000
 		srl		$26, 2
 		andi	$26, 0x000F
 		or 		$26, $27
+		la 		$27, sys_led_port
 		sw 		$26, 0($27)
 
 		# wait for all interrupts = 0

lib/CPUs/MIPS/bsp/examples/hello.c

@@ -13,6 +13,7 @@ int main (void)
 
 	*pGPIO0 = 0xAAAAAAAA;
 	*pGPIO1 = 0xAAAAAAAA;
+
 	return 0;
 }
 

lib/CPUs/MIPS/bsp/examples/init.S

@@ -9,9 +9,9 @@ _init:
 		.set	noreorder
 
 		# set uart
-		la	$8, sys_uart_baud
+#		la	$8, sys_uart_baud
-		addiu	$9, $0, baudrate
+#		addiu	$9, $0, baudrate
-		sb	$9, 0($8)
+#		sb	$9, 0($8)
 		
 		# set stack pointer 
 		la $sp, stack_ptr
@@ -34,12 +34,14 @@ $zeroise:
 #		addiu	$8, 4
 
 		# jump main
-		la $8, main
+		la $t0, main
-		jalr $8
+		jalr $t0
+		nop
 
 _terminate:	
 		nop
-		j		_terminate
+		la $t0, exit
-		nop
+		jalr $t0
+		move $a0, $v0
 		
 		.set	reorder

lib/CPUs/MIPS/bsp/examples/libsys.c

@@ -3,6 +3,7 @@
 #include <sys/resource.h>
 #include <sys/stat.h>
 #include <errno.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include "libsys.h"
 
@@ -150,9 +151,8 @@ void _cg_putchar(char c)
 
 void _exit (int exitcode)
 {
-	sputs("_exit(");
+	fflush(stdout);
-	print_word(exitcode);
+	fflush(stderr);
-	sputs(")\n");
 	while(1);
 }
 
@@ -239,29 +239,31 @@ int settimeofday(const struct timeval *tp, const struct timezone *tzp)
 caddr_t sbrk(int incr)
 {
 	extern char end;
+	extern char stack_ptr;
 	static char *heap_end;
 	char *prev_heap_end;
 
 	if (heap_end == 0)
+	{
 		heap_end = &end;
+	}
 
 	prev_heap_end = heap_end;
-//	if (heap_end + incr > stack_ptr)
+	if (heap_end + incr > &stack_ptr)
-//	{
+	{
-//		sputs("Heap and stack collision\r\n");
+//		sputs("Heap and stack collision\n");
-//		abort();
+//		sputs("Stack Ptr = ");print_word(&stack_ptr);sputs("\n");
-//	}
+//		sputs("Heap end  = ");print_word(heap_end);sputs("\n");
-
+//		sputs("Increment = ");print_word(incr);sputs("\n");
-//	sputs("\n");
+		exit(1);
-//	print_word((int)prev_heap_end);
+	}
-//	sputs("\n");
 	heap_end += incr;
 	return (caddr_t) prev_heap_end;
 }
 
 int fstat(int file, struct stat *st)
 {
-//	sputs("Fstat()\n");
+//	sputs("fstat\n");
 	st->st_mode = S_IFCHR;
 	st->st_blksize = 0;
 	return 0;
@@ -269,41 +271,49 @@ int fstat(int file, struct stat *st)
 
 int lseek(int file, int ptr, int dir)
 {
-	sputs("Lseek()\n");
+//	sputs("lseek\n");
-
 	errno = ESPIPE;
 	return -1;
 }
 
 int open(const char *name, int flags, int mode)
 {
-	sputs("Open()\n");
+//	sputs("open\n");
 	errno = EIO;
 	return -1;
 }
 
 int close(int file)
 {
-	sputs("Close()\n");
+//	sputs("close\n");
 	return 0;
 }
 
 int read(int file, char *ptr, int len)
 {
 	int i;
+	char c;
 
-//	sputs("Read()\n");
+//	sputs("read\n");
-	for (i = 0; i < len; i++)
+	i = 0;
+	while (i < len)
 	{
-		ptr[i] = readchar();
+		c = readchar();
-		if ((ptr[i] == '\n') || (ptr[i] == '\r'))
+		if ((c == 0x0D) || (c == 0x0A))
 		{
-			i++;
 			writechar(0x0D);
 			writechar(0x0A);
+			if (i==0)
+				continue;
+
+			ptr[i++] = c;
 			break;
 		}
-		writechar(ptr[i]);
+		else
+		{
+			ptr[i++] = c;
+			writechar(c);
+		}
 	}
 	return i;
 }

lib/CPUs/MIPS/bsp/examples/libsys.h

@@ -51,8 +51,12 @@
 //#define STDOUT_FUNCTION	_cg_putchar		// Video character
 //#define STDERR_FUNCTION	_putchar		// Serial output
 
+#ifndef STDOUT_FUNCTION
 #define STDOUT_FUNCTION	_putchar		// Serial output
+#endif
+#ifndef STDERR_FUNCTION
 #define STDERR_FUNCTION	_putchar		// Serial output
+#endif
 
 UINT32 CP0_SR_read(void);
 void CP0_SR_write(UINT32 val);

lib/CPUs/MIPS/bsp/examples/test_exception.c

@@ -0,0 +1,232 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "libsys.h"
+
+void _exc_break(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		"break 0x123\n"
+		".set	reorder\n"
+
+	);
+}
+
+void _exc_syscall(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		"syscall\n"
+		".set	reorder\n"
+
+	);
+}
+
+void _exc_arith(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t0, 0x7FFFFFFF\n"
+		" addi  $t1, $t0, 2\n"
+		".set	reorder\n"
+
+	);
+}
+
+void _exc_store_err(void)
+{
+	volatile int *pSrc = (int*)sys_timer_sec;
+	volatile int *pDst = (int*)0x40000001;
+
+	*pDst = *pSrc;
+
+}
+
+void _exc_load_err(void)
+{
+	volatile int *pSrc = (int*)0x40000002;
+	volatile int *pDst = (int*)sys_led_port;
+
+	*pDst = *pSrc;
+
+}
+
+void _exc_kaddr_err(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t0, 0x80000000\n"
+		" jr    $t0\n"
+		"nop\n"
+		".set	reorder\n"
+
+	);
+
+}
+
+void _exc_iaddr_err(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t0, 0x80000003\n"
+		" jr    $t0\n"
+		"nop\n"
+		".set	reorder\n"
+
+	);
+
+}
+
+void _exc_ri(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t0, 0x40010000\n"
+		" li	$t1, 0x9c563442\n"
+		" sw	$t1, 0($t0)\n"
+		" jr    $t0\n"
+		"nop\n"
+		".set	reorder\n"
+
+	);
+
+}
+
+void _exc_ibe(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t1, 0xAc563440\n"
+		" jr    $t1\n"
+		"nop\n"
+		".set	reorder\n"
+
+	);
+
+}
+
+void _exc_dbe(void)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		" li	$t1, 0xAc563440\n"
+		" lw	$t0, 0($t1)\n"
+		"nop\n"
+		" jr    $t0\n"
+		"nop\n"
+		".set	reorder\n"
+
+	);
+
+}
+
+void handler0(void)
+{
+	printf("Interrupt 0\n");
+	interrupt_clr(0);
+}
+
+void handler1(void)
+{
+	printf("Interrupt 1\n");
+	interrupt_clr(1);
+}
+
+int main(void)
+{
+	int buf[256];
+	volatile int *pLED = (int*)sys_led_port;
+	volatile int *pFlash = (int*)sys_flash_io;
+	int i, sel;
+
+	interrupt_register(0, handler0);
+	interrupt_enable(0);
+	interrupt_register(1, handler1);
+	interrupt_enable(1);
+
+	for (i=0; i < 8192; i++)
+		*pLED = *pFlash;
+
+	while(1)
+	{
+		printf("Welche exception möchten Sie testen?\n");
+		printf(" 1 : Reserved instruction\n");
+		printf(" 2 : Privileged address\n");
+		printf(" 3 : Arithmetic overflow\n");
+		printf(" 4 : Syscall\n");
+		printf(" 5 : Breakpoint\n");
+		printf(" 6 : Load error on instruction\n");
+		printf(" 7 : Load error on data\n");
+		printf(" 8 : Store error on data\n");
+		printf(" 9 : Bus error on instruction\n");
+		printf("10 : Bus error on data\n");
+		printf("11 : SW-interrupt 0\n");
+		printf("12 : SW-interrupt 1\n");
+
+		scanf("%d", &sel);
+		printf("Jetzt kommt die exception (%d)!\n", sel);
+
+		switch(sel)
+		{
+			case 1:
+			_exc_ri();
+			break;
+
+			case 2:
+			_exc_kaddr_err();
+			break;
+
+			case 3:
+			_exc_arith();
+			break;
+
+			case 4:
+			_exc_syscall();
+			break;
+
+			case 5:
+			_exc_break();
+			break;
+
+			case 6:
+			_exc_iaddr_err();
+			break;
+
+			case 7:
+			_exc_load_err();
+			break;
+
+			case 8:
+			_exc_store_err();
+			break;
+
+			case 9:
+			printf("IBE: Exception not implemented in current CPU!\nPush reset to restart!\n");
+			_exc_ibe();
+			break;
+
+			case 10:
+			printf("DBE: Exception not implemented in current CPU!\nPush reset to restart!\n");
+			_exc_dbe();
+			break;
+
+			case 11:
+			case 12:
+			interrupt_set(sel-11);
+			break;
+
+			default:
+			break;
+		}
+		sel = 0;
+	}
+	return 0;
+}

lib/CPUs/MIPS/bsp/examples/testbench.c

@@ -3,6 +3,8 @@
 #include <string.h>
 #include <math.h>
 #include <time.h>
+#include <sys/times.h>
+#include <sys/time.h>
 #include "libsys.h"
 
 #define	NO_ERROR		0x00000000
@@ -22,11 +24,14 @@ void handler3(void)
 {
 	volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat;
 	volatile UINT32 *pUART_data = (UINT32*)sys_uart_data;
+	volatile UINT32 *pLED = (UINT32*)sys_led_port;
 
 	while((0x10 & *pUART_stat))
 	{
 		buffer[i] = (char)*pUART_data;
+		*pLED = buffer[i]*buffer[i];
 		i = (i+1)%sizeof(buffer);
+
 	}
 
 }
@@ -204,7 +209,7 @@ int Test10_LoadStore()
 }
 
 
-#define	NUM_ELEMENTS	100000
+#define	NUM_ELEMENTS	10000
 #define	NUM_RUNS		3
 int Test11_AddSub()
 {
@@ -299,7 +304,7 @@ int pi_calc()
     return 0;
 }
 
-#define	TEST_SIZE			(32*1024*1024)	// Bytes
+#define	TEST_SIZE			(128*1024)	// Bytes
 #define	SMALL_TEST_SIZE		(8192)			// Bytes
 int main (void)
 {
@@ -312,7 +317,8 @@ int main (void)
 	time_t curr_date;
 	struct tm *pDate, date;
 	UINT32 start, end;
-	char sel;
+	char sel[80];
+	struct timeval time_sec;
 
 	UINT8 *ram8 = NULL;
 	UINT16 *ram16 = NULL;
@@ -522,9 +528,12 @@ int main (void)
 	sputs("\r\n");
 
 	printf("Datum und Uhrzeit setzen? [j/N]: ");
-	scanf("%c", &sel);
+	scanf("%s", sel);
-	if (toupper(sel) == 'J')
+	if (toupper(sel[0]) == 'J')
 	{
+		do
+		{
+			printf("Datum\n");
 		printf("Jahr  : ");
 		scanf("%d", &date.tm_year);
 		printf("Monat : ");
@@ -532,7 +541,30 @@ int main (void)
 		printf("Tag   : ");
 		scanf("%d", &date.tm_mday);
 
-		printf("Wir haben heute den %d. %d. %d\n", date.tm_mday, date.tm_mon, date.tm_year);
+			printf("Uhrzeit\n");
+			printf("Stunde  : ");
+			scanf("%d", &date.tm_hour);
+			printf("Minute  : ");
+			scanf("%d", &date.tm_min);
+			printf("Sekunde : ");
+			scanf("%d", &date.tm_sec);
+
+			date.tm_year  -= 1900;
+			date.tm_mon  -= 1;
+			time_sec.tv_sec = mktime(&date);
+			time_sec.tv_usec = 0;
+			settimeofday(&time_sec, NULL);
+
+			printf("Datum\n");
+			curr_date = time(NULL);
+			pDate = gmtime(&curr_date);
+			puts(asctime(pDate));
+			printf("\nOK? [J/n]: ");
+			scanf("%s", sel);
+			printf("sel=%d\n", (int)sel[0]);
+
+
+		} while(toupper(sel[0]) == 'N');
 	}
 
 	interrupt_enable(3);

lib/CPUs/MIPS/bsp/examples/xcpt.c

@@ -18,7 +18,7 @@ char *_xcpt_code_str[32] =
 #define PRINT_REG(tag_str, reg)			\
 			sputs(tag_str);				\
 			print_word(reg);			\
-			sputs("\n");
+			sputs("   ");
 
 int _xcpt_default_dispatch(struct xcptcontext * xcp)
 {
@@ -59,45 +59,54 @@ int _xcpt_deliver(struct xcptcontext * _xcp)
 		PRINT_REG("  Cause : ", _xcp->cr);
 		PRINT_REG("    EPC : ", _xcp->epc);
 		PRINT_REG("BadAddr : ", _xcp->baddr);
+		sputs("\n");
 		PRINT_REG("   MDLO : ", _xcp->mdlo);
 		PRINT_REG("   MDHI : ", _xcp->mdhi);
 
 		sputs("\n");
 
 		sputs("Registers:\n");
-		PRINT_REG(" 0 (zero) : ", _xcp->regs[0]);
+		PRINT_REG(" 0 (ze) : ", _xcp->regs[0]);
 		PRINT_REG(" 1 (at) : ", _xcp->regs[1]);
 		PRINT_REG(" 2 (v0) : ", _xcp->regs[2]);
 		PRINT_REG(" 3 (v1) : ", _xcp->regs[3]);
+		sputs("\n");
 		PRINT_REG(" 4 (a0) : ", _xcp->regs[4]);
 		PRINT_REG(" 5 (a1) : ", _xcp->regs[5]);
 		PRINT_REG(" 6 (a2) : ", _xcp->regs[6]);
 		PRINT_REG(" 7 (a3) : ", _xcp->regs[7]);
+		sputs("\n");
 		PRINT_REG(" 8 (t0) : ", _xcp->regs[8]);
 		PRINT_REG(" 9 (t1) : ", _xcp->regs[9]);
 		PRINT_REG("10 (t2) : ", _xcp->regs[10]);
 		PRINT_REG("11 (t3) : ", _xcp->regs[11]);
+		sputs("\n");
 		PRINT_REG("12 (t4) : ", _xcp->regs[12]);
 		PRINT_REG("13 (t5) : ", _xcp->regs[13]);
 		PRINT_REG("14 (t6) : ", _xcp->regs[14]);
 		PRINT_REG("15 (t7) : ", _xcp->regs[15]);
+		sputs("\n");
 		PRINT_REG("16 (s0) : ", _xcp->regs[16]);
 		PRINT_REG("17 (s1) : ", _xcp->regs[17]);
 		PRINT_REG("18 (s2) : ", _xcp->regs[18]);
 		PRINT_REG("19 (s3) : ", _xcp->regs[19]);
+		sputs("\n");
 		PRINT_REG("20 (s4) : ", _xcp->regs[20]);
 		PRINT_REG("21 (s5) : ", _xcp->regs[21]);
 		PRINT_REG("22 (s6) : ", _xcp->regs[22]);
 		PRINT_REG("23 (s7) : ", _xcp->regs[23]);
+		sputs("\n");
 		PRINT_REG("24 (t8) : ", _xcp->regs[24]);
 		PRINT_REG("25 (t9) : ", _xcp->regs[25]);
 		PRINT_REG("26 (k0) : ", _xcp->regs[26]);
 		PRINT_REG("27 (k1) : ", _xcp->regs[27]);
+		sputs("\n");
 		PRINT_REG("28 (gp) : ", _xcp->regs[28]);
 		PRINT_REG("29 (sp) : ", _xcp->regs[29]);
 		PRINT_REG("30 (fp) : ", _xcp->regs[30]);
 		PRINT_REG("31 (ra) : ", _xcp->regs[31]);
 		sputs("\n");
+		sputs("\n");
 
 		exc_code = (_xcp->cr >> 2) & 0x1F;
 

lib/CPUs/MIPS/bsp/toolchain/make.sh

@@ -2,46 +2,150 @@
 TARGET=mipsel-elf
 PREFIX=/usr/local
 
+SRC_BINUTILS=binutils-2.19
+SRC_GCC=gcc-4.3.3
+SRC_NEWLIB=newlib-1.16.0
+SRC_GMP=gmp-4.2.4
+SRC_MPFR=mpfr-2.4.0
+
 # ---------------------------------------------------------------
 # 1. Binutils bauen und installieren
 # ---------------------------------------------------------------
-if [ ! -d ./binutils-2.19 ]; then
+if [ ! -e $SRC_BINUTILS.tar.bz2 ]; then
-  tar -xjf binutils-2.19.tar.bz2
+  echo Downloading $SRC_BINUTILS
+  wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/binutils/$SRC_BINUTILS.tar.bz2 || exit 1
+else
+  echo Skipped downloading $SRC_BINUTILS
 fi  
 
-if [ ! -d ./binutils-2.19_build ]; then
+if [ ! -e ./$SRC_BINUTILS ]; then
-  mkdir -p binutils-2.19_build
+  echo Unpacking $SRC_BINUTILS
-  cd binutils-2.19_build
+  tar -xjf $SRC_BINUTILS.tar.bz2 || exit 1
-  ../binutils-2.19/configure --target=$TARGET --prefix=$PREFIX
+else
-  make
+  echo Skipped unpacking $SRC_BINUTILS
-  make install
+fi
+
+if [ ! -e ./$SRC_BINUTILS-build ]; then
+  echo Building $SRC_BINUTILS
+  mkdir -p $SRC_BINUTILS-build
+  cd $SRC_BINUTILS-build
+  ../$SRC_BINUTILS/configure --target=$TARGET --prefix=$PREFIX || exit 1
+  make || exit 1
+  make install || exit 1
   cd ..
 else
-  echo binutils is already built.
+  echo $SRC_BINUTILS is already built.
 fi
 
 # ---------------------------------------------------------------
-# 2. GCC & newlib bauen und installieren
+# 2. GMP bauen und installieren
 # ---------------------------------------------------------------
-if [ ! -d ./newlib-1.16.0 ]; then
+if [ ! -e $SRC_GMP.tar.bz2 ]; then
-  tar -xzf newlib-1.16.0.tar.gz
+  echo Downloading $SRC_GMP
+  wget http://ftp.sunet.se/pub/gnu/gmp/$SRC_GMP.tar.bz2 || exit 1
+else
+  echo Skipped downloading $SRC_GMP
 fi  
 
-if [ ! -d ./gcc-4.3.2 ]; then
+if [ ! -e ./$SRC_GMP ]; then
-  tar -xjf gcc-4.3.2.tar.bz2
+  echo Unpacking $SRC_GMP
-  cd ./gcc-4.3.2
+  tar -xjf $SRC_GMP.tar.bz2 || exit 1
-  ln -sf ../newlib-1.16.0/newlib/ .
+else
-  cd ..
+  echo Skipped unpacking $SRC_GMP
 fi
 
-if [ ! -d ./gcc-4.3.2_build ]; then
+if [ ! -e ./$SRC_GMP-build ]; then
-  mkdir -p gcc-4.3.2_build
+  echo Building $SRC_GMP
-  cd gcc-4.3.2_build
+  mkdir -p $SRC_GMP-build
-  ../gcc-4.3.2/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++"
+  cd $SRC_GMP-build
-  make all
+  ../$SRC_GMP/configure --prefix=$PREFIX || exit 1
-  make info
+  make || exit 1
-  make install
+  make check || exit 1
+  make install || exit 1
   cd ..
 else
-  echo GCC is already built.
+  echo $SRC_GMP is already built.
+fi
+
+# ---------------------------------------------------------------
+# 3. MPFR bauen und installieren
+# ---------------------------------------------------------------
+if [ ! -e $SRC_MPFR.tar.bz2 ]; then
+  echo Downloading $SRC_MPFR
+  wget http://www.mpfr.org/mpfr-current/$SRC_MPFR.tar.bz2 || exit 1
+else
+  echo Skipped downloading $SRC_MPFR
+fi  
+
+if [ ! -e ./$SRC_MPFR ]; then
+  echo Unpacking $SRC_MPFR
+  tar -xjf $SRC_MPFR.tar.bz2 || exit 1
+else
+  echo Skipped unpacking $SRC_MPFR
+fi
+
+if [ ! -e ./$SRC_MPFR-build ]; then
+  echo Building $SRC_MPFR
+  mkdir -p $SRC_MPFR-build
+  cd $SRC_MPFR-build
+  ../$SRC_MPFR/configure --prefix=$PREFIX || exit 1
+  make || exit 1
+  make check || exit 1
+  make install || exit 1
+  cd ..
+else
+  echo $SRC_MPFR is already built.
+fi
+
+# ---------------------------------------------------------------
+# 4. GCC & newlib bauen und installieren
+# ---------------------------------------------------------------
+if [ ! -e $SRC_NEWLIB.tar.gz ]; then
+  echo Downloading $SRC_NEWLIB
+  wget ftp://sources.redhat.com/pub/newlib/$SRC_NEWLIB.tar.gz || exit 1
+else
+  echo Skipped downloading $SRC_NEWLIB
+fi  
+
+if [ ! -e ./$SRC_NEWLIB ]; then
+  echo Unpacking $SRC_NEWLIB
+  tar -xzf $SRC_NEWLIB.tar.gz || exit 1
+  if [ -e  $SRC_NEWLIB-jens.patch ]; then
+    echo Patching $SRC_NEWLIB
+    patch -p0 < $SRC_NEWLIB-jens.patch || exit 1
+  fi	
+else
+  echo Skipped unpacking $SRC_NEWLIB
+fi
+
+if [ ! -e $SRC_GCC.tar.bz2 ]; then
+  echo Downloading $SRC_GCC
+  wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/gcc/$SRC_GCC/$SRC_GCC.tar.bz2 || exit 1
+else
+  echo Skipped downloading $SRC_GCC
+fi  
+
+if [ ! -e ./$SRC_GCC ]; then
+  echo Unpacking $SRC_GCC
+  tar -xjf $SRC_GCC.tar.bz2 || exit 1
+  cd ./$SRC_GCC
+  ln -sf ../$SRC_NEWLIB/newlib/ .
+  cd ..
+else
+  echo Skipped unpacking $SRC_GCC
+fi
+
+if [ ! -e ./$SRC_GCC-build ]; then
+  echo Building $SRC_GCC
+  mkdir -p $SRC_GCC-build
+  cd $SRC_GCC-build
+  ../$SRC_GCC/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++" || exit 1
+  LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PREFIX/lib make all || exit 1
+  make info || exit 1
+  make install || exit 1
+  cd ..
+  echo $PREFIX/lib >/etc/ld.so.conf.d/local.conf
+  ldconfig
+else
+  echo $SRC_GCC is already built.
 fi

lib/CPUs/MIPS/bsp/toolchain/newlib-1.16.0-jens.patch

@@ -0,0 +1,11 @@
+diff -Naur newlib-1.16.0/newlib/libc/machine/mips/strlen.c newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c
+--- newlib-1.16.0/newlib/libc/machine/mips/strlen.c	2002-03-14 03:41:43.000000000 +0100
++++ newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c	2009-02-14 15:52:58.000000000 +0100
+@@ -60,6 +60,7 @@
+ 	"	addiu	$2,$4,1\n"
+ 	"\n"
+ 	"1:	lbu	$3,0($4)\n"
++	"	nop\n"
+ 	"	bnez	$3,1b\n"
+ 	"	addiu	$4,$4,1\n"
+ 	"\n"

lib/CPUs/MIPS/bsp/toolchain/newlib-1.17.0-jens.patch

@@ -0,0 +1,11 @@
+diff -Naur newlib-1.17.0/newlib/libc/machine/mips/strlen.c newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c
+--- newlib-1.17.0/newlib/libc/machine/mips/strlen.c	2002-03-14 03:41:43.000000000 +0100
++++ newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c	2009-02-14 15:45:19.000000000 +0100
+@@ -60,6 +60,7 @@
+ 	"	addiu	$2,$4,1\n"
+ 	"\n"
+ 	"1:	lbu	$3,0($4)\n"
++	"	nop\n"
+ 	"	bnez	$3,1b\n"
+ 	"	addiu	$4,$4,1\n"
+ 	"\n"

lib/CPUs/MIPS/dist/mdist

@@ -2,7 +2,7 @@
 
 PROJECT="mips_top"
 DIST_FILE="./files.dist"
-DIST_DIR="./release/mips.r10a"
+DIST_DIR="./release/mips.r11"
 
 # ---------------------------------------------------------------
 mkdir -p $DIST_DIR/src
@@ -16,9 +16,11 @@ cp -a ../doc/*.pdf $DIST_DIR/doc/
 cp -a ../doc/*.txt $DIST_DIR/doc/
 cp -a ../tools/* $DIST_DIR/tools/
 
+cp -a ./tmpl/notes.txt $DIST_DIR/
 cp -a ./tmpl/gpl-3.0.txt $DIST_DIR/
 cp -a ./tmpl/tb_mips_top.wdo $DIST_DIR/sim/
 cp -a ./tmpl/hello.flash.bin $DIST_DIR/sim/
+cp -a ./tmpl/mips_sys.vhd $DIST_DIR/src/
 
 for i in $(cat -s $DIST_FILE); do
   echo $i;

lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd

@@ -0,0 +1,335 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+use work.async_types.all;
+use work.async_defs.all;
+
+ENTITY mips_sys IS
+	GENERIC 
+	(
+		ICACHE_SIZE			: natural := 512;	-- words
+		DCACHE_SIZE			: natural := 512;	-- words
+		SRAM_ADDR_WIDTH		: integer := 14;
+		FLASH_ADDR_WIDTH	: integer := 14
+	);
+	PORT
+	(
+		rst				: in  std_logic;
+		clk				: in  std_logic;
+		flash_cs_n		: out std_logic;
+		flash_oe_n		: out std_logic;
+		flash_we_n		: out std_logic;
+		flash_be_n		: out unsigned(3 downto 0);
+		sram_cs_n		: out std_logic;
+		sram_we_n		: out std_logic;
+		sram_oe_n		: out std_logic;
+		sram_be_n		: out unsigned(3 downto 0);
+		sram_a			: out unsigned(SRAM_ADDR_WIDTH-1 downto 0);
+		sram_d			: inout unsigned(31 downto 0);
+		flash_a			: out unsigned(FLASH_ADDR_WIDTH-1 downto 0);
+		flash_d			: inout unsigned(31 downto 0);
+		
+		gpo0			: out unsigned(31 downto 0);
+		gpo1			: out unsigned(31 downto 0);
+		gpi0			: in  unsigned(31 downto 0);
+		gpi1			: in  unsigned(31 downto 0);
+
+		rx				: in std_logic;
+		tx				: out std_logic;
+
+		debug			: out unsigned(1 downto 0)
+	);
+END mips_sys;
+
+ARCHITECTURE behavior OF mips_sys IS 
+
+	constant CLK_PERIOD 			: time := 10 ns;
+	
+	-- Master 
+	signal ACK_I		: STD_LOGIC := '0';
+	signal SRDY_I		: STD_LOGIC := '0';
+	signal ADDR_O		: unsigned(31 downto 0);
+	signal DAT_I		: unsigned(31 downto 0) := (others => '0');
+	signal DAT_O		: unsigned(31 downto 0);
+	signal WE_O			: STD_LOGIC;
+	signal SEL_O		: unsigned(3 downto 0);
+	signal CYC_O		: STD_LOGIC;
+	signal STB_O		: STD_LOGIC;
+	signal MRDY_O		: STD_LOGIC;
+	signal INT			: unsigned (5 downto 0) := (others => '0');
+	
+	-- Slaves
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal DAT_O_rom	: unsigned(31 downto 0);
+
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal DAT_O_flash	: unsigned(31 downto 0);
+
+	signal CYC_I_sram	: std_logic;
+	signal ACK_O_sram	: std_logic;
+	signal SRDY_O_sram	: std_logic;
+	signal DAT_O_sram	: unsigned(31 downto 0);
+
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal DAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal DAT_O_uart	: unsigned(31 downto 0);
+
+	signal int_uart_rx	: std_logic;
+
+	type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
+	signal mem_area : mem_area_t;
+
+BEGIN
+
+------------------------------------------------------------------
+-- Memory mux
+------------------------------------------------------------------
+mem_mux:
+	process(ADDR_O)
+	begin
+		mem_area	<= mem_dead;
+		if ADDR_O(31 downto 28) = X"0" then
+			mem_area	<= mem_flash;
+		elsif ADDR_O(31 downto 28) = X"A" then
+			if ADDR_O(27 downto 26) = "00" then
+				if ADDR_O(18 downto 16) = "000" then
+					mem_area	<= mem_gpio;
+				elsif ADDR_O(18 downto 16) = "001" then
+					mem_area	<= mem_uart;
+				end if;	
+			elsif ADDR_O(27 downto 26) = "01" then
+				mem_area	<= mem_flash;
+			end if;	
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
+			mem_area	<= mem_rom;
+		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
+			mem_area	<= mem_sram;
+		end if;
+	end process;	
+
+signal_mux:
+	process(mem_area, CYC_O)
+	begin
+	
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_sram		<= '0';
+		
+		case mem_area is
+
+		when mem_gpio =>
+			CYC_I_gpio		<= CYC_O;
+
+		when mem_uart =>
+			CYC_I_uart		<= CYC_O;
+
+		when mem_flash =>
+			CYC_I_flash		<= CYC_O;
+
+		when mem_rom =>
+			CYC_I_rom		<= CYC_O;
+
+		when mem_sram =>
+			CYC_I_sram		<= CYC_O;
+		
+		when others => null;
+		
+		end case;
+		
+	end process;
+
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
+ 	DAT_I		<=	DAT_O_sram when CYC_I_sram = '1' else
+					DAT_O_rom when CYC_I_rom = '1' else
+					DAT_O_flash when CYC_I_flash = '1' else
+					DAT_O_uart when CYC_I_uart = '1' else
+					DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
+
+
+------------------------------------------------------------------
+inst_mips_top: entity work.mips_top
+	GENERIC MAP
+	(
+		icache_size	=> ICACHE_SIZE,		-- words
+		dcache_size	=> DCACHE_SIZE		-- words
+	)
+	PORT MAP
+	(
+		debug	=> debug,
+		RST_I	=> rst,
+		CLK_I	=> clk,
+		ACK_I	=> ACK_I,
+		SRDY_I	=> SRDY_I,
+		ADDR_O	=> ADDR_O,
+		DAT_I	=> DAT_I,
+		DAT_O	=> DAT_O,
+		WE_O	=> WE_O,
+		SEL_O	=> SEL_O,
+		CYC_O	=> CYC_O,
+		STB_O	=> STB_O,
+		MRDY_O	=> MRDY_O,
+		INT		=> INT
+	);
+	INT(1)	<= int_uart_rx;
+	
+inst_rom : entity work.rom_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_rom,
+		STB_I	=> STB_O,
+		ACK_O	=> ACK_O_rom,
+		MRDY_I	=> MRDY_O,
+		SRDY_O	=> SRDY_O_rom,
+		ADDR_I	=> ADDR_O,
+		DAT_O	=> DAT_O_rom
+	);
+
+inst_gpio : entity work.gpio_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_gpio,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_O_gpio,
+
+		sys_gpo0	=> gpo0,
+		sys_gpo1	=> gpo1,
+		sys_gpi0	=> gpi0,
+		sys_gpi1	=> gpi1
+	);
+
+inst_flash_port : entity work.async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> FLASH_ADDR_WIDTH,
+		data_width		=> 32,
+		byte_sel_width	=> 4,
+		async_timespec	=> ts_flash
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_flash,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
+		MRDY_I		=> MRDY_O,
+		SEL_I		=> SEL_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_O_flash,
+		async_a		=> flash_a,
+		async_d		=> flash_d,
+		async_cs	=> flash_cs_n,
+		async_wr	=> flash_we_n,
+		async_rd	=> flash_oe_n,
+		async_be	=> flash_be_n,
+		async_rst	=> open
+	);
+
+inst_sram_port : entity work.async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> SRAM_ADDR_WIDTH,
+		data_width		=> 32,
+		byte_sel_width	=> 4,
+		async_timespec	=> ts_sram
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_sram,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_sram,
+		SRDY_O		=> SRDY_O_sram,
+		MRDY_I		=> MRDY_O,
+		SEL_I		=> SEL_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_O_sram,
+		async_a		=> sram_a,
+		async_d		=> sram_d,
+		async_cs	=> sram_cs_n,
+		async_wr	=> sram_we_n,
+		async_rd	=> sram_oe_n,
+		async_be	=> sram_be_n,
+		async_rst	=> open
+	);
+
+inst_uart : entity work.uart_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_uart,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_O_uart,
+		INT_RX_O	=> int_uart_rx,
+		INT_TX_O	=> open,
+		ser_rx		=> rx,
+		ser_tx		=> tx
+	);
+	
+END;

lib/CPUs/MIPS/dist/tmpl/notes.txt

@@ -0,0 +1,36 @@
+-----------------------------------------------------------------
+Changes in release 11
+-----------------------------------------------------------------
+- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset
+  (fixes CPU unrecoverable state after reset)
+- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
+- new example source: test_exception
+- minor changes in libsys
+- added async_port_timing in doc
+- examples/testbench: date set now really works
+
+-----------------------------------------------------------------
+Changes in release 10b
+-----------------------------------------------------------------
+- fixed compiler bug (missing nop after lw) in bootloader,
+  which caused exception during boot
+
+-----------------------------------------------------------------
+Changes in release 10a
+-----------------------------------------------------------------
+async_port_wb:
+- added byte enable for async_port
+
+bootloader.c
+- fixed compiler bug (missing nop after lw)
+
+mips-core
+- SEL_O lines are also asserted correctly during reads
+
+tools/romgen
+- TCL-Jtage now compatible with Chipscope 10.1
+
+mips_sys.c
+- use byte enable for sram and flash
+
+

lib/CPUs/MIPS/sim/tb_mips_top.wdo

@@ -39,10 +39,37 @@ add wave -noupdate -format Literal /tb_mips_top/sram_be_n
 add wave -noupdate -divider ALU
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
+add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu
 add wave -noupdate -divider PC
 add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc
-add wave -noupdate -divider PC
+add wave -noupdate -divider COP0
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/events
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/badvaddr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_code
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/stat_reg_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/eflags_reg_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/epc_reg_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/code_reg_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/ip_reg_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/bd
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exception_end
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/eflags
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/exc_enable
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/inst_cop/cop_ex_en
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/cop_pipe_id
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/cop_pipe_ex
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_state
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/inst_cop/exc_staten
+add wave -noupdate -divider Pipestages
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
 add wave -noupdate -format Logic /tb_mips_top/clk
@@ -52,12 +79,58 @@ add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/i
 add wave -noupdate -format Logic /tb_mips_top/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_rst
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/run_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
+add wave -noupdate -divider I-Cache
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
+add wave -noupdate -divider D-Cache
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we
+add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1375665640 ps} 0}
+WaveRestoreCursors {{Cursor 1} {2127774 ps} 0}
 configure wave -namecolwidth 188
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -71,4 +144,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {0 ps} {1680 us}
+WaveRestoreZoom {0 ps} {5031559 ps}

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -127,7 +127,7 @@ END COMPONENT;
 		return result;
 	end to_tram_data;
 
-	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_data, rd_cache);
 	signal s, sn : cache_state_t;
 	
 	signal	cache_busy			: std_logic;
@@ -159,19 +159,19 @@ END COMPONENT;
 	signal  tram_dout			: tram_data_t;
 	signal  tram_addr_wr		: unsigned(cache_index_width-1 downto 0);
 	signal  tram_din			: tram_data_t;
-	signal	tram_re				: std_logic;
 	signal	tram_we				: std_logic;
 	
 	signal	fill_count			: natural range 0 to 2**word_index_width-1;
-	signal	fill_count_rst		: std_logic;
+	signal	fill_count_en		: std_logic;
-	signal	flush_index_count		: natural range 0 to 2**cache_index_width-1;
+	signal	fill_count_rdy		: std_logic;
-	signal	flush_index_count_en	: std_logic;
+	signal	flush_count			: natural range 0 to 2**cache_index_width-1;
+	signal	flush_count_en		: std_logic;
+	signal	flush_count_rdy		: std_logic;
 	signal	request_count		: natural range 0 to 2**word_index_width-1;
 	signal	request_count_en	: std_logic;
-	signal	request_count_rst		: std_logic;
+	signal	request_count_rdy	: std_logic;
 	signal	cpu_reg_en			: std_logic;
 	signal	was_miss			: std_logic;
-	signal	cache_fill				: std_logic;
 	signal	cpu_hit_we			: std_logic;
 	signal	instant_raw			: std_logic;
 
@@ -183,7 +183,7 @@ cpu_index_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if cache_fill = '1' then
+			if fill_count_en = '1' then
 				if ACK_I = '1' then
 					word_index_reg	<= word_index_reg + 1;
 				end if;	
@@ -199,8 +199,10 @@ addr_windex_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if request_count_en = '1' and SRDY_I = '1' then
+			if request_count_en = '1'then
+				if SRDY_I = '1' then
 					addr_windex_reg	<= addr_windex_reg + 1;
+				end if;	
 			elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
 				addr_windex_reg	<= cpu_word_index;
 			end if;
@@ -247,15 +249,17 @@ instant_raw_logic:
 	end process;	
 
 inst_tag_ram : dpram_1w1r
-	GENERIC MAP (
+	GENERIC MAP 
+	(
 		addr_width	=> tram_addr_width,
 		data_width	=> tram_data_width
 	)
-	PORT MAP (
+	PORT MAP 
+	(
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
-		en_b	=> tram_re,
+		en_b	=> '1',
 		we_a	=> tram_we,
 		addr_a	=> tram_addr_wr,
 		addr_b	=> tram_addr_rd,
@@ -268,11 +272,13 @@ gen_data_ram:
 	begin
 	
 	inst_data_ram : dpram_2w2r
-		GENERIC MAP (
+		GENERIC MAP 
+		(
 			addr_width	=> lg2(cache_size),
 			data_width	=> word_t'length/4
 		)
-		PORT MAP (
+		PORT MAP 
+		(
 			clk_a	=> CLK_I,
 			clk_b	=> CLK_I,
 			en_a	=> '1',
@@ -306,31 +312,28 @@ cache_state_next:
 	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
 	cache_hit			<= tag_match and cache_entry_out.valid;
 	tram_din			<= to_tram_data(cache_entry_in);
+	tram_addr_wr		<= to_unsigned(flush_count, cache_index_width) when flush_count_en = '1' else cache_index_reg;
 	tram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_dcache_entry(tram_dout);
 	
-	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0'and instant_raw = '0' and cache_fill = '0') else (cache_index_reg & word_index_reg);
+	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (cache_index_reg & word_index_reg);
 	ADDR_O				<= tag_index_reg & cache_index_reg & addr_windex_reg & "00";
 	ctrl_dram_addr		<= cache_index_reg & word_index_reg;
-	ctrl_dram_we		<= (others => cache_fill and ACK_I);
+	ctrl_dram_we		<= (others => fill_count_en and ACK_I);
 	cpu_dram_we			<= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
 	
 cache_state:
-	process(s, instant_raw, cache_hit, flush_index_count, fill_count, request_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
+	process(s, instant_raw, cache_hit, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
 		tram_we					<= '0';
-		flush_index_count_en	<= '0';
+		flush_count_en			<= '0';
-		fill_count_rst			<= '0';
 		request_count_en		<= '0';
-		request_count_rst		<= '0';
+		fill_count_en			<= '0';
 		CYC_O					<= '0';
 		STB_O					<= '0';
-		tram_re					<= '0';
 		was_miss				<= '0';
-		cache_fill				<= '0';
-		tram_addr_wr			<= to_unsigned(flush_index_count, cache_index_width);
 		cache_entry_in.tv_p		<= (others => '0');
 		cache_entry_in.tag		<= tag_index_reg;
 		cache_entry_in.valid	<= '0';
@@ -342,7 +345,6 @@ cache_state:
 		when ready =>
 			cache_busy 		<= '0';
 			cpu_reg_en		<= '1';
-			tram_re			<= cpu_en;
 			if cpu_en2 = '1' then
 				if cache_hit = '0' and cpu_we_reg = '0' then
 					sn						<= mem_request;
@@ -352,79 +354,61 @@ cache_state:
 				end if;	
 			end if;	
 		when flush =>
-			flush_index_count_en	<= '1';
+			flush_count_en			<= '1';
-			tram_addr_wr			<= to_unsigned(flush_index_count, cache_index_width);
 			tram_we					<= '1';
 			cache_entry_in.valid	<= '0';
 			cache_entry_in.tag		<= (others => '0');
-			if flush_index_count = 0 then
+			if flush_count_rdy = '1' then
+				tram_we				<= '0';
 				sn	<= ready;
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
-					tram_re				<= '1';
 				end if;
 			end if;
 		when mem_request =>
-			fill_count_rst		<= '1';
-			request_count_rst		<= '1';
 			CYC_O		<= '1';
 			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
-			cache_fill			<= '1';
+			fill_count_en		<= '1';
 			request_count_en	<= '1';
 			CYC_O				<= '1';
 			STB_O				<= '1';
-			if request_count = 0 then
+			if request_count_rdy = '1' then
-				if SRDY_I = '1' then
+				STB_O			<= '0';
 				sn 				<= mem_data;
 			end if;	
-			end if;	
 		when mem_data =>
 			CYC_O			<= '1';
-			cache_fill	<= '1';
+			fill_count_en	<= '1';
-			if fill_count = 0 then
+			if fill_count_rdy = '1' then
-				if ACK_I = '1' then
-					sn			<= upd_cache;
-				end if;	
-			end if;	
-		when upd_cache =>
-			tram_addr_wr			<= cache_index_reg;
 				tram_we					<= '1';
 				cache_entry_in.valid	<= '1';
 				sn						<= rd_cache;
+			end if;	
 		when rd_cache =>
-			tram_re					<= '1';
 			was_miss				<= '1';
 			sn	<= ready;
 
 		when others => 
 			sn	<= ready;
 		end case;
+
 	end process;
 
-flush_index_counter:
+flush_counter:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if flush_index_count_en = '0' then
+			if flush_count_en = '0' then
-				flush_index_count	<= 2**cache_index_width-1;
+				flush_count_rdy	<= '0';
-			elsif flush_index_count /= 0 then
+				flush_count		<= 2**cache_index_width-1;
-				flush_index_count	<= flush_index_count - 1;
+			else
-			end if;
+				if flush_count /= 0 then
-		end if;
+					flush_count	<= flush_count - 1;
-	end process;	
+				else
-		
+					flush_count_rdy	<= '1';
-fill_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if fill_count_rst = '1' then
-				fill_count	<= 2**word_index_width-1;
-			elsif cache_fill = '1' and ACK_I = '1' then
-				if fill_count /= 0 then
-					fill_count 	<= fill_count - 1;
 				end if;	
 			end if;
 		end if;
@@ -434,11 +418,35 @@ request_counter:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if request_count_rst = '1' then
+			if request_count_en = '0' then
+				request_count_rdy	<= '0';
 				request_count		<= 2**word_index_width-1;
-			elsif request_count_en = '1' and SRDY_I = '1' then
+			else	
+				if SRDY_I = '1' then
 					if request_count /= 0 then
 						request_count 	<= request_count - 1;
+					else
+						request_count_rdy	<= '1';
+					end if;
+				end if;	
+			end if;	
+		end if;
+	end process;	
+
+fill_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if fill_count_en = '0' then
+				fill_count_rdy	<= '0';
+				fill_count		<= 2**word_index_width-1;
+			else	
+				if ACK_I = '1' then
+					if fill_count /= 0 then
+						fill_count 	<= fill_count - 1;
+					else
+						fill_count_rdy	<= '1';
+					end if;
 				end if;
 			end if;	
 		end if;

lib/CPUs/MIPS/src/core/icache.vhd

@@ -101,13 +101,14 @@ END COMPONENT;
 		return result;
 	end to_tag_ram_data;
 
-	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_data, rd_cache);
 	signal s, sn : cache_state_t;
 	
 	signal	cache_busy			: std_logic;
 	signal	cache_miss			: std_logic;
 	signal	tag_match			: std_logic;
 	signal  word_index_reg		: unsigned(word_index_width-1 downto 0);
+	signal  addr_windex_reg		: unsigned(word_index_width-1 downto 0);
 	signal  cache_index_reg		: unsigned(cache_index_width-1 downto 0);
 	signal  tag_index_reg		: unsigned(tag_width-1 downto 0);
 	
@@ -127,16 +128,17 @@ END COMPONENT;
 	signal	tag_ram_re			: std_logic;
 	signal	tag_ram_we			: std_logic;
 	
-	signal	ram_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	fill_count			: natural range 0 to 2**word_index_width-1;
-	signal	ram_index_count_rst		: std_logic;
+	signal	fill_count_en		: std_logic;
-	signal	cache_index_count		: natural range 0 to 2**cache_index_width-1;
+	signal	fill_count_rdy		: std_logic;
-	signal	cache_index_count_en	: std_logic;
+	signal	flush_count			: natural range 0 to 2**cache_index_width-1;
-	signal	mem_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	flush_count_en		: std_logic;
-	signal	mem_index_count_en		: std_logic;
+	signal	flush_count_rdy		: std_logic;
-	signal	mem_index_count_rst		: std_logic;
+	signal	request_count		: natural range 0 to 2**word_index_width-1;
+	signal	request_count_en	: std_logic;
+	signal	request_count_rdy	: std_logic;
 	signal	cpu_reg_en			: std_logic;
 	signal	was_miss			: std_logic;
-	signal	data_write				: std_logic;
 
 begin
 
@@ -148,6 +150,10 @@ cpu_index_reg:
 			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
+			elsif fill_count_en = '1' then
+				if ACK_I = '1' then
+					word_index_reg	<= word_index_reg + 1;
+				end if;	
 			elsif cpu_reg_en = '1' then
 				word_index_reg	<= cpu_word_index;
 				cache_index_reg	<= cpu_cache_index;
@@ -156,12 +162,28 @@ cpu_index_reg:
 		end if;
 	end process;	
 
+addr_windex_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if request_count_en = '1'then
+				if SRDY_I = '1' then
+					addr_windex_reg	<= addr_windex_reg + 1;
+				end if;	
+			elsif cpu_reg_en = '1' then
+				addr_windex_reg	<= cpu_word_index;
+			end if;
+		end if;
+	end process;	
+
 inst_tag_ram : dpram_1w1r
-	GENERIC MAP (
+	GENERIC MAP 
+	(
 		addr_width	=> tag_ram_addr_width,
 		data_width	=> tag_ram_data_width
 	)
-	PORT MAP (
+	PORT MAP
+	(
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
@@ -174,11 +196,13 @@ inst_tag_ram : dpram_1w1r
 	);
 
 inst_data_ram : dpram_1w1r
-	GENERIC MAP (
+	GENERIC MAP
+	(
 		addr_width	=> lg2(cache_size),
 		data_width	=> word_t'length
 	)
-	PORT MAP (
+	PORT MAP
+	(
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
@@ -209,31 +233,29 @@ cache_state_next:
 	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
 	cache_miss			<= not (tag_match and cache_entry_out.valid);
 	tag_ram_data_wr		<= to_tag_ram_data(cache_entry_in);
+	tag_ram_addr_wr		<= to_unsigned(flush_count, cache_index_width) when flush_count_en = '1' else cache_index_reg;
 	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_icache_entry(tag_ram_data_rd);
 	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
-	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	ADDR_O				<= tag_index_reg & cache_index_reg & addr_windex_reg & "00";
-	data_ram_addr_wr	<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
+	data_ram_addr_wr	<= cache_index_reg & word_index_reg;
 	data_ram_data_wr	<= DAT_I;
-	data_ram_we			<= data_write and ACK_I;
+	data_ram_we			<= fill_count_en and ACK_I;
 
 cache_state:
-	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
+	process(s, cache_miss, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_index_reg, cpu_en, SRDY_I, en)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
 		tag_ram_we				<= '0';
-		cache_index_count_en	<= '0';
+		flush_count_en			<= '0';
-		ram_index_count_rst		<= '0';
+		request_count_en		<= '0';
-		mem_index_count_en		<= '0';
+		fill_count_en			<= '0';
-		mem_index_count_rst		<= '0';
 		CYC_O					<= '0';
 		STB_O					<= '0';
 		data_ram_re				<= '0';
 		tag_ram_re				<= '0';
 		was_miss				<= '0';
-		data_write				<= '0';
-		tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
 		cache_entry_in.tv_p		<= (others => '0');
 		cache_entry_in.tag		<= tag_index_reg;
 		cache_entry_in.valid	<= '0';
@@ -257,12 +279,12 @@ cache_state:
 				end if;	
 			end if;	
 		when flush =>
-			cache_index_count_en	<= '1';
+			flush_count_en			<= '1';
-			tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
 			tag_ram_we				<= '1';
 			cache_entry_in.valid	<= '0';
 			cache_entry_in.tag		<= (others => '0');
-			if cache_index_count = 0 then
+			if flush_count_rdy = '1' then
+				tag_ram_we			<= '0';
 				sn	<= ready;
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
@@ -271,81 +293,89 @@ cache_state:
 				end if;
 			end if;
 		when mem_request =>
-			ram_index_count_rst		<= '1';
-			mem_index_count_rst		<= '1';
 			CYC_O		<= '1';
 			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
-			mem_index_count_en	<= '1';
+			request_count_en	<= '1';
-			data_write	<= '1';
+			fill_count_en		<= '1';
 			CYC_O				<= '1';
 			STB_O				<= '1';
-			if mem_index_count = 2**word_index_width-1 then
+			if request_count_rdy = '1' then
-				if SRDY_I = '1' then
+				STB_O			<= '0';
 				sn				<= mem_data;
 			end if;	
-			end if;	
 		when mem_data =>
 			CYC_O			<= '1';
-			data_write	<= '1';
+			fill_count_en	<= '1';
-			if ram_index_count = 2**word_index_width-1 then
+			if fill_count_rdy = '1' then
-				if ACK_I = '1' then
-					sn			<= upd_cache;
-				end if;	
-			end if;	
-		when upd_cache =>
-			tag_ram_addr_wr			<= cache_index_reg;
 				tag_ram_we				<= '1';
 				cache_entry_in.valid	<= '1';
 				sn						<= rd_cache;
-			
+			end if;	
 		when rd_cache =>
 			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';
 			sn	<= ready;
+
 		when others => 
 			sn	<= ready;
 		end case;
+
 	end process;
 
-cache_index_counter:
+flush_counter:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if cache_index_count_en = '0' then
+			if flush_count_en = '0' then
-				cache_index_count	<= 2**cache_index_width-1;
+				flush_count_rdy	<= '0';
-			elsif cache_index_count /= 0 then
+				flush_count		<= 2**cache_index_width-1;
-				cache_index_count	<= cache_index_count - 1;
+			else
-			end if;
+				if flush_count /= 0 then
-		end if;
+					flush_count	<= flush_count - 1;
-	end process;	
+				else
-		
+					flush_count_rdy	<= '1';
-ram_index_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if ram_index_count_rst = '1' then
-				ram_index_count	<= 0;
-			elsif data_write = '1' and ACK_I = '1' then
-				if ram_index_count /= 2**word_index_width-1 then
-					ram_index_count 	<= ram_index_count + 1;
 				end if;	
 			end if;
 		end if;
 	end process;	
 		
-mem_index_counter:
+request_counter:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			if mem_index_count_rst = '1' then
+			if request_count_en = '0' then
-				mem_index_count	<= 0;
+				request_count_rdy	<= '0';
-			elsif mem_index_count_en = '1' and SRDY_I = '1' then
+				request_count		<= 2**word_index_width-1;
-				if mem_index_count /= 2**word_index_width-1 then
+			else	
-					mem_index_count 	<= mem_index_count + 1;
+				if SRDY_I = '1' then
+					if request_count /= 0 then
+						request_count 	<= request_count - 1;
+					else
+						request_count_rdy	<= '1';
+					end if;
+				end if;	
+			end if;	
+		end if;
+	end process;	
+
+fill_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if fill_count_en = '0' then
+				fill_count_rdy	<= '0';
+				fill_count		<= 2**word_index_width-1;
+			else	
+				if ACK_I = '1' then
+					if fill_count /= 0 then
+						fill_count 	<= fill_count - 1;
+					else
+						fill_count_rdy	<= '1';
+					end if;
 				end if;
 			end if;	
 		end if;

lib/CPUs/MIPS/src/core/mips_pipeline.vhd

@@ -33,7 +33,7 @@ entity pipeline is
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		halt		: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
 		int			: in  unsigned(5 downto 0);
 		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
@@ -174,16 +174,11 @@ architecture Behavioral of pipeline is
 	signal clk_2, clk_1		: STD_LOGIC;
 	signal hdu				: hdu_t;
 	signal sdu				: sdu_t;
-	signal cpu_rst			: STD_LOGIC;
 	signal reg_a			: word_t;
 	signal reg_b			: word_t;
 	signal ctrl_lines		: ctrl_lines_t;
-	signal cpu_run			: STD_LOGIC;
 	signal branch_ce		: STD_LOGIC;
-	signal run_en			: STD_LOGIC;
+	signal cpu_run			: STD_LOGIC;
-	signal mul_dep			: STD_LOGIC;
-	signal imem_dep			: STD_LOGIC;
-	signal dmem_dep			: STD_LOGIC;
 	signal cop_ctrl			: cop_ctrl_in_t;
 	signal cop_stat			: cop_ctrl_out_t;
 	signal cop_din			: word_t;
@@ -213,24 +208,24 @@ begin
 	
 	clk_1					<= clk;
 	clk_2					<= not clk;
-	cpu_run					<= run_en;
+	cpu_run					<= ce;
 	
 	-- Stall Detection Unit ---------------------------------------------------
-	sdu.ID_nop				<= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
+	sdu.ID_nop				<= sdu.imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
-	sdu.EX_nop				<= mul_dep or ID_stage.nop or ID_stage.exc;
+	sdu.EX_nop				<= sdu.mul_dep or ID_stage.nop or ID_stage.exc;
 	sdu.MEM_nop				<= EX_stage.nop or EX_stage.exc;
-	sdu.WB_nop				<= dmem_dep or MEM_stage.nop;
+	sdu.WB_nop				<= sdu.dmem_dep or MEM_stage.nop;
 
-	sdu.ID_stall			<= dmem_dep or imem_dep or mul_dep or ID_stage.exc;
+	sdu.ID_stall			<= sdu.dmem_dep or sdu.imem_dep or sdu.mul_dep or ID_stage.exc;
-	sdu.EX_stall			<= dmem_dep;
+	sdu.EX_stall			<= sdu.dmem_dep;
-	sdu.MEM_stall			<= dmem_dep;
+	sdu.MEM_stall			<= sdu.dmem_dep;
 	sdu.WB_stall			<= '0';
 
-	mul_dep					<= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
+	sdu.mul_dep				<= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
-	imem_dep				<= not imem_rdy;
+	sdu.imem_dep			<= not imem_rdy;
-	dmem_dep				<= not dmem_rdy and MEM_stage.ctrl.dmem_en;
+	sdu.dmem_dep			<= not dmem_rdy and MEM_stage.ctrl.dmem_en;
 	---------------------------------------------------------------------------
-	imem_en 				<= cpu_run and not (mul_dep or dmem_dep or cop_stat.exc_commit);
+	imem_en 				<= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or cop_stat.exc_commit);
 	
 --------------------------------------------------------------------------
 -- Muldiv
@@ -238,7 +233,7 @@ begin
 inst_muldiv: muldiv
 	PORT MAP
 	(
-		rst			=> cpu_rst,
+		rst			=> rst,
 		clk			=> clk,
 		hilo_we		=> EX_stage.ctrl.mul_hilo_we,
 		din_hi		=> EX_stage.reg_a,
@@ -257,7 +252,7 @@ inst_muldiv: muldiv
 inst_cop: cop
 	PORT MAP
 	(
-		rst			=> cpu_rst,
+		rst			=> rst,
 		clk			=> clk,
 		sdu			=> sdu,
 		events		=> MEM_stage.events,
@@ -308,12 +303,13 @@ proc_stage_pc_next:
 	process(clk_1)
 	begin
 		if rising_edge(clk_1) then
-			branch_ce	<= '0';
 			cop_ctrl.exc_left		<= '0';
 			if rst = '1' then
 				pc.nxt	<= pc.curr;
 				pc.last	<= pc.curr;
+				branch_ce	<= '1';
 			else
+				branch_ce	<= '0';
 				if cop_stat.exc_commit = '1' then
 					pc.nxt	<= cop_stat.exc_vec;
 				elsif sdu.ID_stall = '0' then
@@ -362,25 +358,6 @@ proc_stage_branch:
 		end if;	
 	end process;
 
-	process(rst, clk_1)
-	variable reset_delay : unsigned (5 downto 0);
-	begin
-		if rising_edge(clk_1) then
-			if rst = '1' then
-				reset_delay := (others => '1');
-				cpu_rst <= '1';
-				run_en	<= '0';
-			elsif reset_delay /= (5 downto 0 => '0') then
-				reset_delay := reset_delay - 1;
-			else
-				cpu_rst <= '0';
-			end if;	
-			if reset_delay(reset_delay'left-1) = '0' then
-				run_en	<= '1';
-			end if;	
-		end if;
-	end process;
-
 --------------------------------------------------------------------------
 -- ID stage
 --------------------------------------------------------------------------

lib/CPUs/MIPS/src/core/mips_top.vhd

@@ -61,7 +61,7 @@ architecture rtl of mips_top is
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		halt		: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
 		int			: in  unsigned (5 downto 0);
 		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
@@ -92,6 +92,9 @@ architecture rtl of mips_top is
 	signal dmem_din			: word_t;
 	signal dmem_be			: unsigned(3 downto 0);
 
+	signal cpu_rst			: STD_LOGIC;
+	signal cpu_run			: STD_LOGIC;
+
 	COMPONENT biu
 	GENERIC
 	(
@@ -134,12 +137,31 @@ begin
 	debug(0)		<= imem_err;
 	debug(1)		<= dmem_err;
 	
+	process(CLK_I)
+	variable reset_delay : unsigned (5 downto 0);
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				reset_delay := (others => '1');
+				cpu_rst <= '1';
+				cpu_run	<= '0';
+			elsif reset_delay /= (5 downto 0 => '0') then
+				reset_delay := reset_delay - 1;
+			else
+				cpu_rst <= '0';
+			end if;	
+			if reset_delay(reset_delay'left-1) = '0' then
+				cpu_run	<= '1';
+			end if;	
+		end if;
+	end process;
+
 inst_pipeline: pipeline
 	PORT MAP
 	(
-		rst			=> RST_I,
+		rst			=> cpu_rst,
 		clk			=> CLK_I,
-		halt		=> '0',
+		ce			=> cpu_run,
 		int			=> INT,
 		imem_err	=> imem_err,
 		imem_rdy	=> imem_rdy,
@@ -164,7 +186,7 @@ inst_biu: biu
 	)
 	PORT MAP
 	(
-		RST_I			=> RST_I,
+		RST_I			=> cpu_rst,
 		CLK_I			=> CLK_I,
 		ACK_I			=> ACK_I,
 		SRDY_I			=> SRDY_I,

lib/CPUs/MIPS/src/core/mips_types.vhd

@@ -30,7 +30,7 @@ use IEEE.numeric_std.ALL;
 package mips_types is
 
 	-- Revision of the CPU
-	constant REVISION : integer := 10;
+	constant REVISION : integer := 11;
 	constant WORD_WIDTH : integer := 32;
 	
 	--Types
@@ -220,6 +220,9 @@ package mips_types is
 	end record;
 	
 	type sdu_t is record
+		imem_dep		: STD_LOGIC;
+		dmem_dep		: STD_LOGIC;
+		mul_dep			: STD_LOGIC;
 		ID_nop			: STD_LOGIC;
 		EX_nop			: STD_LOGIC;
 		MEM_nop			: STD_LOGIC;

lib/CPUs/MIPS/src/tb_mips_top.vhd

@@ -38,8 +38,8 @@ END tb_mips_top;
 ARCHITECTURE behavior OF tb_mips_top IS 
 
 	constant CLK_PERIOD 			: time := 10 ns;
-	constant SRAM_ADDR_WIDTH		: integer := 14;		-- bits
+	constant SRAM_ADDR_WIDTH		: integer := 15;		-- bits
-	constant FLASH_ADDR_WIDTH		: integer := 14;		-- bits
+	constant FLASH_ADDR_WIDTH		: integer := 15;		-- bits
 	
 	signal debug		: unsigned(1 downto 0);
 

lib/CPUs/MIPS/tools/Makefile

@@ -1,7 +1,6 @@
 CFLAGS=-O2
-
 CC=gcc
-
+PREFIX=/usr/local
 all: romgen ramgen flashgen
 
 romgen: ./src/romgen.c
@@ -11,8 +10,13 @@ ramgen: ./src/ramgen.c
 	$(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen
 
 flashgen: ./src/flashgen.c
-	$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen_little
+	$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen_el
-	$(CC) $(CFLAGS) -DTARGET_IS_BIG_ENDIAN ./src/flashgen.c -lm -o ./flashgen_big
+	$(CC) $(CFLAGS) -DTARGET_IS_BIG_ENDIAN ./src/flashgen.c -lm -o ./flashgen_eb
 
+install:
+	cp romgen $(PREFIX)/bin
+	cp ramgen $(PREFIX)/bin
+	cp flashgen_el $(PREFIX)/bin
+	cp flashgen_eb $(PREFIX)/bin
 clean:
 	rm -rf romgen* ramgen* flashgen*

lib/VGA_ctrl/src/vga_frontend.vhd

@@ -321,26 +321,19 @@ read_counter:
 
 pixel_counter:
 	process(CLK_I)
-	variable pixel_cntx	: natural range 0 to tsvga.ts_h.ncyc_scan-1;
+	variable pixel_cnt	: natural range 0 to MAX_REQUEST_CNT-1;
-	variable pixel_cnty	: natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 	begin
 		if rising_edge(CLK_I) then
 			if pixel_cnt_rst = '1' then
-				pixel_cntx	:= 0;
+				pixel_cnt	:= 0;
-				pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 			elsif request_cnt_en = '1' and SRDY_I = '1' then
-				if pixel_cntx /= tsvga.ts_h.ncyc_scan-1 then
+				if pixel_cnt /= MAX_REQUEST_CNT-1 then
-					pixel_cntx 	:= pixel_cntx + 1;
+					pixel_cnt 	:= pixel_cnt + 1;
 				else
-					pixel_cntx	:= 0;
+					pixel_cnt	:= 0;
-					if pixel_cnty /= 0 then
-						pixel_cnty 	:= pixel_cnty - tsvga.ts_h.ncyc_scan;
-					else
-						pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 				end if;	
  			end if;	
-			end if;	
+ 			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cnt, 30) & "00");
-			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cntx, 30) & "00") + (to_unsigned(pixel_cnty, 30) & "00");
 		end if;
 	end process;	
 	

lib/VGA_ctrl/src/vga_frontend64.vhd

@@ -325,26 +325,19 @@ read_counter:
 
 pixel_counter:
 	process(CLK_I)
-	variable pixel_cntx	: natural range 0 to tsvga.ts_h.ncyc_scan/2-1;
+	variable pixel_cnt	: natural range 0 to MAX_REQUEST_CNT/2-1;
-	variable pixel_cnty	: natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 	begin
 		if rising_edge(CLK_I) then
 			if pixel_cnt_rst = '1' then
-				pixel_cntx	:= 0;
+				pixel_cnt	:= 0;
-				pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 			elsif request_cnt_en = '1' and SRDY_I = '1' then
-				if pixel_cntx /= tsvga.ts_h.ncyc_scan/2-1 then
+				if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
-					pixel_cntx 	:= pixel_cntx + 1;
+					pixel_cnt 	:= pixel_cnt + 1;
 				else
-					pixel_cntx	:= 0;
+					pixel_cnt	:= 0;
-					if pixel_cnty /= 0 then
-						pixel_cnty 	:= pixel_cnty - tsvga.ts_h.ncyc_scan;
-					else
-						pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
 				end if;	
  			end if;	
-			end if;	
+ 			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cnt, 29) & "000");
-			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cntx, 29) & "000") + (to_unsigned(pixel_cnty, 30) & "00");
 		end if;
 	end process;	
 	

projects/mips_sys/ise101/mips_sys/mips_sys.prj

@@ -0,0 +1,45 @@
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/misc/singleshot.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
+vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
+vhdl work "../../src/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/misc/async_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
+vhdl work "../../src/async_defs.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
+vhdl work "../../../../lib/misc/rom_wb.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/misc/gpio_wb.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,45 @@
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
+vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\misc\async_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf

@@ -0,0 +1,503 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_ssram_a<24> LOC = T21;
+NET sys_flash_ssram_a<23> LOC = U20;
+NET sys_flash_ssram_a<22> LOC = T19;
+NET sys_flash_ssram_a<21> LOC = AC5;
+NET sys_flash_ssram_a<20> LOC = AB5;
+NET sys_flash_ssram_a<19> LOC = AC4;
+NET sys_flash_ssram_a<18> LOC = AB4;
+NET sys_flash_ssram_a<17> LOC = AB3;
+NET sys_flash_ssram_a<16> LOC = AA4;
+NET sys_flash_ssram_a<15> LOC = AA3;
+NET sys_flash_ssram_a<14> LOC = W5;
+NET sys_flash_ssram_a<13> LOC = W6;
+NET sys_flash_ssram_a<12> LOC = W3;
+NET sys_flash_ssram_a<11> LOC = AF3;
+NET sys_flash_ssram_a<10>  LOC = AE3;
+NET sys_flash_ssram_a<9>  LOC = AD2;
+NET sys_flash_ssram_a<8>  LOC = AD1;
+NET sys_flash_ssram_a<7>  LOC = AC2;
+NET sys_flash_ssram_a<6>  LOC = AC1;
+NET sys_flash_ssram_a<5>  LOC = AB2;
+NET sys_flash_ssram_a<4>  LOC = AB1;
+NET sys_flash_ssram_a<3>  LOC = AA1;
+NET sys_flash_ssram_a<2>  LOC = Y2;
+NET sys_flash_ssram_a<1>  LOC = Y1;
+NET sys_flash_ssram_a<0>  LOC = T20;
+NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_a<*>  SLEW = FAST;
+NET sys_flash_ssram_a<*>  DRIVE = 8;
+
+
+NET sys_flash_ssram_d<31> LOC = F14;
+NET sys_flash_ssram_d<30> LOC = F13;
+NET sys_flash_ssram_d<29> LOC = F12;
+NET sys_flash_ssram_d<28> LOC = F11;
+NET sys_flash_ssram_d<27> LOC = F16;
+NET sys_flash_ssram_d<26> LOC = F15;
+NET sys_flash_ssram_d<25> LOC = D14;
+NET sys_flash_ssram_d<24> LOC = D13;
+NET sys_flash_ssram_d<23> LOC = D15;
+NET sys_flash_ssram_d<22> LOC = E14;
+NET sys_flash_ssram_d<21> LOC = C11;
+NET sys_flash_ssram_d<20> LOC = D11;
+NET sys_flash_ssram_d<19> LOC = D16;
+NET sys_flash_ssram_d<18> LOC = C16;
+NET sys_flash_ssram_d<17> LOC = E13;
+NET sys_flash_ssram_d<16> LOC = D12;
+NET sys_flash_ssram_d<15> LOC = AA14;
+NET sys_flash_ssram_d<14> LOC = AB14;
+NET sys_flash_ssram_d<13> LOC = AC12;
+NET sys_flash_ssram_d<12> LOC = AC11;
+NET sys_flash_ssram_d<11> LOC = AA16;
+NET sys_flash_ssram_d<10> LOC = AA15;
+NET sys_flash_ssram_d<9>  LOC = AB13;
+NET sys_flash_ssram_d<8>  LOC = AA13;
+NET sys_flash_ssram_d<7>  LOC = AC14;
+NET sys_flash_ssram_d<6>  LOC = AD14;
+NET sys_flash_ssram_d<5>  LOC = AA12;
+NET sys_flash_ssram_d<4>  LOC = AA11;
+NET sys_flash_ssram_d<3>  LOC = AC16;
+NET sys_flash_ssram_d<2>  LOC = AC15;
+NET sys_flash_ssram_d<1>  LOC = AC13;
+NET sys_flash_ssram_d<0>  LOC = AD13;
+NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_ssram_d<*> DRIVE = 12;
+NET sys_flash_ssram_d<*> SLEW = FAST;
+NET sys_flash_ssram_d<*> PULLDOWN;
+
+NET sys_flash_ssram_oe_n     LOC = AC6;
+NET sys_flash_ssram_oe_n    IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_oe_n SLEW = FAST;
+NET sys_flash_ssram_oe_n DRIVE = 8;
+
+NET sys_flash_ssram_we_n     LOC = AB6;
+NET sys_flash_ssram_we_n    IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_we_n SLEW = FAST;
+NET sys_flash_ssram_we_n DRIVE = 8;
+
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_rstn    LOC = AD10;
+NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_rstn    DRIVE = 8;
+NET sys_flash_rstn    SLEW = FAST;
+NET sys_flash_rstn           TIG;
+
+NET sys_flash_byten   LOC = N22;
+NET sys_flash_byten          IOSTANDARD = LVCMOS33;
+NET sys_flash_byten          DRIVE = 8;
+NET sys_flash_byten          SLEW = FAST;
+NET sys_flash_byten          TIG;
+
+# SSRAM
+NET sys_ssram_clk            LOC = AF7;
+NET sys_ssram_clk            IOSTANDARD = LVCMOS33;
+NET sys_ssram_clk            DRIVE = 16;
+NET sys_ssram_clk            SLEW = FAST;
+
+NET "sys_ssram_clk" TNM_NET = "ssram_clk";
+#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
+
+
+NET sys_ssram_clk_fb         LOC = AD17;
+NET sys_ssram_clk_fb         IOSTANDARD = LVCMOS33;
+
+# Timing Constraint for Feedback Clock
+NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
+
+NET sys_ssram_ce_n           LOC = V7;
+NET sys_ssram_ce_n           IOSTANDARD = LVDCI_33;
+NET sys_ssram_ce_n           SLEW = FAST;
+NET sys_ssram_ce_n           DRIVE = 8;
+
+NET sys_ssram_bw_n<3>        LOC = Y3; #Y4; 
+NET sys_ssram_bw_n<2>        LOC = Y4; #Y3;
+NET sys_ssram_bw_n<1>        LOC = Y5; #Y6;
+NET sys_ssram_bw_n<0>        LOC = Y6; #Y5;
+NET sys_ssram_bw_n<*>        IOSTANDARD = LVDCI_33;
+NET sys_ssram_bw_n<*>        SLEW = FAST;
+NET sys_ssram_bw_n<*>        DRIVE = 8;
+
+NET sys_ssram_adv            LOC = W4;
+NET sys_ssram_adv            IOSTANDARD = LVDCI_33;
+NET sys_ssram_adv            SLEW = FAST;
+NET sys_ssram_adv            DRIVE = 8;
+
+NET sys_ssram_mode           LOC = V26;
+NET sys_ssram_mode           IOSTANDARD = LVDCI_33;
+NET sys_ssram_mode           SLEW = FAST;
+NET sys_ssram_mode           DRIVE = 8;
+
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

projects/mips_sys/ise101/mips_sys/ucf/systest.ucf

@@ -0,0 +1,500 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
+# GOOD 1
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
+
+# GOOD 2 (smaller)
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
+
+# GOOD 3 (even smaller)
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
+
+# GOOD 4 (even more smaller)
+AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
+AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_a<24> LOC = T21;
+NET sys_flash_a<23> LOC = U20;
+NET sys_flash_a<22> LOC = T19;
+NET sys_flash_a<21> LOC = AC5;
+NET sys_flash_a<20> LOC = AB5;
+NET sys_flash_a<19> LOC = AC4;
+NET sys_flash_a<18> LOC = AB4;
+NET sys_flash_a<17> LOC = AB3;
+NET sys_flash_a<16> LOC = AA4;
+NET sys_flash_a<15> LOC = AA3;
+NET sys_flash_a<14> LOC = W5;
+NET sys_flash_a<13> LOC = W6;
+NET sys_flash_a<12> LOC = W3;
+NET sys_flash_a<11> LOC = AF3;
+NET sys_flash_a<10>  LOC = AE3;
+NET sys_flash_a<9>  LOC = AD2;
+NET sys_flash_a<8>  LOC = AD1;
+NET sys_flash_a<7>  LOC = AC2;
+NET sys_flash_a<6>  LOC = AC1;
+NET sys_flash_a<5>  LOC = AB2;
+NET sys_flash_a<4>  LOC = AB1;
+NET sys_flash_a<3>  LOC = AA1;
+NET sys_flash_a<2>  LOC = Y2;
+NET sys_flash_a<1>  LOC = Y1;
+NET sys_flash_a<0>  LOC = T20;
+
+NET sys_flash_d<31> LOC = F14;
+NET sys_flash_d<30> LOC = F13;
+NET sys_flash_d<29> LOC = F12;
+NET sys_flash_d<28> LOC = F11;
+NET sys_flash_d<27> LOC = F16;
+NET sys_flash_d<26> LOC = F15;
+NET sys_flash_d<25> LOC = D14;
+NET sys_flash_d<24> LOC = D13;
+NET sys_flash_d<23> LOC = D15;
+NET sys_flash_d<22> LOC = E14;
+NET sys_flash_d<21> LOC = C11;
+NET sys_flash_d<20> LOC = D11;
+NET sys_flash_d<19> LOC = D16;
+NET sys_flash_d<18> LOC = C16;
+NET sys_flash_d<17> LOC = E13;
+NET sys_flash_d<16> LOC = D12;
+NET sys_flash_d<15> LOC = AA14;
+NET sys_flash_d<14> LOC = AB14;
+NET sys_flash_d<13> LOC = AC12;
+NET sys_flash_d<12> LOC = AC11;
+NET sys_flash_d<11> LOC = AA16;
+NET sys_flash_d<10> LOC = AA15;
+NET sys_flash_d<9>  LOC = AB13;
+NET sys_flash_d<8>  LOC = AA13;
+NET sys_flash_d<7>  LOC = AC14;
+NET sys_flash_d<6>  LOC = AD14;
+NET sys_flash_d<5>  LOC = AA12;
+NET sys_flash_d<4>  LOC = AA11;
+NET sys_flash_d<3>  LOC = AC16;
+NET sys_flash_d<2>  LOC = AC15;
+NET sys_flash_d<1>  LOC = AC13;
+NET sys_flash_d<0>  LOC = AD13;
+NET sys_flash_rdn     LOC = AC6;
+NET sys_flash_wrn     LOC = AB6;
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_ac97_rstn    LOC = AD10;
+NET sys_flash_byten   LOC = N22;
+
+NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_a<*>  SLEW = FAST;
+NET sys_flash_a<*>  DRIVE = 8;
+
+NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_d<*> DRIVE = 12;
+NET sys_flash_d<*> SLEW = FAST;
+NET sys_flash_d<*> PULLDOWN;
+
+NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
+NET sys_flash_rdn SLEW = FAST;
+NET sys_flash_rdn DRIVE = 8;
+
+NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
+NET sys_flash_wrn SLEW = FAST;
+NET sys_flash_wrn DRIVE = 8;
+
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_ac97_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_ac97_rstn    DRIVE = 8;
+NET sys_flash_ac97_rstn    SLEW = FAST;
+NET sys_flash_ac97_rstn    TIG;
+
+NET sys_flash_byten    IOSTANDARD = LVCMOS33;
+NET sys_flash_byten    DRIVE = 8;
+NET sys_flash_byten    SLEW = FAST;
+NET sys_flash_byten    TIG;
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for AC97 Sound Controller
+#------------------------------------------------------------------------------
+NET "sys_ac97_bit_clk"  TNM_NET = "ac97_clk";
+TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
+
+NET sys_ac97_bit_clk   LOC = AE10;
+NET sys_ac97_bit_clk   IOSTANDARD = LVCMOS33;
+NET sys_ac97_bit_clk   PERIOD = 80;
+NET sys_ac97_sdata_in  LOC = AD16;
+NET sys_ac97_sdata_in  IOSTANDARD = LVCMOS33;
+NET sys_ac97_sdata_out LOC = C8;
+NET sys_ac97_sdata_out SLEW = FAST;
+NET sys_ac97_ssync     LOC = D9;
+NET sys_ac97_ssync     SLEW = FAST;

projects/mips_sys/ise92/mips_sys/mips_sys.prj

@@ -0,0 +1,43 @@
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vhdl work "../../src/sys_types.vhd"
+vhdl work "../../src/ram_ld.vhd"
+vhdl work "../../src/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/misc/rom_wb.vhd"
+vhdl work "../../../../lib/misc/ram_wb.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/misc/gpio_wb.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,43 @@
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/ucf/systest.ucf

@@ -0,0 +1,469 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+# GOOD
+INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
+AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
+AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_a<24> LOC = T21;
+NET sys_flash_a<23> LOC = U20;
+NET sys_flash_a<22> LOC = T19;
+NET sys_flash_a<21> LOC = AC5;
+NET sys_flash_a<20> LOC = AB5;
+NET sys_flash_a<19> LOC = AC4;
+NET sys_flash_a<18> LOC = AB4;
+NET sys_flash_a<17> LOC = AB3;
+NET sys_flash_a<16> LOC = AA4;
+NET sys_flash_a<15> LOC = AA3;
+NET sys_flash_a<14> LOC = W5;
+NET sys_flash_a<13> LOC = W6;
+NET sys_flash_a<12> LOC = W3;
+NET sys_flash_a<11> LOC = AF3;
+NET sys_flash_a<10>  LOC = AE3;
+NET sys_flash_a<9>  LOC = AD2;
+NET sys_flash_a<8>  LOC = AD1;
+NET sys_flash_a<7>  LOC = AC2;
+NET sys_flash_a<6>  LOC = AC1;
+NET sys_flash_a<5>  LOC = AB2;
+NET sys_flash_a<4>  LOC = AB1;
+NET sys_flash_a<3>  LOC = AA1;
+NET sys_flash_a<2>  LOC = Y2;
+NET sys_flash_a<1>  LOC = Y1;
+NET sys_flash_a<0>  LOC = T20;
+
+NET sys_flash_d<31> LOC = F14;
+NET sys_flash_d<30> LOC = F13;
+NET sys_flash_d<29> LOC = F12;
+NET sys_flash_d<28> LOC = F11;
+NET sys_flash_d<27> LOC = F16;
+NET sys_flash_d<26> LOC = F15;
+NET sys_flash_d<25> LOC = D14;
+NET sys_flash_d<24> LOC = D13;
+NET sys_flash_d<23> LOC = D15;
+NET sys_flash_d<22> LOC = E14;
+NET sys_flash_d<21> LOC = C11;
+NET sys_flash_d<20> LOC = D11;
+NET sys_flash_d<19> LOC = D16;
+NET sys_flash_d<18> LOC = C16;
+NET sys_flash_d<17> LOC = E13;
+NET sys_flash_d<16> LOC = D12;
+NET sys_flash_d<15> LOC = AA14;
+NET sys_flash_d<14> LOC = AB14;
+NET sys_flash_d<13> LOC = AC12;
+NET sys_flash_d<12> LOC = AC11;
+NET sys_flash_d<11> LOC = AA16;
+NET sys_flash_d<10> LOC = AA15;
+NET sys_flash_d<9>  LOC = AB13;
+NET sys_flash_d<8>  LOC = AA13;
+NET sys_flash_d<7>  LOC = AC14;
+NET sys_flash_d<6>  LOC = AD14;
+NET sys_flash_d<5>  LOC = AA12;
+NET sys_flash_d<4>  LOC = AA11;
+NET sys_flash_d<3>  LOC = AC16;
+NET sys_flash_d<2>  LOC = AC15;
+NET sys_flash_d<1>  LOC = AC13;
+NET sys_flash_d<0>  LOC = AD13;
+NET sys_flash_rdn     LOC = AC6;
+NET sys_flash_wrn     LOC = AB6;
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_rstn    LOC = AD10;
+NET sys_flash_byten   LOC = N22;
+
+NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_a<*>  SLEW = FAST;
+NET sys_flash_a<*>  DRIVE = 8;
+
+NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_d<*> DRIVE = 12;
+NET sys_flash_d<*> SLEW = FAST;
+NET sys_flash_d<*> PULLDOWN;
+
+NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
+NET sys_flash_rdn SLEW = FAST;
+NET sys_flash_rdn DRIVE = 8;
+
+NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
+NET sys_flash_wrn SLEW = FAST;
+NET sys_flash_wrn DRIVE = 8;
+
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_rstn    DRIVE = 8;
+NET sys_flash_rstn    SLEW = FAST;
+NET sys_flash_rstn    TIG;
+
+NET sys_flash_byten    IOSTANDARD = LVCMOS33;
+NET sys_flash_byten    DRIVE = 8;
+NET sys_flash_byten    SLEW = FAST;
+NET sys_flash_byten    TIG;
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -0,0 +1,104 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+# Configs
+vcom -explicit  -93 "../src/sdram_config_sim.vhd"
+
+# Packages
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
+
+# RAMs
+vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
+
+# FIFOS
+vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
+
+# CPU
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
+
+# VGA
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+
+# UART
+vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
+
+# GPIO
+vcom -explicit  -93 "../../../lib/misc/gpio_wb.vhd"
+
+# LCD
+vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
+
+# Flash and USB
+vcom -explicit  -93 "../../../lib/misc/async_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
+vcom -explicit  -93 "../../../lib/misc/flash_port_wb.vhd"
+vcom -explicit  -93 "../src/async_defs.vhd"
+
+# Sync SRAM
+vcom -explicit  -93 "../../../lib/SSRAM/src/package_utility.vhd"
+vcom -explicit  -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
+vcom -explicit  -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
+
+# SDRAM
+vcom -explicit  -93 "../../../lib/misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
+
+# AC-97
+vcom -explicit  -93 "../../../lib/misc/singleshot.vhd"
+vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
+vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
+vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
+vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
+
+# Top and TB
+vcom -explicit  -93 "../src/mips_sys_sim.vhd"
+vcom -explicit  -93 "../src/tb_mips_sys.vhd"
+
+vsim -t 1ps   -lib work tb_mips_sys
+do {tb_mips_sys.wdo}
+view wave
+view structure
+view signals
+run 50ms

projects/mips_sys/sim/tb_mips_sys.wdo

@@ -0,0 +1,248 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider UUT
+add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
+add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
+add wave -noupdate -format Literal /tb_mips_sys/dip
+add wave -noupdate -format Literal /tb_mips_sys/btn
+add wave -noupdate -format Literal /tb_mips_sys/led
+add wave -noupdate -format Logic /tb_mips_sys/sys_rx
+add wave -noupdate -format Logic /tb_mips_sys/sys_tx
+add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
+add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
+add wave -noupdate -format Logic /tb_mips_sys/refresh
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
+add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
+add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
+add wave -noupdate -format Literal /tb_mips_sys/sys_error
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
+add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
+add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
+add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -divider Arbiter
+add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
+add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
+add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
+add wave -noupdate -divider AC97
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
+add wave -noupdate -format Logic /tb_mips_sys/ac_synced
+add wave -noupdate -divider {CPU Master}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
+add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
+add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
+add wave -noupdate -divider {VGA Master}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
+add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
+add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
+add wave -noupdate -divider BUI
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
+add wave -noupdate -divider USB
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
+add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
+add wave -noupdate -divider Flash
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
+add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
+add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
+add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
+add wave -noupdate -divider {Sync SRAM}
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
+add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
+add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
+add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
+add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
+add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
+add wave -noupdate -divider {MIPS TOP}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/badvaddr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_code
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
+add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
+add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
+add wave -noupdate -format Logic -label .cop_read /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.cop_read
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -divider {CPU DMEM}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -divider {CPU IMEM}
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -divider {User ROM}
+add wave -noupdate -divider UUT
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
+add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
+add wave -noupdate -divider I-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
+add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_mips_sys/uut/clk
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
+configure wave -namecolwidth 187
+configure wave -valuecolwidth 64
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {381220785 ps} {2601775328 ps}

projects/mips_sys/src/.directory_history

@@ -0,0 +1,4 @@
+VHDL/projects/mips_sys/src/async_defs.vhd
+
+VHDL/projects/mips_sys/src/sys_types.vhd
+VHDL/projects/mips_sys/src/async_defs.vhd

projects/mips_sys/src/mips_sys.vhd

@@ -0,0 +1,870 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+library work;
+use work.mips_types.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.vga_types.all;
+use work.async_types.all;
+use work.async_defs.all;
+
+
+ENTITY mips_sys IS
+GENERIC
+(
+	sys_freq			: integer		    := 100E6;
+	ddr_phaseshift		: integer			:= 0;
+	ddr_frequency_hz	: integer			:= 100E6
+);
+PORT
+(
+	sys_rst_n_in		: in std_logic;
+	sys_clk_in			: in std_logic;
+
+	-- Buttons and LEDs
+	sys_btn				: in unsigned(4 downto 0);
+	sys_dip				: in unsigned(7 downto 0);
+	sys_led				: out unsigned(8 downto 0);
+
+	-- UART
+	sys_rx				: in std_logic;
+	sys_tx				: out std_logic;
+
+	-- LCD
+	sys_lcd_d			: inout unsigned(3 downto 0);
+	sys_lcd_e			: out std_logic;
+	sys_lcd_rs			: out std_logic;
+	sys_lcd_rw			: out std_logic;
+
+	-- DDR SDRAM
+	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
+	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
+	sys_sdr_cke_q		: out std_logic;    -- clock enable
+	sys_sdr_cs_qn		: out std_logic;    -- /chip select
+	sys_sdr_ras_qn		: out std_logic;    -- /ras
+	sys_sdr_cas_qn		: out std_logic;    -- /cas
+	sys_sdr_we_qn		: out std_logic;    -- /write enable
+	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
+	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
+	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
+	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
+	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
+	sys_sdr_clk_fb		: in std_logic;
+	
+	-- VGA
+	sys_vga_clk			: out std_logic;
+	sys_vga_red			: out unsigned(7 downto 0);
+	sys_vga_green		: out unsigned(7 downto 0);
+	sys_vga_blue		: out unsigned(7 downto 0);
+	sys_vga_blank_n		: out std_logic;
+	sys_vga_sync_n		: out std_logic;
+	sys_vga_hsync		: out std_logic;
+	sys_vga_vsync		: out std_logic;
+
+	sys_usb_d			: inout unsigned(15 downto 0);
+	sys_usb_a			: out unsigned(1 downto 0);
+	sys_usb_csn			: out std_logic;
+	sys_usb_wrn			: out std_logic;
+	sys_usb_rdn			: out std_logic;
+	sys_usb_rstn		: out std_logic;
+	sys_usb_int			: in std_logic;
+
+	sys_flash_d			: inout unsigned(31 downto 0);
+	sys_flash_a			: out unsigned(24 downto 0);
+	sys_flash_ce		: out std_logic;
+	sys_flash_wrn		: out std_logic;
+	sys_flash_rdn		: out std_logic;
+	sys_flash_ac97_rstn	: out std_logic;
+	sys_flash_byten		: out std_logic;	
+
+	sys_ac97_sdata_in	: in  std_logic;
+	sys_ac97_bit_clk	: in  std_logic;
+	sys_ac97_sdata_out	: out std_logic;
+	sys_ac97_ssync		: out std_logic;
+
+	sys_error			: out unsigned(1 downto 0) -- indicates Errors
+	
+);
+--	attribute BUFFER_TYPE : string;
+--	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
+--	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
+
+END mips_sys;
+
+ARCHITECTURE behavior OF mips_sys IS 
+
+	COMPONENT mips_top
+	Port 
+	(
+		debug		: out unsigned(1 downto 0);
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		DAT_O		: out word_t;
+		WE_O		: out STD_LOGIC;
+		SEL_O		: out unsigned(3 downto 0);
+		CYC_O		: out STD_LOGIC;
+		STB_O		: out STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
+		INT			: in  unsigned (5 downto 0)
+		
+	);
+	END COMPONENT;
+	
+	COMPONENT rom_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT lcd_port
+	PORT 
+	(
+		rst			: in std_logic;
+		clk			: in std_logic;
+		we			: in std_logic;
+		din			: in unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		lcd_d		: inout unsigned(3 downto 0);
+		lcd_e		: out std_logic;
+		lcd_rs		: out std_logic;
+		lcd_rw		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT async_port_wb
+	GENERIC
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		byte_sel_width	: natural := 4;
+		async_timespec	: async_timespec_t
+	);
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_be	: out unsigned(byte_sel_width-1 downto 0);
+		async_rst	: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT uart_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		INT_RX_O	: out STD_LOGIC;
+		INT_TX_O	: out STD_LOGIC;
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT gpio_wb
+	PORT
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+
+		sys_gpo0	: out unsigned(31 downto 0);
+		sys_gpo1	: out unsigned(31 downto 0);
+		sys_gpi0	: in  unsigned(31 downto 0);
+		sys_gpi1	: in  unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT vga_frontend64
+	GENERIC
+	(
+		sys_freq					: integer;
+		fifo_depth					: integer;
+		fifo_almost_full_thresh		: natural;
+		fifo_almost_empty_thresh	: natural;
+		tsvga						: vga_timespec_t
+	);
+	PORT
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(7 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(63 downto 0);
+		MDAT_O			: out unsigned(63 downto 0);
+		
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+	END COMPONENT;
+
+	signal rst			: std_logic;
+	signal clk			: std_logic;
+	signal clk270		: std_logic;
+	signal clk270var	: std_logic;
+	signal rst_in		: std_logic;
+	signal int_uart_rx	: std_logic;
+	signal locked		: std_logic;
+	signal usb_addr 	: unsigned(31 downto 0);
+	signal flash_addr	: unsigned(31 downto 0);
+	signal ac97_rstn	: std_logic;
+	signal flash_rstn	: std_logic;
+
+	-- Arbiter
+	constant ARB_MAX_MASTER	: natural := 2;
+	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	
+	-- J-Bus signals
+	signal INT	 		: unsigned(5 downto 0);
+	signal MDAT_I		: word_t;
+	signal MDAT_O 		: word_t;
+	signal ADDR_O 		: word_t;
+	signal SEL_O 		: unsigned(3 downto 0);
+	signal WE_O 		: std_logic;
+	signal CYC_O 		: std_logic;
+	signal STB_O 		: std_logic;
+	signal ACK_I		: std_logic;
+	signal SRDY_I		: std_logic;
+	signal MRDY_O		: std_logic;
+
+	-- CPU Master
+	signal MRDY_O_cpu	: std_logic;
+	signal MDAT_O_cpu	: word_t;
+	signal ADDR_O_cpu	: word_t;
+	signal SEL_O_cpu	: unsigned(3 downto 0);
+	signal WE_O_cpu		: std_logic;
+	signal CYC_O_cpu	: std_logic;
+	signal STB_O_cpu	: std_logic;
+	signal SRDY_I_cpu	: std_logic;
+	signal ACK_I_cpu	: std_logic;
+
+	-- VGA Master
+	signal MRDY_O_vga	: std_logic;
+	signal ADDR_O_vga	: word_t;
+	signal SEL_O_vga	: unsigned(7 downto 0);
+	signal WE_O_vga		: std_logic;
+	signal CYC_O_vga	: std_logic;
+	signal STB_O_vga	: std_logic;
+	signal SRDY_I_vga	: std_logic;
+	signal ACK_I_vga	: std_logic;
+	signal MDAT_I_vga	: unsigned(63 downto 0);
+	signal MDAT_O_vga	: unsigned(63 downto 0);
+
+	-- Slaves
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal SDAT_O_flash	: unsigned(31 downto 0);
+
+	signal CYC_I_usb	: std_logic;
+	signal ACK_O_usb	: std_logic;
+	signal SRDY_O_usb	: std_logic;
+	signal SDAT_O_usb	: unsigned(31 downto 0);
+
+	signal CYC_I_sdram	: std_logic;
+	signal ACK_O_sdram	: std_logic;
+	signal SRDY_O_sdram	: std_logic;
+	signal SDAT_O_sdram	: unsigned(63 downto 0);
+	signal SDAT_I_sdram	: unsigned(63 downto 0);
+	signal SEL_I_sdram	: unsigned(7 downto 0);
+
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal SDAT_O_rom	: unsigned(31 downto 0);
+
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal SDAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal SDAT_O_uart	: unsigned(31 downto 0);
+
+	signal CYC_I_vga	: std_logic;
+	signal ACK_O_vga	: std_logic;
+	signal SRDY_O_vga	: std_logic;
+	signal SDAT_O_vga	: unsigned(31 downto 0);
+
+	signal INT_O_ac97	: std_logic;
+	signal CYC_I_ac97	: std_logic;
+	signal ACK_O_ac97	: std_logic;
+	signal SRDY_O_ac97	: std_logic;
+	signal SDAT_O_ac97	: unsigned(31 downto 0);
+
+	signal gpo0			: unsigned(31 downto 0);
+	signal gpo1			: unsigned(31 downto 0);
+	signal gpi0			: unsigned(31 downto 0);
+	signal gpi1			: unsigned(31 downto 0);
+
+	signal debug		: unsigned(1 downto 0);
+
+	-- DDR SDRAM
+	constant BURST_LEN		: natural := 2;
+
+	
+--	attribute rom_style: string;
+--	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
+--	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
+
+	type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
+	signal mem_area : mem_area_t;
+
+BEGIN
+
+	gpi0(4 downto 0)	<= sys_btn;
+	gpi1(7 downto 0)	<= sys_dip;
+	sys_led				<= gpo0(8 downto 0);
+	sys_error			<= debug;
+	rst_in 				<= not sys_rst_n_in;
+	rst					<= not locked;
+	sys_usb_rstn		<= not gpo1(0);
+	sys_flash_byten		<= '1';
+	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
+	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
+
+	SDAT_I_sdram		<= MDAT_O & MDAT_O;
+	SEL_I_sdram			<= "0000" & SEL_O;
+	
+	sys_flash_ac97_rstn	<= ac97_rstn and flash_rstn;
+	
+	---------------------------------------------------------------
+	-- Arbiter
+	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
+	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
+	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
+	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
+	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
+	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
+	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
+	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
+	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
+	ACK_I_cpu	<= ACK_I and arb_gnt(0);
+	ACK_I_vga	<= ACK_I and arb_gnt(1);
+	
+	arb_req(0)	<= CYC_O_cpu;
+	arb_req(1)	<= CYC_O_vga;
+	
+	MDAT_I_vga	<= SDAT_O_sdram(63 downto 32) & MDAT_I;
+	
+arbiter_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				arb_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif arb_req(arb_idx) = '0' then
+				if arb_idx /= ARB_MAX_MASTER-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				arb_gnt	<= (others => '0');
+				arb_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+	
+int_sample:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
+		end if;
+	end process;
+	
+mem_mux:
+	process(ADDR_O)
+	begin
+		mem_area	<= mem_dead;
+--		if ADDR_O(31 downto 28) = X"0" then
+--			mem_area	<= mem_flash;
+		if ADDR_O(31 downto 28) = X"A" then
+			if ADDR_O(27 downto 26) = "00" then
+				if ADDR_O(18 downto 16) = "000" then
+					mem_area	<= mem_gpio;
+				elsif ADDR_O(18 downto 16) = "001" then
+					mem_area	<= mem_uart;
+				elsif ADDR_O(18 downto 16) = "010" then
+					mem_area	<= mem_usb;
+				elsif ADDR_O(18 downto 16) = "011" then
+					mem_area	<= mem_vga;
+				elsif ADDR_O(18 downto 16) = "100" then
+					mem_area	<= mem_ac97;
+				end if;	
+			elsif ADDR_O(27 downto 26) = "01" then
+				mem_area	<= mem_flash;
+			end if;	
+		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
+			mem_area	<= mem_rom;
+--		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
+		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
+			mem_area	<= mem_sdram;
+		end if;
+	end process;	
+
+signal_mux:
+	process(mem_area, CYC_O)
+	begin
+	
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_usb		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_sdram		<= '0';
+		CYC_I_vga		<= '0';
+		CYC_I_ac97		<= '0';
+		
+		case mem_area is
+
+		when mem_gpio =>
+			CYC_I_gpio		<= CYC_O;
+
+		when mem_uart =>
+			CYC_I_uart		<= CYC_O;
+
+		when mem_flash =>
+			CYC_I_flash		<= CYC_O;
+
+		when mem_usb =>
+			CYC_I_usb		<= CYC_O;
+
+		when mem_rom =>
+			CYC_I_rom		<= CYC_O;
+
+		when mem_sdram =>
+			CYC_I_sdram		<= CYC_O;
+		
+		when mem_vga =>
+			CYC_I_vga		<= CYC_O;
+
+		when mem_ac97 =>
+			CYC_I_ac97		<= CYC_O;
+
+		when others => null;
+		
+		end case;
+		
+	end process;
+
+------------------------------------------------------------------
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
+ 	MDAT_I		<=	SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
+					SDAT_O_rom when CYC_I_rom = '1' else
+					SDAT_O_flash when CYC_I_flash = '1' else
+					SDAT_O_usb when CYC_I_usb = '1' else
+					SDAT_O_uart when CYC_I_uart = '1' else
+					SDAT_O_vga when CYC_I_vga = '1' else
+					SDAT_O_ac97 when CYC_I_ac97 = '1' else
+					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
+
+------------------------------------------------------------------
+inst_mips_top: mips_top
+	PORT MAP
+	(
+		debug			=> debug,
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		ACK_I			=> ACK_I_cpu,
+		SRDY_I			=> SRDY_I_cpu,
+		MRDY_O			=> MRDY_O_cpu,
+		CYC_O			=> CYC_O_cpu,
+		STB_O			=> STB_O_cpu,
+		WE_O			=> WE_O_cpu,
+		SEL_O			=> SEL_O_cpu,
+		DAT_I			=> MDAT_I,
+		DAT_O			=> MDAT_O_cpu,
+		ADDR_O			=> ADDR_O_cpu,
+		INT				=> INT
+	);
+
+inst_rom_wb : rom_wb
+	PORT MAP
+	(
+		CLK_I	=> clk,
+		RST_I	=> rst,
+		CYC_I	=> CYC_I_rom,
+		STB_I	=> STB_O,
+		ACK_O	=> ACK_O_rom,
+		MRDY_I	=> MRDY_O,
+		SRDY_O	=> SRDY_O_rom,
+		ADDR_I	=> ADDR_O,
+		DAT_O	=> SDAT_O_rom
+	);
+
+
+inst_lcd_port: lcd_port
+	PORT MAP
+	(
+		clk => clk,
+		rst => rst,
+		we => '0',
+		din => X"00",
+		dout => open,
+		lcd_d => sys_lcd_d,
+		lcd_e => sys_lcd_e,
+		lcd_rs => sys_lcd_rs,
+		lcd_rw => sys_lcd_rw
+	);
+	
+inst_gpio_wb : gpio_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_gpio,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_gpio,
+
+		sys_gpo0	=> gpo0,
+		sys_gpo1	=> gpo1,
+		sys_gpi0	=> gpi0,
+		sys_gpi1	=> gpi1
+	);
+
+inst_flash_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 25,
+		data_width		=> 32,
+		byte_sel_width	=> 1,
+		async_timespec	=> ts_flash
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_flash,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
+		MRDY_I		=> MRDY_O,
+		SEL_I		=> SEL_O,
+		ADDR_I		=> flash_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_flash,
+		async_a		=> sys_flash_a,
+		async_d		=> sys_flash_d,
+		async_cs	=> sys_flash_ce,
+		async_wr	=> sys_flash_wrn,
+		async_rd	=> sys_flash_rdn,
+		async_be	=> open,
+		async_rst	=> flash_rstn
+	);
+
+inst_usb_port : async_port_wb
+	GENERIC MAP
+	(
+		addr_width		=> 2,
+		data_width		=> 16,
+		byte_sel_width	=> 1,
+		async_timespec	=> ts_usb
+	)
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_usb,
+		STB_I		=> STB_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_usb,
+		SRDY_O		=> SRDY_O_usb,
+		MRDY_I		=> MRDY_O,
+		SEL_I		=> SEL_O,
+		ADDR_I		=> usb_addr,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_usb,
+		async_a		=> sys_usb_a,
+		async_d		=> sys_usb_d,
+		async_cs	=> sys_usb_csn,
+		async_wr	=> sys_usb_wrn,
+		async_rd	=> sys_usb_rdn,
+		async_be	=> open,
+		async_rst	=> open
+	);
+
+inst_uart_wb : uart_wb
+	PORT MAP
+	(
+		CLK_I		=> clk,
+		RST_I		=> rst,
+		CYC_I		=> CYC_I_uart,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_uart,
+		INT_RX_O	=> int_uart_rx,
+		INT_TX_O	=> open,
+		ser_rx		=> sys_rx,
+		ser_tx		=> sys_tx
+	);
+
+
+inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
+	GENERIC MAP
+	(
+		BL			=> BURST_LEN,
+		f_sysclk	=> ddr_frequency_hz,
+		fifo_depth	=> 5
+	)
+	PORT MAP
+	(
+		RST_I			=> rst,
+		CLK_I			=> clk,
+		CLK270_I		=> clk270,
+		CLK270VAR_I		=> clk270var,
+		
+		CYC_I			=> CYC_I_sdram,
+		STB_I			=> STB_O,
+		SEL_I			=> SEL_I_sdram,
+		WE_I			=> WE_O,
+		ACK_O			=> ACK_O_sdram,
+		MRDY_I			=> MRDY_O,
+		SRDY_O			=> SRDY_O_sdram,
+		ADDR_I			=> ADDR_O,
+		DAT_I			=> SDAT_I_sdram,
+		DAT_O			=> SDAT_O_sdram,
+
+		-- SDRAM signals
+		sd_clk_p		=> sys_sdr_clk_p,
+		sd_clk_n		=> sys_sdr_clk_n,
+		sd_cke			=> sys_sdr_cke_q,
+		sd_cs_n			=> sys_sdr_cs_qn,
+		sd_cas_n		=> sys_sdr_cas_qn,
+		sd_ras_n		=> sys_sdr_ras_qn,
+		sd_we_n			=> sys_sdr_we_qn,
+		sd_addr			=> sys_sdr_a_q,
+		sd_ba			=> sys_sdr_ba_q,
+		sd_dm			=> sys_sdr_dm_q,
+		sd_dqs			=> sys_sdr_dqs_q,
+		sd_data			=> sys_sdr_data
+		
+	);
+
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst_in,   -- external async reset, low active
+		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> open
+	);
+
+inst_vga_frontend : vga_frontend64
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 1860,
+		fifo_almost_empty_thresh	=> 256,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> rst,
+		CLK_I			=> clk,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_O_vga,
+		STB_O			=> STB_O_vga,
+		WE_O			=> WE_O_vga,
+		SEL_O			=> SEL_O_vga,
+		ACK_I			=> ACK_I_vga,
+		SRDY_I			=> SRDY_I_vga,
+		MRDY_O			=> MRDY_O_vga,
+		ADDR_O			=> ADDR_O_vga,
+		MDAT_I			=> MDAT_I_vga,
+		MDAT_O			=> MDAT_O_vga,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_I_vga,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_O_vga,
+		SRDY_O			=> SRDY_O_vga,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> MDAT_O,
+		SDAT_O			=> SDAT_O_vga,
+		
+		-- VGA signals
+		vga_clk_out		=> sys_vga_clk,
+		vga_red			=> sys_vga_red,
+		vga_green		=> sys_vga_green,
+		vga_blue		=> sys_vga_blue,
+		vga_blank_n		=> sys_vga_blank_n,
+		vga_sync_n		=> sys_vga_sync_n,
+		vga_hsync		=> sys_vga_hsync,
+		vga_vsync		=> sys_vga_vsync	
+	);
+
+inst_ac97_wb : entity work.ac97_wb
+	GENERIC MAP
+	(
+		fifo_depth		=> 8
+	)
+	PORT MAP
+	(
+		-- J-Bus domain
+		CLK_I			=> clk,
+		RST_I			=> rst,
+		CYC_I			=> CYC_I_ac97,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		ACK_O			=> ACK_O_ac97,
+		SRDY_O			=> SRDY_O_ac97,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		DAT_I			=> MDAT_O,
+		DAT_O			=> SDAT_O_ac97,
+		INT_O			=> INT_O_ac97,
+
+		-- AC97 domain
+		ac97_sdata_in	=> sys_ac97_sdata_in,
+		ac97_bit_clk	=> sys_ac97_bit_clk,          
+		ac97_reset_n	=> ac97_rstn,
+		ac97_sdata_out	=> sys_ac97_sdata_out,
+		ac97_ssync		=> sys_ac97_ssync		
+	);
+
+	------------------------------------------------------------------
+END;

projects/mips_sys/src/ram_ld.vhd

@@ -0,0 +1,173 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY ram IS
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	COMPONENT dpram_2w2r
+	Generic 
+	(
+		addr_width : integer;
+		data_width : integer
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+	
+	signal jtag_clk		: STD_LOGIC;
+	signal jtag_we		: unsigned(3 downto 0);
+	signal jtag_addr	: unsigned (15 downto 0);
+	signal jtag_dout	: unsigned (31 downto 0);
+	signal jtag_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	
+BEGIN
+
+gen_sram:
+	for i in 0 to 3 generate
+	begin
+	inst_dpram_2w2r : dpram_2w2r
+		GENERIC MAP
+		(
+			addr_width	=> 11,
+			data_width	=> 8
+		)
+		PORT MAP
+		(
+			clk_a		=> clk,
+			en_a		=> ce,
+			we_a		=> we(i),
+			addr_a		=> addr(12 downto 2),
+			din_a		=> din((i+1)*8-1 downto i*8),
+			dout_a		=> dout((i+1)*8-1 downto i*8),
+
+			clk_b		=> jtag_clk,
+			en_b		=> jtag_we(i),
+			we_b		=> jtag_we(i),
+			addr_b		=> jtag_addr(10 downto 0),
+			din_b		=> jtag_din((i+1)*8-1 downto i*8),
+			dout_b		=> jtag_dout((i+1)*8-1 downto i*8)
+		);
+	end generate;
+	
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_addr	<= user_regi(user_regi'left downto jtag_dout'length);
+	jtag_din	<= user_regi(jtag_dout'length-1 downto 0);
+	jtag_clk	<= bs_update1;
+	jtag_we		<= (3 downto 0 => bs_sel);
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+end behavior;

projects/mips_sys/src/ram_sim.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram(index)(7 downto 0)		<= din(7 downto 0);
+			end if;	
+			if we(1) = '1' then
+				sram(index)(15 downto 8)	<= din(15 downto 8);
+			end if;	
+			if we(2) = '1' then
+				sram(index)(23 downto 16)	<= din(23 downto 16);
+			end if;	
+			if we(3) = '1' then
+				sram(index)(31 downto 24)	<= din(31 downto 24);
+			end if;	
+			dout <= sram(index);
+		end if;	
+	end process;
+	
+end behavior;

projects/mips_sys/src/sdram_config.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+	
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+	
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+	
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 5;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 222; -- µs
+
+	subtype user_tag_t is unsigned(3 downto 0);
+
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

projects/mips_sys/src/sdram_config_sim.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+	
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+	
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+	
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 5;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 22; -- µs
+
+	subtype user_tag_t is unsigned(3 downto 0);
+
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

projects/mips_sys/src/sys_types.vhd

@@ -0,0 +1,64 @@
+-------------------------------------------------------------------------
+-- Project: MIPS System controller
+-- This file: 
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.async_types.all;
+
+package async_defs is
+
+	constant ts_flash : async_timespec_t :=
+	(
+		ncyc_access				=> 1,
+		ncyc_pulse_rd			=> 12,
+		ncyc_pulse_wr			=> 7,
+		ncyc_cs_hold			=> 1,
+		ncyc_release			=> 1,
+		ncyc_pulse_rst			=> 8,
+		pol_cs					=> '1',
+		pol_oe					=> '0',
+		pol_we					=> '0',
+		pol_be					=> '0',
+		pol_rst					=> '0'
+	);
+
+	constant ts_usb : async_timespec_t :=
+	(
+		ncyc_access				=> 1,
+		ncyc_pulse_rd			=> 6,
+		ncyc_pulse_wr			=> 6,
+		ncyc_cs_hold			=> 1,
+		ncyc_release			=> 6,
+		ncyc_pulse_rst			=> 8,
+		pol_cs					=> '0',
+		pol_oe					=> '0',
+		pol_we					=> '0',
+		pol_be					=> '0',
+		pol_rst					=> '0'
+	);
+
+	----------------------------------------------------------------------------------------------
+	
+end async_defs;

projects/mips_sys/src/tb_mips_sys.vhd

@@ -0,0 +1,339 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+ENTITY tb_mips_sys IS
+END tb_mips_sys;
+
+ARCHITECTURE behavior OF tb_mips_sys IS 
+
+	constant CLK_PERIOD			: time := 10 ns;
+	constant AC97_CLK_PERIOD	: time := 83 ns;
+	signal sys_rst_n_in : std_logic := '0';
+	signal sys_clk_in : std_logic := '1';
+	signal dip  : unsigned(7 downto 0) := (others => '0');
+	signal btn  : unsigned(4 downto 0) := (others => '0');
+	signal led : unsigned(8 downto 0);
+	signal sys_rx : std_logic := '1';
+	signal sys_tx : std_logic;
+	
+	signal sys_lcd_d			: unsigned(3 downto 0);
+	signal sys_lcd_e			: std_logic;
+	signal sys_lcd_rs			: std_logic;
+	signal sys_lcd_rw			: std_logic;
+
+	signal refresh        : boolean:= true;
+
+	signal sys_sdr_clk_p		: std_logic;    -- ddr_sdram_clock
+	signal sys_sdr_clk_n		: std_logic;    -- /ddr_sdram_clock
+	signal sys_sdr_cke_q		: std_logic;    -- clock enable
+	signal sys_sdr_cs_qn		: std_logic;    -- /chip select
+	signal sys_sdr_ras_qn		: std_logic;    -- /ras
+	signal sys_sdr_cas_qn		: std_logic;    -- /cas
+	signal sys_sdr_we_qn		: std_logic;    -- /write enable
+	signal sys_sdr_dm_q			: unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
+	signal sys_sdr_dqs_q		: unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
+	signal sys_sdr_ba_q			: unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
+	signal sys_sdr_a_q			: unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
+	signal sys_sdr_data			: unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
+
+	signal sys_error			: unsigned(1 downto 0); -- indicates DCM Errors
+	signal sys_sdr_clk_fb		: std_logic;
+
+	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
+	signal sys_usb_a			: unsigned(1 downto 0);
+	signal sys_usb_csn			: std_logic;
+	signal sys_usb_wrn			: std_logic;
+	signal sys_usb_rdn			: std_logic;
+	signal sys_usb_rstn			: std_logic;
+	signal sys_usb_int			: std_logic := '0';
+	
+	signal sys_flash_ssram_d	: word_t;
+	signal sys_flash_ssram_a	: unsigned(24 downto 0);
+	signal sys_flash_ssram_we_n	: std_logic;
+	signal sys_flash_ssram_oe_n	: std_logic;
+
+	signal sys_flash_ce			: std_logic;
+	signal sys_flash_ac97_rstn	: std_logic;
+	signal sys_flash_byten		: std_logic;
+
+	signal sys_ssram_clk_fb		: std_logic;
+	signal sys_ssram_clk		: std_logic;
+	signal sys_ssram_cke_n		: std_logic;
+	signal sys_ssram_ce_n		: std_logic;
+	signal sys_ssram_bw_n		: unsigned(3 downto 0);
+	signal sys_ssram_dp			: unsigned(3 downto 0);
+	signal sys_ssram_adv		: std_logic;
+	signal sys_ssram_mode		: std_logic;
+	signal sys_ssram_zz			: std_logic;
+
+	SIGNAL sys_ac97_bit_clk		:  std_logic := '0';
+	SIGNAL sys_ac97_sdata_out	:  std_logic;
+	SIGNAL sys_ac97_ssync		:  std_logic;
+	SIGNAL sys_ac97_sdata_in	:  std_logic;
+
+	signal flash_reg			: word_t;
+
+	type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
+	signal flash_data : flash_data_t;
+
+	signal	ac_frame_reg		: unsigned(255 downto 0) := (others => '0');
+	signal	ac_left				: unsigned(17 downto 0) := X"0000" & "00";
+	signal	ac_right			: unsigned(17 downto 0) := X"0000" & "01";
+	signal  ac_synced			:  std_logic;
+	
+BEGIN
+
+uut: entity work.mips_sys
+--	GENERIC MAP
+--	(
+--		ddr_phaseshift => 90,
+--		ddr_frequency_hz => 100E6
+--	)
+	PORT MAP
+	(
+		sys_rst_n_in			=> sys_rst_n_in,
+		sys_clk_in				=> sys_clk_in,
+		sys_btn					=> btn,
+		sys_dip					=> dip,
+		sys_led					=> led,
+
+		sys_rx					=> sys_rx,
+		sys_tx					=> sys_tx,
+
+		sys_lcd_d				=> sys_lcd_d,
+		sys_lcd_e				=> sys_lcd_e,
+		sys_lcd_rs				=> sys_lcd_rs,
+		sys_lcd_rw				=> sys_lcd_rw,
+
+		sys_sdr_clk_p			=> sys_sdr_clk_p,
+		sys_sdr_clk_n			=> sys_sdr_clk_n,
+		sys_sdr_cke_q			=> sys_sdr_cke_q,
+		sys_sdr_clk_fb			=> sys_sdr_clk_fb,
+		sys_sdr_cs_qn			=> sys_sdr_cs_qn,
+		sys_sdr_ras_qn			=> sys_sdr_ras_qn,
+		sys_sdr_cas_qn			=> sys_sdr_cas_qn,
+		sys_sdr_we_qn			=> sys_sdr_we_qn,
+		sys_sdr_dm_q			=> sys_sdr_dm_q,
+		sys_sdr_dqs_q			=> sys_sdr_dqs_q,
+		sys_sdr_ba_q			=> sys_sdr_ba_q,
+		sys_sdr_a_q				=> sys_sdr_a_q,
+		sys_sdr_data			=> sys_sdr_data,
+
+		sys_usb_d				=> sys_usb_d,
+		sys_usb_a				=> sys_usb_a,
+		sys_usb_csn				=> sys_usb_csn,
+		sys_usb_wrn				=> sys_usb_wrn,
+		sys_usb_rdn				=> sys_usb_rdn,
+		sys_usb_rstn			=> sys_usb_rstn,
+		sys_usb_int				=> sys_usb_int,
+
+		sys_flash_ssram_d		=> sys_flash_ssram_d,
+		sys_flash_ssram_a		=> sys_flash_ssram_a,
+		sys_flash_ssram_we_n	=> sys_flash_ssram_we_n,
+		sys_flash_ssram_oe_n	=> sys_flash_ssram_oe_n,
+		sys_flash_ce			=> sys_flash_ce,
+		sys_flash_ac97_rstn		=> sys_flash_ac97_rstn,
+		sys_flash_byten			=> sys_flash_byten,
+
+		sys_ssram_clk_fb		=> sys_ssram_clk_fb,
+		sys_ssram_clk			=> sys_ssram_clk,
+		sys_ssram_cke_n			=> sys_ssram_cke_n,
+		sys_ssram_ce_n			=> sys_ssram_ce_n,
+		sys_ssram_bw_n			=> sys_ssram_bw_n,
+		sys_ssram_dp			=> sys_ssram_dp,
+		sys_ssram_adv			=> sys_ssram_adv,
+		sys_ssram_mode			=> sys_ssram_mode,
+		sys_ssram_zz			=> sys_ssram_zz,
+
+		sys_ac97_bit_clk		=> sys_ac97_bit_clk,
+		sys_ac97_sdata_out		=> sys_ac97_sdata_out,
+		sys_ac97_ssync			=> sys_ac97_ssync,
+		sys_ac97_sdata_in		=> sys_ac97_sdata_in,
+
+		sys_error 				=> sys_error
+	);
+
+inst_ssram : entity work.cy7c1354
+    PORT MAP 
+    (
+		Dq		=> STD_LOGIC_VECTOR(sys_flash_ssram_d),   	-- Data I/O
+		Dpq		=> STD_LOGIC_VECTOR(sys_ssram_dp),   	-- Data I/O
+		Addr	=> STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)),   	-- Address
+		Mode	=> sys_ssram_mode, 	-- Burst Mode
+		Clk		=> sys_ssram_clk,      -- Clk
+		CEN_n	=> sys_ssram_cke_n,                                   -- CEN#
+		AdvLd_n	=> sys_ssram_adv,                                   -- Adv/Ld#
+		Bwa_n	=> sys_ssram_bw_n(0),                                   -- Bwa#
+		Bwb_n	=> sys_ssram_bw_n(1),                                   -- BWb#
+		Bwc_n	=> sys_ssram_bw_n(2),                                   -- Bwc#
+		Bwd_n	=> sys_ssram_bw_n(3),                                   -- BWd#
+		Rw_n	=> sys_flash_ssram_we_n,                                   -- RW#
+		Oe_n	=> sys_flash_ssram_oe_n,                                   -- OE#
+		Ce1_n	=> sys_ssram_ce_n,                                   -- CE1#
+		Ce2		=> '1',                                   -- CE2
+		Ce3_n	=> '0',                                   -- CE3#
+		Zz		=> sys_ssram_zz
+    );
+    
+-- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16 
+      port map (
+         dq    => std_logic_vector(sys_sdr_data(15 downto 0)),
+         dqs   => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
+         addr  => std_logic_vector(sys_sdr_a_q),
+         ba    => std_logic_vector(sys_sdr_ba_q),
+         clk   => sys_sdr_clk_p,
+         clk_n => sys_sdr_clk_n,
+         cke   => sys_sdr_cke_q,
+         cs_n  => sys_sdr_cs_qn,
+         ras_n => sys_sdr_ras_qn,
+         cas_n => sys_sdr_cas_qn,
+         we_n  => sys_sdr_we_qn,
+         dm    => std_logic_vector(sys_sdr_dm_q(1 downto 0))
+         );
+
+-- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16 
+      port map (
+         dq    => std_logic_vector(sys_sdr_data(31 downto 16)),
+         dqs   => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
+         addr  => std_logic_vector(sys_sdr_a_q),
+         ba    => std_logic_vector(sys_sdr_ba_q),
+         clk   => sys_sdr_clk_p,
+         clk_n => sys_sdr_clk_n,
+         cke   => sys_sdr_cke_q,
+         cs_n  => sys_sdr_cs_qn,
+         ras_n => sys_sdr_ras_qn,
+         cas_n => sys_sdr_cas_qn,
+         we_n  => sys_sdr_we_qn,
+         dm    => std_logic_vector(sys_sdr_dm_q(3 downto 2))
+         );
+
+	sys_sdr_clk_fb		<= sys_sdr_clk_p after 2300 ps;
+	sys_ssram_clk_fb	<= sys_ssram_clk after 0.5 ns;
+	
+	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
+
+	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
+	
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		sys_clk_in <= not sys_clk_in;
+	end process;
+
+
+	sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
+
+ac97_data_gen :
+	PROCESS(sys_ac97_bit_clk)
+	begin
+		if rising_edge(sys_ac97_bit_clk) then
+			ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
+			if sys_flash_ac97_rstn = '0' then
+				ac_synced	<= '0';
+			elsif sys_ac97_ssync = '1' then
+				if ac_synced = '0' then
+					ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
+					ac_left <= ac_left + 2;
+					ac_right <= ac_right + 2;
+					ac_synced	<= '1';
+				end if;	
+			else	
+				ac_synced	<= '0';
+			end if;
+		end if;	
+	END PROCESS;
+
+ac97_clk_gen : PROCESS
+	begin
+		if (sys_flash_ac97_rstn = '0') then
+			sys_ac97_bit_clk <= '0';
+			wait until sys_flash_ac97_rstn = '1';
+			wait for 150 us;
+		end if;	
+		wait for AC97_CLK_PERIOD/2;
+		sys_ac97_bit_clk <= not sys_ac97_bit_clk;
+	END PROCESS;
+
+FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
+	type file_t is file of integer;
+	file load_flash : file_t open read_mode is "test_ac97.flash.bin";
+	variable instr : integer;
+	variable index : natural;
+	variable temp : signed(31 downto 0);
+	begin
+		if sys_rst_n_in = '0' then
+			index := 0;
+			while not endfile(load_flash) loop
+				read(load_flash, instr);
+				temp	:= to_signed(instr, word_t'length);
+				flash_data(index) <= unsigned(temp);
+				index := index + 1;
+			end loop;
+		else
+	 		sys_flash_ssram_d <= (others => 'Z') after 10 ns;
+			if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
+				index := to_integer(sys_flash_ssram_a(24 downto 1));
+				sys_flash_ssram_d <= flash_data(index) after 10 ns;
+			end if;	
+		end if;	
+	end process;
+
+FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
+	begin
+		if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
+			flash_reg <= sys_flash_ssram_d;
+		end if;
+	end process;
+		
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		sys_rst_n_in <= '1';
+		wait for 200000*CLK_PERIOD;
+		
+		loop
+		wait for 251*CLK_PERIOD;
+		btn(4)		<= '1';			
+		wait for 311*CLK_PERIOD;
+		btn(4)		<= '0';			
+		end loop;
+		wait; 
+	
+	end process;
+	
+END;

projects/mips_sys/tools/insrom.rb

@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2008 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end

projects/mips_sys/tools/irom.vhd.tpl

@@ -0,0 +1,29 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- ROM_INSERT_HERE
+

projects/mips_sys/tools/irom_ld.vhd.tpl

@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

projects/mips_sys/tools/make

@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip

projects/mips_sys/tools/rom.tcl.tpl

@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

projects/mips_sys/tools/src/flashgen.c

@@ -0,0 +1,117 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define INT8    char
+#define INT16   short
+#define INT32   long
+#define UINT8   unsigned char
+#define UINT16  unsigned short
+#define UINT32  unsigned long
+#define INT     int
+#define UINT    unsigned int
+#define FLOAT32 float
+#define FLOAT64 double
+
+#define SDRAM_BASE			0x40000000
+#define	FLASH_OFFSET		0x00000000
+
+// --------------------------------------------------------------
+typedef struct _sflash_img_hdr_t
+{
+	UINT8 magic[4];
+	UINT32 target_addr;
+	UINT32 img_offset;
+	UINT32 img_size;
+	UINT32 hdr_next;
+	UINT8 img_name[128];
+	UINT8 res[108];
+
+} flash_img_hdr_t;
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+// --------------------------------------------------------------
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_flash[1024];
+	char name_prj[1024];
+	char *pBuf;
+	flash_img_hdr_t img_hdr = {0};
+
+	FILE *pFile;
+	int filesize;
+	long start, end;
+	int i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: flashgen <input file>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	pFile = fopen(pFilenameIn, "rb");
+	if (!pFile)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_flash, "%s.flash.bin", name_prj);
+
+	// determine filesize
+	fseek(pFile, 0, SEEK_SET);
+	start = ftell(pFile);
+	fseek(pFile, 0, SEEK_END);
+	end = ftell(pFile);
+	fseek(pFile, 0, SEEK_SET);
+	filesize = (end-start);
+
+	pBuf = (char*)malloc(filesize);
+	fread(pBuf, 1, filesize, pFile);
+
+	fclose(pFile);
+
+	pFile = fopen(name_flash, "wb");
+	if (!pFile)
+	{
+		fprintf(stderr, "Error opening file %s\n", name_flash);
+		return 1;
+	}
+
+	img_hdr.magic[0] = 'J';
+	img_hdr.magic[1] = 'F';
+	img_hdr.magic[2] = 'I';
+	img_hdr.magic[3] = '1';
+	img_hdr.target_addr = SDRAM_BASE;
+	img_hdr.img_size = filesize;
+	img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
+	img_hdr.hdr_next = FLASH_OFFSET;
+
+	fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
+	fwrite(pBuf, 1, filesize, pFile);
+
+	fclose(pFile);
+
+	return 0;
+}
+

projects/mips_sys/tools/src/ramgen.c

@@ -0,0 +1,385 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"ram"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 2\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom_tcl[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+

projects/mips_sys/tools/src/romgen.c

@@ -0,0 +1,368 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"rom"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 1\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+	char name_rom_tcl[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+