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base: jens/vhdl:BRANCH_MIPS_R14
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
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compare: jens/vhdl:MIPS_R11
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
1 Commits
BRANCH_MIPS_R14 .. MIPS_R11
Author SHA1 Message Date
jens f394d45220 This commit was manufactured by cvs2svn to create tag 'MIPS_R11'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R11@377 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-03-01 18:32:41 +00:00
1786 changed files with 42785 additions and 1264180 deletions
Expand all files Collapse all files
Common/make/ghdl.mk
-127
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@@ -1,127 +0,0 @@
# -------------------------------------------------
# User options
# -------------------------------------------------
# SRCS
# WITH_VCD
# WITH_GHW
TARGET ?= default
ENTITY ?= default
WORK_LIB ?= work
LANG_STD ?= 93c
IEEE_STD ?= standard
RUN_TIME ?= 1000ns
WAVE_FORMAT ?= fst
# Build path
BUILD_DIR ?= build/$(TARGET)
WORK_DIR ?= $(BUILD_DIR)/$(WORK_LIB)
# Can be pre-initialized by user
RUN_OPTS += --stop-time=$(RUN_TIME)
GHDL_OPTS += --work=$(WORK_LIB) --workdir=$(WORK_DIR) --std=$(LANG_STD) --ieee=$(IEEE_STD)
# -------------------------------------------------
# Make unique
# -------------------------------------------------
define uniq =
$(eval seen :=)
$(foreach _,$1,$(if $(filter $_,${seen}),,$(eval seen += $_)))
${seen}
endef
SRCS := $(abspath $(SRCS))
SRCS := $(call uniq,$(SRCS))
SRCS := $(filter-out ,$(SRCS))
#$(info ----------------------)
#$(info $(SRCS))
#$(info ----------------------)
# -------------------------------------------------
# GHDL binary
# -------------------------------------------------
GHDL := ghdl
GHDL_GCC := ghdl-gcc
# Wave format selection
SIM_FILE-vcd := $(BUILD_DIR)/$(TARGET).vcd
GTK_OPTS-vcd := --vcd=$(SIM_FILE-vcd)
SIM_FILE-fst := $(BUILD_DIR)/$(TARGET).fst
GTK_OPTS-fst := --fst=$(SIM_FILE-fst)
SIM_FILE-ghw := $(BUILD_DIR)/$(TARGET).ghw
GTK_OPTS-ghw := --wave=$(SIM_FILE-ghw) --read-wave-opt=$(TARGET).wopt
SIM_FILE := $(SIM_FILE-$(WAVE_FORMAT))
GTK_OPTS := $(GTK_OPTS-$(WAVE_FORMAT))
# -------------------------------------------------
# Targets
# -------------------------------------------------
all: analyze
$(WORK_DIR):
mkdir -p $@
syntax:
$(GHDL) -s $(GHDL_OPTS) $(SRCS)
import:
$(GHDL) -i $(GHDL_OPTS) $(SRCS)
analyze: $(WORK_DIR) $(SRCS)
$(GHDL) -a $(GHDL_OPTS) $(SRCS)
html: $(WORK_DIR) $(SRCS)
$(GHDL) --pp-html $(GHDL_OPTS) $(SRCS) >$(BUILD_DIR)/$(TARGET).html
anaborate: $(WORK_DIR) $(SRCS)
$(GHDL) -c $(GHDL_OPTS) -o $(BUILD_DIR)/$(TARGET) $(SRCS) -e $(ENTITY)
makeunit: analyze
$(GHDL) -m $(GHDL_OPTS) $(ENTITY)
elaborate: analyze
$(GHDL) -e $(GHDL_OPTS) $(ENTITY)
run: analyze
$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS)
run_wave: analyze
$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS) $(GTK_OPTS) >$(BUILD_DIR)/$(TARGET).log
synth: analyze
$(GHDL) --synth $(GHDL_OPTS) $(ENTITY)
wave: run_wave
exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
result:
exec gtkwave -f $(SIM_FILE) -a $(TARGET).gtkw &
tree: analyze
$(GHDL) -r $(GHDL_OPTS) $(ENTITY) $(RUN_OPTS) --no-run --disp-tree=inst
genwopt: analyze
rm -rf $(TARGET).wopt.templ
$(GHDL) -r $(GHDL_OPTS) $(ENTITY) --stop-time=0ps --write-wave-opt=$(TARGET).wopt.templ --wave=$(BUILD_DIR)/$(TARGET).ghw
.PHONY: list
INSTR = $(foreach number,$(SRCS),echo $(number);)
list:
@$(INSTR)
clean:
rm -rf $(WORK_DIR)
rm -f $(BUILD_DIR)/$(TARGET)*.vcd
rm -f $(BUILD_DIR)/$(TARGET)*.fst
rm -f $(BUILD_DIR)/$(TARGET)*.ghw
rm -f $(BUILD_DIR)/$(TARGET)*.log
rm -f $(BUILD_DIR)/$(TARGET)*.o
mrproper:
rm -rf $(BUILD_DIR)
Common/make/ise.mk
-58
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@@ -1,58 +0,0 @@
.PHONY: clean
all: bit
netlist: $(PRJ).ngc
translate: $(PRJ).ngd
map: $(PRJ)_map.ncd
par: $(PRJ).ncd
bit: $(PRJ).bit
prom : $(PRJ).mcs
timing : $(PRJ).twr
NETLIST_DIR ?= ./
MAP_EFFORT ?= high
PAR_EFFORT ?= high
BUILD_DIR := ./
XST_DIR := $(BUILD_DIR)/xst/tmp
DIRS := $(XST_DIR)
# Netlist
$(PRJ).ngc: $(DIRS) $(PREQ) ./project/$(PRJ).ucf
xst -intstyle xflow -ifn ./project/$(PRJ).xst
# Translate
$(PRJ).ngd: $(NETLISTS) $(PRJ).ngc ./project/$(PRJ).ucf
ngdbuild -p $(DEVICE) -sd $(NETLIST_DIR) -dd _ngo -nt timestamp -uc ./project/$(PRJ).ucf $(PRJ).ngc $(PRJ).ngd
# Map
$(PRJ)_map.ncd: $(PRJ).ngd
map -intstyle xflow -p $(DEVICE) -timing -logic_opt on -ol $(MAP_EFFORT) -t 1 -register_duplication -cm area -ignore_keep_hierarchy -pr off -k 4 -power off -o $(PRJ)_map.ncd $(PRJ).ngd $(PRJ).pcf
# PAR
$(PRJ).ncd: $(PRJ)_map.ncd
par -w -intstyle xflow -ol $(PAR_EFFORT) -t 1 $(PRJ)_map.ncd $(PRJ).ncd $(PRJ).pcf
# Timing
$(PRJ).twr: $(PRJ).ncd $(PRJ).pcf ./project/$(PRJ).ucf
trce -intstyle xflow -v 3 $(PRJ).ncd -ucf ./project/$(PRJ).ucf -o $(PRJ).twr $(PRJ).pcf
# Bitgen
$(PRJ).bit: $(PRJ).ncd ./project/$(PRJ).ut
bitgen -intstyle xflow -f ./project/$(PRJ).ut $(PRJ).ncd
# Promgen
$(PRJ).mcs: $(PRJ).bit
promgen -w -p mcs -c FF -o $(PRJ) -ver 0 $(PRJ).bit -x xcf32p
$(DIRS):
mkdir -p $(DIRS)
clean:
rm -rf ./_ngo
rm -rf ./xst
rm -rf ./xlnx_auto_0_xdb
rm -f xlnx_auto_0.ise
rm -f smartpreview.twr
rm -f $(PRJ)*.*
Common/make/package_new.inc
-14
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@@ -1,14 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -----------------------------------------------------------
include package_other.inc
# -----------------------------------------------------------
PKG_NAME := PACKAGE_NEW
# -----------------------------------------------------------
$(PKG_NAME)_SRCS += $(PKG_OTHER_SRC)
$(PKG_NAME)_SRCS += $(LIB_PATH)/pkg_new.vhd
# -----------------------------------------------------------
Common/make/tb_new.make
-21
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@@ -1,21 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -----------------------------------------------------------
include package1.inc
include package2.inc
# -----------------------------------------------------------
SRCS := $(PACKAGE1_SRCS)
SRCS += $(PACKAGE2_SRCS)
SRCS += $(LIB_PATH)/tb_new.vhd
# -----------------------------------------------------------
# Compile
TARGET := tb_new
ENTITY := tb_new
WITH_VCD := y
RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk
# -----------------------------------------------------------
Common/sim/.gitignore.templ
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@@ -1,4 +0,0 @@
.gitignore
build/
.gitignore
build/
Common/sim/ModelSim SE .lnk
BIN
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Binary file not shown.
Common/sim/altera/libsrc/altera/alt_cusp_package.vhd
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@@ -1,4 +0,0 @@
PACKAGE ALT_CUSP_PACKAGE IS
END ALT_CUSP_PACKAGE;
Common/sim/altera/libsrc/altera/alt_dspbuilder_package.vhd
-1738
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File diff suppressed because it is too large Load Diff
Common/sim/altera/libsrc/altera/altera_europa_support_lib.vhd
-689
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@@ -1,689 +0,0 @@
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- --
-- Description: Declares utility package for Altera IP support --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
package altera_europa_support_lib is
attribute IS_SIGNED : BOOLEAN ;
attribute SYNTHESIS_RETURN : STRING ;
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION A_SRL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SRL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR) return Std_Logic;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC;
-- Result subtype: STD_LOGIC
-- Result: Converts a BOOLEAN to a STD_LOGIC..
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
function a_min(L, R: INTEGER) return INTEGER ;
function a_max(L, R: INTEGER) return INTEGER ;
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
-- All required padding is to the left of the value (right justified) to
-- a string that can hold the maximum value of the vector in that radix.
-- When displaying decimal values (e.g. %d), padding is spaces.
-- When displaying other radices (e.g. %h), padding is zeros.
-- There is no padding when a zero is placed after the % (e.g. %0d or %0h).
type pad_type is (pad_none, pad_spaces, pad_zeros);
function to_hex_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : integer;
pad : pad_type := pad_spaces) return string;
function to_decimal_string(val : std_logic_vector;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_hex_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : std_logic;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
end altera_europa_support_lib;
package body altera_europa_support_lib is
--
-- Reducing logical functions.
--
FUNCTION and_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION or_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result OR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NOR" ;
BEGIN
result := NOT or_reduce(arg);
RETURN result;
END;
FUNCTION xor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result XOR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION xnor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_XNOR" ;
BEGIN
result := NOT xor_reduce(arg);
RETURN result;
END;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC is
begin
if(arg = true) then
return('1');
else
return('0');
end if;
end;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SRL(arg,conv_integer(shift)));
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SLL(arg,conv_integer(shift)));
END;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT - shift DOWNTO 0) := arg(arg'LEFT DOWNTO shift);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT DOWNTO shift) := arg(arg'LEFT - shift DOWNTO 0);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector IS
BEGIN
IF a = '1' THEN
return "1";
ELSE
return "0";
END IF;
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector IS
BEGIN
return a;
END;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR)
return Std_Logic IS
BEGIN
return (vector(vector'right));
END;
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(repeat-1 DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result(i) := arg;
end LOOP;
RETURN(result);
END;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR(((repeat * (arg_copy'LEFT+1))-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result((((arg_copy'left + 1) * i) + arg_copy'left) downto ((arg_copy'left + 1) * i)) := arg_copy(arg_copy'LEFT DOWNTO 0);
end LOOP;
RETURN(result);
END;
-- a_min : return the minimum of two integers;
function a_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- a_max : return the minimum of two integers;
function a_max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
-- a_ext is the Altera version of the EXT function. It is used to both
-- zero-extend a signal to a new length, and to extract a signal of 'size'
-- length from a larger signal.
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
VARIABLE bits_to_copy : integer := 0;
VARIABLE arg_length : integer := arg'length ;
VARIABLE LSB_bit : integer := 0;
BEGIN
bits_to_copy := a_min(arg_length, size);
FOR i IN 0 TO (bits_to_copy - 1) LOOP
result(i) := arg_copy(i);
end LOOP;
RETURN(result);
END;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
subtype slv4 is std_logic_vector(1 to 4);
subtype slv3 is std_logic_vector(1 to 3);
-- Remove leading zeros. Also changes strings of all 'x' or 'z' to one char.
-- This handles the %0<radix> kind of Verilog syntax in the format string.
-- Examples:
-- input output
-- ----- -----------
-- 001f 1f
-- 0000 0
-- xxxx x
-- zzzz z
-- xxzz xxzz
function do_pad_none(
str_in : string) return string is
variable start : integer;
variable all_x : boolean := true;
variable all_z : boolean := true;
begin
-- Nothing to remove if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
case str_in(i) is
when 'X' | 'x' => all_z := false;
when 'Z' | 'z' => all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x or all_z) then
return str_in(str_in'left to str_in'left);
end if;
-- Find index of first non-zero character.
for i in str_in'range loop
start := i;
exit when (str_in(i) /= '0');
end loop;
return str_in(start to str_in'right);
end do_pad_none;
-- Replace leading zeros with spaces.
-- This handles the %d kind of Verilog syntax in the format string.
function replace_leading_zeros(
str_in : string;
c : character) return string is
variable str_out : string(str_in'range) := str_in;
begin
-- Nothing to replace if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
if (str_in(i) = '0') then
str_out(i) := c;
else
exit;
end if;
end loop;
return str_out;
end replace_leading_zeros;
function do_pad(
str : string;
pad : pad_type) return string is
begin
case pad is
when pad_none => return do_pad_none(str);
when pad_spaces => return replace_leading_zeros(str, ' ');
when pad_zeros => return str;
end case;
end do_pad;
function round_up_to_multiple(
val : integer;
size : integer) return integer is
begin
return ((val + size - 1) / size) * size;
end round_up_to_multiple;
function to_hex_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,4);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/4)+1 := 1;
variable str : string(1 to ext_len/4) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 4 /= 1;
case slv4(to_x01z(val_ext(i to i+3))) is
when "0000" => str(ptr) := '0';
when "0001" => str(ptr) := '1';
when "0010" => str(ptr) := '2';
when "0011" => str(ptr) := '3';
when "0100" => str(ptr) := '4';
when "0101" => str(ptr) := '5';
when "0110" => str(ptr) := '6';
when "0111" => str(ptr) := '7';
when "1000" => str(ptr) := '8';
when "1001" => str(ptr) := '9';
when "1010" => str(ptr) := 'a';
when "1011" => str(ptr) := 'b';
when "1100" => str(ptr) := 'c';
when "1101" => str(ptr) := 'd';
when "1110" => str(ptr) := 'e';
when "1111" => str(ptr) := 'f';
when "XXXX" => str(ptr) := 'x';
when "ZZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 3 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_hex_string;
function to_decimal_string(
val : integer;
pad : pad_type := pad_spaces) return string is
variable tmp : integer := val;
variable ptr : integer range 1 to 32 := 32;
variable str : string(1 to 32) := (others=>'0');
begin
if val=0 then
return do_pad("0", pad);
else
while tmp > 0 loop
case tmp rem 10 is
when 0 => str(ptr) := '0';
when 1 => str(ptr) := '1';
when 2 => str(ptr) := '2';
when 3 => str(ptr) := '3';
when 4 => str(ptr) := '4';
when 5 => str(ptr) := '5';
when 6 => str(ptr) := '6';
when 7 => str(ptr) := '7';
when 8 => str(ptr) := '8';
when 9 => str(ptr) := '9';
when others => null;
end case;
tmp := tmp / 10;
ptr := ptr - 1;
end loop;
return do_pad(str(ptr+1 to 32), pad);
end if;
end to_decimal_string;
function to_decimal_string(
val : std_logic_vector;
pad : pad_type := pad_spaces) return string is
variable all_x : boolean := true;
variable all_z : boolean := true;
variable some_x : boolean := false;
variable some_z : boolean := false;
variable fixed_str : string(1 to 1);
begin
for i in val'range loop
case to_x01z(val(i)) is
when 'X' => some_x := true; all_z := false;
when 'Z' => some_z := true; all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x) then
fixed_str(1) := 'x';
return fixed_str;
elsif (all_z) then
fixed_str(1) := 'z';
return fixed_str;
elsif (some_x) then
fixed_str(1) := 'X';
return fixed_str;
elsif (some_z) then
fixed_str(1) := 'Z';
return fixed_str;
else
return to_decimal_string(conv_integer(val), pad);
end if;
end to_decimal_string;
function to_octal_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,3);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/3)+1 := 1;
variable str : string(1 to ext_len/3) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 3 /= 1;
case slv3(to_x01z(val_ext(i to i+2))) is
when "000" => str(ptr) := '0';
when "001" => str(ptr) := '1';
when "010" => str(ptr) := '2';
when "011" => str(ptr) := '3';
when "100" => str(ptr) := '4';
when "101" => str(ptr) := '5';
when "110" => str(ptr) := '6';
when "111" => str(ptr) := '7';
when "XXX" => str(ptr) := 'x';
when "ZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 2 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_octal_string;
function to_hex_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_hex_string;
function to_decimal_string(
val : std_logic;
pad : pad_type := pad_spaces) return string is
begin
return to_binary_string(val, pad);
end to_decimal_string;
function to_octal_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_octal_string;
function to_binary_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to 1);
begin
case to_x01z(val) is
when '0' => str(1) := '0';
when '1' => str(1) := '1';
when 'X' => str(1) := 'x';
when 'Z' => str(1) := 'z';
when others => str(1) := 'x';
end case;
return do_pad(str, pad);
end to_binary_string;
function to_binary_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to val'length) := (others=>'0');
variable ptr : integer := str'left;
begin
for i in val'range loop
str(ptr to ptr) := to_binary_string(val(i));
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_binary_string;
end altera_europa_support_lib;
Common/sim/altera/libsrc/altera/altera_internal_syn.vhd
-40
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@@ -1,40 +0,0 @@
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 2003 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Declares utility package for internal Altera synthesis --
-- support. --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
PACKAGE altera_internal_syn is
-- Specfies a built-in pragma function that should replace a user-defined
-- subprogram during synthesis.
ATTRIBUTE synthesis_return : STRING;
-- If a subprogram specifies a synthesis_return attribute, it may also
-- use these additional attributes to fine-tune the behavior of a built-in
-- function.
-- Specifies the method for calculating the size of a unary or binary
-- built-in pragma function's result. The following values are supported:
--
-- LEFT: Use the size of the left operand
-- RIGHT: Use the size of the right operand
-- MAX_LEFT_RIGHT: Use the maximum of the left and right operands
ATTRIBUTE synthesis_result_size : STRING;
-- Flag that indicates if a type or an argument/result of a built-in pragma
-- function is signed (TRUE) or unsigned (FALSE).
ATTRIBUTE is_signed : BOOLEAN;
-- Flag that indicates if truncation should preserve the sign bit
attribute signed_truncation : BOOLEAN;
END altera_internal_syn;
Common/sim/altera/libsrc/altera/altera_primitives.vhd
-1785
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Common/sim/altera/libsrc/altera/altera_primitives_components.vhd
-435
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@@ -1,435 +0,0 @@
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
dont_touch : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
Common/sim/altera/libsrc/altera/altera_standard_functions.vhd
-45
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@@ -1,45 +0,0 @@
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
library std;
use std.standard.all;
package altera_standard_functions is
function maximum (L, R: integer) return integer;
function minimum (L, R: integer) return integer;
end altera_standard_functions;
package body altera_standard_functions is
function maximum (L, R: integer) return integer is
begin
if L > R then
return L;
else
return R;
end if;
end maximum;
function minimum (L, R: integer) return integer is
begin
if L > R then
return R;
else
return L;
end if;
end minimum;
end altera_standard_functions;
Common/sim/altera/libsrc/altera/altera_syn_attributes.vhd
-94
View File
@@ -1,94 +0,0 @@
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 2006 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Package containing Attribute Declarations for all --
-- attributes that control Quartus II Integrated Synthesis. --
-- Please refer to the Quartus II Help for documentation --
-- on using these attributes. --
-- --
-- --
-----------------------------------------------------------------------------
library std;
use std.standard.all;
PACKAGE altera_syn_attributes is
-- Directs Quartus II to implement input, output, and output
-- enable registers in I/O cells that have fast, direct connections to
-- an I/O pin, when possible
ATTRIBUTE useioff : BOOLEAN;
-- Prevents Quartus II from minimizing or removing a register
ATTRIBUTE preserve : BOOLEAN;
-- Prevents Quartus II from removing a dangling register
ATTRIBUTE noprune : BOOLEAN;
-- Prevents Quartus II from merging a register with a duplicate
ATTRIBUTE dont_merge : BOOLEAN;
-- Prevents Quartus II from replicating a register to improve timing
ATTRIBUTE dont_replicate : BOOLEAN;
-- Prevents Quartus II from retiming a register
ATTRIBUTE dont_retime : BOOLEAN;
-- Identifies the critical clock enable signal for a register. The
-- Quartus II software will attempt to connect this signal to the
-- dedicated clock enable port.
ATTRIBUTE direct_enable : BOOLEAN;
-- Prevents Quartus II from minimizing or removing a particular
-- signal net during combinational logic optimization
ATTRIBUTE keep : BOOLEAN;
-- Sets a fan-out limit on a register or net.
ATTRIBUTE maxfan : NATURAL;
-- Controls the implementation of a multiplication (*) operations in VHDL
ATTRIBUTE multstyle : STRING;
-- Controls the implementation of inferred memories
ATTRIBUTE ramstyle : STRING;
-- Controls the implementation of inferred ROMs
ATTRIBUTE romstyle : STRING;
-- Specifies a Memory Initialization File (.mif) for an inferred RAM
ATTRIBUTE ram_init_file : STRING;
-- Assigns a logic encoding to an enumerated type. Prevents state
-- machine extraction for all objects with the enumerated type.
ATTRIBUTE enum_encoding : STRING;
-- Assigns a state encoding to an enumerated type that models the states
-- of an extracted state machine.
ATTRIBUTE syn_encoding : STRING;
-- Specifies device pin assignments for a VHDL entity port
ATTRIBUTE chip_pin : STRING;
-- Applies an arbitrary number of Quartus Settings File (QSF) assignments
-- to a signal, entity, architecture, instance, or inferred register
ATTRIBUTE altera_attribute : STRING;
END altera_syn_attributes;
Common/sim/altera/libsrc/altera/maxplus2.vhd
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Common/sim/altera/libsrc/altera/megacore.vhd
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-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1996 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Package file for Altera mega functions. --
-- --
-- --
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package megacore is
component a16450
port (
mr : IN std_logic;
clk : IN std_logic;
a : IN std_logic_vector(2 downto 0);
din : IN std_logic_vector(7 downto 0);
cs0 : IN std_logic;
cs1 : IN std_logic;
ncs2 : IN std_logic;
nads : IN std_logic;
rd : IN std_logic;
nrd : IN std_logic;
wr : IN std_logic;
nwr : IN std_logic;
sin : IN std_logic;
rclk : IN std_logic;
ncts : IN std_logic;
ndsr : IN std_logic;
ndcd : IN std_logic;
nri : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
ddis : OUT std_logic;
csout : OUT std_logic;
sout : OUT std_logic;
nbaudout : OUT std_logic;
nrts : OUT std_logic;
ndtr : OUT std_logic;
nout1 : OUT std_logic;
nout2 : OUT std_logic;
intr : OUT std_logic
);
end component;
component a6402
port (
cls1 : IN std_logic;
cls2 : IN std_logic;
crl : IN std_logic;
ndrr : IN std_logic;
epe : IN std_logic;
mr : IN std_logic;
pi : IN std_logic;
rrc : IN std_logic;
rri : IN std_logic;
sbs : IN std_logic;
tbr : IN std_logic_vector(7 downto 0);
ntbrl : IN std_logic;
trc : IN std_logic;
dr : OUT std_logic;
fe : OUT std_logic;
oe : OUT std_logic;
pe : OUT std_logic;
rbr : OUT std_logic_vector(7 downto 0);
tbre : OUT std_logic;
tro : OUT std_logic;
tre : OUT std_logic
);
end component;
component a6850
port (
nreset : IN std_logic;
di : IN std_logic_vector(7 downto 0);
e : IN std_logic;
rnw : IN std_logic;
cs : IN std_logic_vector(2 downto 0);
rs : IN std_logic;
txclk : IN std_logic;
rxclk : IN std_logic;
rxdata : IN std_logic;
ncts : IN std_logic;
ndcd : IN std_logic;
do : OUT std_logic_vector(7 downto 0);
nirq : OUT std_logic;
txdata : OUT std_logic;
nrts : OUT std_logic
);
end component;
component a8237
port (
reset : IN std_logic;
clk : IN std_logic;
ncs : IN std_logic;
niorin : IN std_logic;
niowin : IN std_logic;
ready : IN std_logic;
hlda : IN std_logic;
neopin : IN std_logic;
ain : IN std_logic_vector(3 downto 0);
dreq : IN std_logic_vector(3 downto 0);
dbin : IN std_logic_vector(7 downto 0);
dbout : OUT std_logic_vector(7 downto 0);
dben : OUT std_logic;
aout : OUT std_logic_vector(7 downto 0);
hrq : OUT std_logic;
dack : OUT std_logic_vector(3 downto 0);
aen : OUT std_logic;
adstb : OUT std_logic;
niorout : OUT std_logic;
niowout : OUT std_logic;
nmemr : OUT std_logic;
nmemw : OUT std_logic;
neopout : OUT std_logic;
dmaenable : OUT std_logic
);
end component;
component a8251
port (
clk : IN std_logic;
nreset : IN std_logic;
nwr : IN std_logic;
nrd : IN std_logic;
ncs : IN std_logic;
cnd : IN std_logic;
ndsr : IN std_logic;
ncts : IN std_logic;
extsyncd : IN std_logic;
ntxc : IN std_logic;
nrxc : IN std_logic;
rxd : IN std_logic;
din : IN std_logic_vector(7 downto 0);
txd : OUT std_logic;
txrdy : OUT std_logic;
txempty : OUT std_logic;
rxrdy : OUT std_logic;
ndtr : OUT std_logic;
nrts : OUT std_logic;
syn_brk : OUT std_logic;
nen : OUT std_logic;
dout : OUT std_logic_vector(7 downto 0)
);
end component;
component a8255
port (
reset : IN std_logic;
clk : IN std_logic;
ncs : IN std_logic;
nrd : IN std_logic;
nwr : IN std_logic;
a : IN std_logic_vector(1 downto 0);
din : IN std_logic_vector(7 downto 0);
pain : IN std_logic_vector(7 downto 0);
pbin : IN std_logic_vector(7 downto 0);
pcin : IN std_logic_vector(7 downto 0);
dout : OUT std_logic_vector(7 downto 0);
paout : OUT std_logic_vector(7 downto 0);
paen : OUT std_logic;
pbout : OUT std_logic_vector(7 downto 0);
pben : OUT std_logic;
pcout : OUT std_logic_vector(7 downto 0);
pcen : OUT std_logic_vector(7 downto 0)
);
end component;
component rgb2ycrcb
port (
R : IN std_logic_vector(7 downto 0);
G : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic := '0';
ACLR : IN std_logic := '0';
Y : OUT std_logic_vector(15 downto 0);
Cr: OUT std_logic_vector(14 downto 0);
Cb: OUT std_logic_vector(14 downto 0)
);
end component;
component ycrcb2rgb
port (
Y : IN std_logic_vector(7 downto 0);
CR : IN std_logic_vector(7 downto 0);
CB : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic := '0';
ACLR : IN std_logic := '0';
R : OUT std_logic_vector(16 downto 0);
G: OUT std_logic_vector(16 downto 0);
B: OUT std_logic_vector(16 downto 0)
);
end component;
component a8259
port (
nmrst, clk, ncs, nwr, nrd, a0, nsp, ninta : IN std_logic;
casin : IN std_logic_vector(2 downto 0);
din, ir : IN std_logic_vector(7 downto 0);
nen, cas_en, int : OUT std_logic;
dout : OUT std_logic_vector(7 downto 0);
casout : OUT std_logic_vector(7 downto 0)
);
end component;
component fft
generic (
WIDTH_DATA : POSITIVE;
WIDTH_TWIDDLE : POSITIVE;
PIPE_DATA : INTEGER;
PIPE_TWIDDLE : INTEGER;
WIDTH_EXPONENT : POSITIVE;
WIDTH_ADD : POSITIVE;
EXPONENT_INITIAL_VALUE : INTEGER
);
port (
clock : IN std_logic := '0';
start_fft : IN std_logic;
data_left_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_left_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_right_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_right_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
twiddle_re : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
twiddle_im : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
done : OUT std_logic;
data_direction : OUT std_logic;
we_left : OUT std_logic;
add_left : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
we_right : OUT std_logic;
add_right : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
add_twiddle : OUT std_logic_vector(WIDTH_ADD-2 downto 0);
data_out_re : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
data_out_im : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
exponent : OUT std_logic_vector(WIDTH_EXPONENT-1 downto 0)
);
end component;
end megacore;
Common/sim/altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
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Common/sim/altera/libsrc/altera_mf/altera_mf_components.vhd
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Common/sim/altera/libsrc/altera_mf/stratixgx_mf_components.vhd
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--
-- Copyright (C) 1988-2002 Altera Corporation
--
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
-- other associated documentation or information provided by Altera or a
-- partner under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, net list, support information,
-- device programming or simulation file, or any other related
-- documentation or information is prohibited for any other purpose,
-- including, but not limited to modification, reverse engineering, de-
-- compiling, or use with any other silicon devices, unless such use is
-- explicitly licensed under a separate agreement with Altera or a
-- megafunction partner. Title to the intellectual property, including
-- patents, copyrights, trademarks, trade secrets, or maskworks, embodied
-- in any such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information provided by Altera or a megafunction partner, remains with
-- Altera, the megafunction partner, or their respective licensors. No
-- other licenses, including any licenses needed under any third party's
-- intellectual property, are provided herein.
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- ALtera Stratix GX Megafunction Component Declaration File
--
library ieee;
use ieee.std_logic_1164.all;
package stratixgx_mf_components is
function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
channel_width : integer) return integer;
function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
dwidth_factor : integer) return integer;
component altgxb
generic (
operation_mode : string := "DUPLEX";
loopback_mode : string := "NONE";
reverse_loopback_mode : string := "NONE";
protocol : string := "CUSTOM";
number_of_channels: integer := 20;
number_of_quads : integer := 1;
channel_width : positive := 20;
pll_inclock_period : integer := 20000;
data_rate : integer := 0;
data_rate_remainder : integer := 0;
rx_data_rate : integer := 0;
rx_data_rate_remainder : integer := 0;
use_8b_10b_mode : string := "OFF";
use_double_data_mode : string := "OFF";
dwidth_factor : integer := 1;
-- RX Mode
disparity_mode : string := "OFF";
cru_inclock_period : integer := 0; -- Units in ps
run_length : integer := 128;
run_length_enable : string := "OFF";
use_channel_align : string := "OFF";
use_auto_bit_slip : string := "OFF";
use_rate_match_fifo : string := "OFF";
use_symbol_align : string := "OFF";
align_pattern : string := "X";
align_pattern_length : integer := 0;
infiniband_invalid_code : integer := 0;
clk_out_mode_reference : string := "ON";
-- TX Mode
use_fifo_mode : string := "ON";
intended_device_family : string := "STRATIXGX";
force_disparity_mode : string := "OFF";
lpm_type : string := "altgxb";
tx_termination : integer := 0;
-- Quartus 2.2 New Parameters
-- common
use_self_test_mode : string := "OFF";
self_test_mode : integer := 0;
-- Receiver
use_equalizer_ctrl_signal : string := "OFF";
equalizer_ctrl_setting : integer := 0;
signal_threshold_select : integer := 80;
rx_bandwidth_type : string := "NEW_MEDIUM";
rx_enable_dc_coupling : string := "OFF";
use_vod_ctrl_signal : string := "OFF";
vod_ctrl_setting : integer := 1000;
use_preemphasis_ctrl_signal : string := "OFF";
preemphasis_ctrl_setting : integer := 0;
use_phase_shift : string := "ON";
pll_bandwidth_type : string := "LOW";
pll_use_dc_coupling : string := "OFF";
rx_ppm_setting : integer := 1000;
use_generic_fifo : string := "OFF";
use_rx_cruclk : string := "OFF";
use_rx_clkout : string := "OFF";
use_rx_coreclk : string := "OFF";
use_tx_coreclk : string := "OFF";
instantiate_transmitter_pll : string := "OFF";
consider_instantiate_transmitter_pll_param : string := "OFF";
rx_force_signal_detect : string := "OFF";
flip_rx_out : string := "OFF";
flip_tx_in : string := "OFF";
add_generic_fifo_we_synch_register : string := "OFF";
consider_enable_tx_8b_10b_i1i2_generation : string := "OFF";
enable_tx_8b_10b_i1i2_generation : string := "OFF";
for_engineering_sample_device : string := "ON";
device_family : string := ""
);
port (
inclk : in std_logic_vector(number_of_quads-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
pll_areset : in std_logic_vector(number_of_quads-1 downto 0):= (others => '0');
rx_cruclk : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '0');
rx_in : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rx_bitslip : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_enacdet : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_we: in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_re: in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_slpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_a1a2size : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_equalizerctrl : in std_logic_vector(number_of_channels * 3 -1 downto 0) := (others => '0');
rx_locktorefclk : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
rx_locktodata : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
tx_in : in std_logic_vector(channel_width * number_of_channels-1 downto 0) := (others => '0');
tx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
tx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
tx_ctrlenable : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
tx_forcedisparity : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
tx_srlpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
tx_vodctrl : in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
tx_preemphasisctrl: in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
-- XGM Input ports, common for Both Rx and Tx Mode
txdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rxdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rxanalogreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
pllenable : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '1');
pll_locked : out std_logic_vector(number_of_quads-1 downto 0);
coreclk_out : out std_logic_vector(number_of_quads-1 downto 0);
rx_out : out std_logic_vector(get_rx_channel_width(use_generic_fifo,
clk_out_mode_reference, channel_width) * number_of_channels-1 downto 0);
rx_clkout : out std_logic_vector(number_of_channels-1 downto 0);
rx_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_freqlocked : out std_logic_vector(number_of_channels-1 downto 0);
rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
rx_syncstatus : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_patterndetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_ctrldetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_errdetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_disperr : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_signaldetect : out std_logic_vector(number_of_channels-1 downto 0);
rx_fifoalmostempty : out std_logic_vector(number_of_channels-1 downto 0);
rx_fifoalmostfull : out std_logic_vector(number_of_channels-1 downto 0);
rx_channelaligned : out std_logic_vector(number_of_quads-1 downto 0);
rx_bisterr : out std_logic_vector(number_of_channels-1 downto 0);
rx_bistdone : out std_logic_vector(number_of_channels-1 downto 0);
rx_a1a2sizeout : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
tx_out : out std_logic_vector(number_of_channels-1 downto 0)
);
end component;
end;
package body stratixgx_mf_components is
function get_rx_channel_width(use_generic_fifo, clk_out_mode_reference : string;
channel_width : integer) return integer is
variable rx_channel_width : integer;
begin
rx_channel_width := channel_width;
if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
if (channel_width = 16) or (channel_width = 20) then
rx_channel_width := channel_width/2;
end if;
end if;
return rx_channel_width;
end get_rx_channel_width;
function get_rx_dwidth_factor(use_generic_fifo, clk_out_mode_reference : string;
dwidth_factor : integer) return integer is
variable rx_dwidth_factor : integer;
begin
rx_dwidth_factor := dwidth_factor;
if ((use_generic_fifo = "ON") or (clk_out_mode_reference = "OFF")) then
if (dwidth_factor = 2) then
rx_dwidth_factor := dwidth_factor/2;
end if;
end if;
return rx_dwidth_factor;
end get_rx_dwidth_factor;
end;
Common/sim/altera/libsrc/cycloneive/cycloneive_atoms.vhd
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Common/sim/altera/libsrc/cycloneive/cycloneive_components.vhd
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-- Quartus II 15.0.0 Build 145 04/22/2015
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneive_atom_pack.all;
package cycloneive_components is
--
-- cycloneive_lcell_comb
--
COMPONENT cycloneive_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneive_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneive_routing_wire
--
COMPONENT cycloneive_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneive_pll
--
COMPONENT cycloneive_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneive_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cycloneive";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneive_ff
--
COMPONENT cycloneive_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneive_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneive_ram_block
--
COMPONENT cycloneive_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneive_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneive_mac_mult
--
COMPONENT cycloneive_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_mac_out
--
COMPONENT cycloneive_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_io_ibuf
--
COMPONENT cycloneive_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneive_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_io_obuf
--
COMPONENT cycloneive_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneive_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_ddio_oe
--
COMPONENT cycloneive_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneive_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_ddio_out
--
COMPONENT cycloneive_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneive_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_pseudo_diff_out
--
COMPONENT cycloneive_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneive_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_io_pad
--
COMPONENT cycloneive_io_pad
GENERIC (
lpm_type : string := "cycloneive_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneive_asmiblock
--
COMPONENT cycloneive_asmiblock
generic (
lpm_type : string := "cycloneive_asmiblock";
enable_sim : string := "false"
);
port (
dclkin : in std_logic;
scein : in std_logic;
oe : in std_logic;
sdoin : in std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- cycloneive_clkctrl
--
COMPONENT cycloneive_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneive_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneive_rublock
--
COMPONENT cycloneive_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneive_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneive_apfcontroller
--
COMPONENT cycloneive_apfcontroller
generic
(
lpm_type: string := "cycloneive_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneive_termination
--
COMPONENT cycloneive_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneive_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneive_jtag
--
COMPONENT cycloneive_jtag
generic (
lpm_type : string := "cycloneive_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneive_crcblock
--
COMPONENT cycloneive_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneive_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneive_oscillator
--
COMPONENT cycloneive_oscillator
generic
(
lpm_type: string := "cycloneive_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
end cycloneive_components;
Common/sim/altera/libsrc/cyclonev/cyclonev_atoms.vhd
-7686
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Common/sim/altera/libsrc/cyclonev/cyclonev_atoms_ncrypt.v
-92659
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Common/sim/altera/libsrc/cyclonev/cyclonev_components.vhd
-1599
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Common/sim/compile_altera.do
-34
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@@ -1,34 +0,0 @@
if {![file exists build]} {mkdir build}
cd build
if {![file exists altera]} {mkdir altera}
cd altera
if {[file exists altera]} {vdel -lib altera -all}
vlib altera
vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives_components.vhd
vcom -93 -work altera ../../altera/libsrc/altera/altera_primitives.vhd
vcom -93 -work altera ../../altera/libsrc/altera/altera_internal_syn.vhd
vcom -93 -work altera ../../altera/libsrc/altera/altera_europa_support_lib.vhd
vcom -93 -work altera ../../altera/libsrc/altera/altera_standard_functions.vhd
vcom -93 -work altera ../../altera/libsrc/altera/altera_syn_attributes.vhd
vlib altera_mf
vcom -93 -work altera_mf ../../altera/libsrc/altera_mf/altera_mf_components.vhd
vcom -93 -work altera_mf ../../altera/libsrc/altera_mf/altera_mf.vhd
vlib cycloneive
vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_atoms.vhd
vcom -93 -work cycloneive ../../altera/libsrc/cycloneive/cycloneive_components.vhd
vlib altera_lnsim
vcom -93 -work altera_lnsim ../../altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
vlib cyclonev
vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_atoms.vhd
vcom -93 -work cyclonev ../../altera/libsrc/cyclonev/cyclonev_components.vhd
cd ..
cd ..
Common/sim/compile_ieee_proposed.do
-22
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@@ -1,22 +0,0 @@
#
# Compile script for Modeltech
#
if {![file exists build]} {mkdir build}
cd build
if {![file exists modelsim]} {mkdir modelsim}
cd modelsim
if {[file exists modelsim]} {vdel -lib modelsim -all}
vlib ieee_proposed
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_additions_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_textio_additions_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/env_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/std_logic_1164_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_float_types_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_pkg_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/float_pkg_c.vhdl
Common/sim/compile_simprim.do
+2 -3
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@@ -1,7 +1,6 @@
vlib build
vlib build/xilinx
vlib simprim
vlib build/xilinx/simprim
set XILINX C:/Programme/Xilinx101/ISE
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
Common/sim/compile_unisim.do
+5 -12
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@@ -1,15 +1,8 @@
if {![file exists build]} {mkdir build}
cd build
if {![file exists xilinx]} {mkdir xilinx}
cd xilinx
if {[file exists unisim]} {vdel -lib unisim -all}
vlib unisim
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vpkg.vhd
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vcomp.vhd
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_smodel.vhd
vcom -93 -work unisim ../../xilinx/libsrc/unisims/unisim_vital.vhd
set XILINX C:/Programme/Xilinx101/ISE
cd ..
cd ..
vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd
Common/sim/ieee_proposed.make
-29
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@@ -1,29 +0,0 @@
# -------------------------------------------------
# Compile script for GHDL
# -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -------------------------------------------------
# Global options
# -------------------------------------------------
LANG_STD := 93c
IEEE_STD := standard
WORK_LIB := ieee_proposed
TARGET := ghdl
STD_LIB_PATH := ieee_proposed/modelsim
# -------------------------------------------------
# Target options
# -------------------------------------------------
SRCS := $(STD_LIB_PATH)/standard_additions_c.vhdl
SRCS += $(STD_LIB_PATH)/standard_textio_additions_c.vhdl
SRCS += $(STD_LIB_PATH)/env_c.vhdl
SRCS += $(STD_LIB_PATH)/std_logic_1164_additions.vhdl
SRCS += $(STD_LIB_PATH)/numeric_std_additions.vhdl
SRCS += $(STD_LIB_PATH)/numeric_std_unsigned_c.vhdl
SRCS += $(STD_LIB_PATH)/fixed_float_types_c.vhdl
SRCS += $(STD_LIB_PATH)/fixed_pkg_c.vhdl
SRCS += $(STD_LIB_PATH)/float_pkg_c.vhdl
include $(VHDL_HOME)/make/ghdl.mk
Common/sim/ieee_proposed/modelsim/README
-173
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@@ -1,173 +0,0 @@
This is the "ieee_proposed" library. This is a compatability library,
which is designed to provide all of the functionality of the VHDL-200X-FT
packages in VHDL-93. The "_c" after the package name is used to denote
that this is a 1993 compliant version of this package. Otherwise, the
name of the file and the name of the package are the same.
Please compile the following files into a library named "ieee_proposed":
standard_additions_c.vhdl
env_c.vhdl
standard_textio_additions_c.vhdl
std_logic_1164_additions.vhdl
numeric_std_additions.vhdl
numeric_std_unsigned_c.vhdl
fixed_pkg_c.vhdl
float_pkg_c.vhdl
New/Updated functions
A) standard_additions -- Additions to the package "std.standard"
Use model:
use ieee_proposed.standard_additions.all;
Dependancies: None.
Notes: The functions "rising_edge" and "falling_edge" are defined in
this package. If you use "numeric_bit" they are ALSO defined in that
package, causing a conflict. The VHDL-200X-FT version of numeric_bit
has these functions commented out, as well as the "sll", "srl", "ror"
and "rol" functions which are implicit.
New types defined in this package:
REAL_VECTOR
TIME_VECTOR
INTEGER_VECTOR
BOOLEAN_VECTOR
New constants defined in this package:
SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
1) "maximum" and "minimum" are defined for all default datatypes
2) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a bit_vector to a single bit. Example:
or_reduce ("0101") = '1'. In VHDL-2006 syntax these will be "or".
3) "vector" and "bit" operations are defined. These will perform a
boolean operation of a vector. Example:
"1" xor "1010" = "0101";
5) /??/ function is defined for "bit" ("??" operator is release)
if (/??/('1')) then -- will return a "true".
6) rising_edge and falling_edge functions are defined (see Notes).
7) to_string function - Converts any of the base types into a string.
Example:
assert (bv = "101") report "result was " & to_string(bv) severity note;
8) to_hstring and to_ostring function (bit_vector to hex or octal string)
B) standard_textio_additions - Additions to the package "std.textio"
Use model:
use ieee_proposed.standard_textio_additions.all;
Dependencies: std.textio, ieee_proposed.standard_additions
1) tee - Echos the string to BOTH the file and the screen
2) SREAD and SWRITE - String read and write routines (so you no longer
need to do write (L, string'("ABCEDFG"));
3) HREAD and HWRITE (Hex read and write) for bit_vector
4) OREAD and OWRITE (octal read and write) for bit_vector
5) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
bit_vector
6) justify - Justify a string left or right with a width. Example:
justify ("ABCD", left, 6); will result in "ABCD "
C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
Usage model:
use ieee.std_logic_1164.all;
-- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
use ieee_proposed.std_logic_1164_additions.all;
Dependencies: ieee.std_logic_1164
Note: The contents of the "std_logic_textio" package have now been
included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
package is provided in the new release.
1) Short had aliases:
a) to_bv - calls "to_BitVector"
b) to_slv - calls "to_StdLogicVector"
c) to_sulv - calls "to_stdULogicVector"
2) Long hand aliases:
a) to_bit_vector - calls "to_BitVector"
b) to_std_logic_vector - calls "to_StdLogicVector"
c) to_std_ulogic_vector - calls "to_StdULogicVector"
3) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a std_logic_vector (or ulogic) to a single bit.
In vhdl-2006 these will be unary "or", example "or "11011" = '1'"
4) "vector" and "std_ulogic" operations are defined. These will perform a
boolean operation of a vector. Example:
"1" xor "1010" = "0101";
5) "std_ulogic" and "boolean" operations are defined. Thus:
if '1' and true then -- returns a "true".
6) "\??\" function is defined for "std_ulogic" ("??" operator is release)
if (bool('1')) then -- will return a "true".
7) READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
and "std_ulogic" are defined.
8) HREAD and HWRITE (Hex read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
9) OREAD and OWRITE (octal read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
10) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
std_logic_vector and std_ulogic_vector.
11) to_string function - Converts a "std_ulogic", "std_logic_vector" or
"std_ulogic_vector" types into a string.
Example:
assert (slv = "101") report "result was " & to_string(slv) severity note;
12) to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
string)
D) numeric_std_additions - additions the the package "ieee.numeric_std"
Usage Model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.numeric_std_additions.all;
Dependencies: ieee.std_logic_1164, ieee.numeric_std
1) SIGNED or UNSIGNED + std_ulogic operators
2) SIGNED or UNSIGNED - std_ulogic operators
3) type UNRESOLVED_UNSIGNED (aliased to U_UNSIGNED) is an unresolved
verion of UNSIGNED. It is aliased to "UNSIGNED" for compatability.
4) type UNRESOLVED_SIGNED (aliased to U_SIGNED) is an unresolved
verion of SIGNED. It is aliased to "SIGNED" for compatability.
5) \?=\, \?/=\ - similar to "std_match", but return std_ulogic values.
\?<\, \?<=\, \?>\, \?>=\ - compare functions which retrun std_ulogic.
(these will be "?="... operators in the release)
7) To_X01, To_X01Z, To_U01X, Is_X - same as std_logic_1164 functions,
but overloaded for SIGNED and UNSIGNED.
8) "sla" and "sra" - Mathmetically correct versions of these functions.
9) minimum and maximum - smaller or larger of two SIGNED or UNSIGNED values.
10) find_rightmost and find_leftmost - finds the first bit in a string.
Example:
find_leftmost (c12, '1'); -- returns the Log2 of "c12".
returns -1 if not found.
11) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a SIGNED or an UNSIGNED to a single bit.
(will overload the "or" and "and", ... operators in the release)
12) SIGNED or UNSIGNED and "std_ulogic" operations are defined.
These will perform a boolean operation of a vector. Example:
"1" xor "1010" = "0101";
13) READ and WRITE procedures for "SIGNED", and "UNSIGNED" are defined.
14) HREAD and HWRITE (Hex read and write) for SIGNED and UNSIGNED.
These are more "forgiving" than the ones
originally from "std_logic_textio"
15) OREAD and OWRITE (octal read and write) for "SIGNED" and "UNSIGNED.
These are more "forgiving" than the ones
originally from "std_logic_textio"
16) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
SIGNED and UNSIGNED.
17) to_string function - Converts a "SIGNED" or "UNSIGNED" types into a
string. Example:
assert (UNS = "101") report "result was " & to_string(UNS) severity note;
18) to_hstring and to_ostring function (SIGNED or UNSIGNED to hex or octal
string)
E) numeric_std_unsigned - Simular to the "std_logic_unsigned" packages, but
with all of the functionality of the "numeric_std" package.
use model:
use ieee.std_logic_1164.all;
use ieee_proposed.numeric_std_unsigned.all;
dependencies: ieee.numeric_std, ieee_proposed.numeric_std_additions
F) For fixed point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
See fixed point package documentation
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
G) For floating point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
See floating point package documentation
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf
Common/sim/ieee_proposed/modelsim/compile.mti
-14
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@@ -1,14 +0,0 @@
#
# Compile script for Modeltech
#
vlib ieee_proposed.lib
vmap ieee_proposed ieee_proposed.lib
vcom -work ieee_proposed standard_additions_c.vhdl
vcom -work ieee_proposed standard_textio_additions_c.vhdl
vcom -work ieee_proposed env_c.vhdl
vcom -work ieee_proposed std_logic_1164_additions.vhdl
vcom -work ieee_proposed numeric_std_additions.vhdl
vcom -work ieee_proposed numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed fixed_float_types_c.vhdl
vcom -work ieee_proposed fixed_pkg_c.vhdl
vcom -work ieee_proposed float_pkg_c.vhdl
Common/sim/ieee_proposed/modelsim/env_c.vhdl
-48
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@@ -1,48 +0,0 @@
package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
report "Procedure STOP called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure STOP;
procedure FINISH (STATUS : INTEGER) is
begin
report "Procedure FINISH called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure FINISH;
constant BASE_TIME_ARRAY : time_vector :=
(
1 fs, 10 fs, 100 fs,
1 ps, 10 ps, 100 ps,
1 ns, 10 ns, 100 ns,
1 us, 10 us, 100 us,
1 ms, 10 ms, 100 ms,
1 sec, 10 sec, 100 sec,
1 min, 10 min, 100 min,
1 hr, 10 hr, 100 hr
) ;
function RESOLUTION_LIMIT return DELAY_LENGTH is
begin
for i in BASE_TIME_ARRAY'range loop
if BASE_TIME_ARRAY(i) > 0 hr then
return BASE_TIME_ARRAY(i);
end if;
end loop;
report "STANDATD.RESOLUTION_LIMIT: Simulator resolution not less than 100 hr"
severity failure;
return 1 ns;
end function RESOLUTION_LIMIT;
end package body ENV;
Common/sim/ieee_proposed/modelsim/fixed_float_types_c.vhdl
-34
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@@ -1,34 +0,0 @@
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.1 $
-- Date : $Date: 2010/09/22 18:44:20 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
Common/sim/ieee_proposed/modelsim/fixed_pkg_c.vhdl
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Common/sim/ieee_proposed/modelsim/fixed_synth.vhdl
-736
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@@ -1,736 +0,0 @@
-- Synthesis test for the fixed point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:49:35-04 $
-- Version $Id: fixed_synth.vhdl,v 1.1 2006-06-08 10:49:35-04 l435385 Exp $
-- --------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity fixed_synth is
port (
in1, in2 : in STD_LOGIC_VECTOR (15 downto 0); -- inputs
out1 : out STD_LOGIC_VECTOR (15 downto 0); -- output
cmd : in STD_LOGIC_VECTOR (3 downto 0);
clk, rst_n : in STD_ULOGIC); -- clk and reset
end entity fixed_synth;
architecture rtl of fixed_synth is
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
type cmd_type is array (1 to 15) of STD_ULOGIC_VECTOR (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 4) of sfixed16; -- arrays
signal outarray0, outarray1, outarray2, outarray3, outarray4,
outarray5, outarray6, outarray7, outarray8, outarray9, outarray10,
outarray11, outarray12, outarray13, outarray14, outarray15 : sfixed16;
signal in1reg3, in2reg3 : sfixed16; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg : process (clk, rst_n) is
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
SFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray0 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray0 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1pin2 := in1array(3) + in2array(3);
outarray(0) := resize (in1pin2, outarray(0));
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
variable in1min2 : sfixed (SFixed_high(in1array(0), '-', in2array(0)) downto
SFixed_low(in1array(0), '-', in2array(0)));
-- variable in1min2 : sfixed (SFixed_high(7, -8, '-', 7, -8) downto
-- SFixed_low(7, -8, '-', 7, -8));
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray1 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray1 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := in1array(3) - in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg : process (clk, rst_n) is
-- variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto
-- SFixed_low(in1reg3, '*', in2reg3));
variable in1min2 : sfixed (SFixed_high(7, -8, '*', 7, -8) downto
SFixed_low(7, -8, '*', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray2 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray2 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := in1array(3) * in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd2reg;
-- purpose: "0011" test the "/" operator
cmd3reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(in1reg3'high, in1reg3'low,
'/', in2reg3'high, in2reg3'low)
downto
SFixed_low(in1reg3'high, in1reg3'low,
'/', in2reg3'high, in2reg3'low));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd3reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray3 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray3 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) / in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd3reg;
-- purpose: "0100" test the "+" operator
cmd4reg : process (clk, rst_n) is
variable in1pin2 : ufixed (uFixed_high(7, -8, '+', 7, -8) downto
uFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray4 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray4 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1pin2 := ufixed(in1array(3)) + ufixed(in2array(3));
outarray(0) := sfixed (resize (in1pin2, outarray4'high, outarray4'low));
end if;
end process cmd4reg;
-- purpose: "0101" test the "-" operator
cmd5reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '-', 7, -8) downto
uFixed_low(7, -8, '-', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray5 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray5 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := ufixed(in1array(3)) - ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray5'high, outarray5'low));
end if;
end process cmd5reg;
-- purpose: "0110" test the "*" operator
cmd6reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '*', 7, -8) downto
uFixed_low(7, -8, '*', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray6 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray6 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := ufixed(in1array(3)) * ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray6'high, outarray6'low));
end if;
end process cmd6reg;
-- purpose: "0111" test the "/" operator
cmd7reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '/', 7, -8) downto
uFixed_low(7, -8, '/', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray7 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray7 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
else
in2array(0) := in2reg3;
end if;
in1min2 := ufixed(in1array(3)) / ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray7'high, outarray7'low));
end if;
end process cmd7reg;
-- purpose: "1000" test the resize test
cmd8reg : process (clk, rst_n) is
variable tmpfp71, tmpfp72 : sfixed7; -- 8 bit fp number
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray8 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray8 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
-- Resize test Convert inputs into two 8 bit numbers
tmpfp71 := resize (in1array(3), tmpfp71'high, tmpfp71'low,
fixed_wrap, fixed_truncate);
tmpfp72 := resize (in2array(3), tmpfp72'high, tmpfp72'low,
fixed_saturate, fixed_round);
outarray(0) := (others => '0');
fx1 : for i in tmpfp71'range loop
outarray(0)(i+4) := tmpfp71(i);
end loop fx1;
fx2 : for i in tmpfp72'range loop
outarray(0)(i-4) := tmpfp72(i);
end loop fx2;
end if;
end process cmd8reg;
-- purpose: "1001" test the to_signed/unsigned test
cmd9reg : process (clk, rst_n) is
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
variable tmpsig : SIGNED (7 downto 0); -- signed number
variable tmpuns : UNSIGNED (15 downto 0); -- unsigned number
variable tmpint : INTEGER;
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray9 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray9 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
if (tmp = "00") then
-- Signed to sfixed and back
tmpsig := to_signed (in1array(3), tmpsig'length);
outarray(0) := to_sfixed (tmpsig, outarray(0));
elsif (tmp = "01") then
-- unsigned to ufixed and back
tmpuns := to_unsigned (ufixed(in1array(3)), tmpuns'length);
outarray(0) := sfixed(to_ufixed (tmpuns, outarray(0)'high,
outarray(0)'low));
elsif (tmp = "10") then
tmpint := to_integer (in1array(3));
outarray(0) := to_sfixed (tmpint, outarray(0));
else
tmpint := to_integer (ufixed(in1array(3)));
outarray(0) := sfixed(to_ufixed (tmpint, outarray(0)'high,
outarray(0)'low));
end if;
end if;
end process cmd9reg;
-- purpose: "1010" test the reciprocal, abs, - test
cmd10reg : process (clk, rst_n) is
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
variable in1recip : sfixed (-in1reg3'low+1 downto -in1reg3'high);
variable uin1recip : ufixed (-in1reg3'low downto -in1reg3'high-1);
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
SFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray10 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := to_sfixed(1, in1reg3);
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray10 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
if (in1reg3 = 0) then
in1array(0) := to_sfixed(1, in1reg3);
else
in1array(0) := in1reg3;
end if;
in2array(0) := in2reg3;
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
if (tmp = "00") then
in1recip := reciprocal (in1array(3));
outarray(0) := resize (in1recip, outarray(0)'high,
outarray(0)'low);
elsif (tmp = "01") then
uin1recip := reciprocal (ufixed(in1array(3)));
outarray(0) := sfixed(resize (uin1recip, outarray(0)'high,
outarray(0)'low));
elsif (tmp = "10") then
-- abs
in1pin2 := abs(in1array(3));
outarray(0) := resize (in1pin2,
outarray(0)'high,
outarray(0)'low);
else
-- -
in1pin2 := - in1array(3);
outarray(0) := resize (in1pin2,
outarray(0)'high,
outarray(0)'low);
end if;
end if;
end process cmd10reg;
-- purpose: "1011" test the mod operator
cmd11reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(7, -8, 'M', 7, -8) downto
SFixed_low(7, -8, 'm', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray11 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray11 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) mod in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd11reg;
-- purpose: "1100" test the rem operator
cmd12reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(7, -8, 'R', 7, -8) downto
SFixed_low(7, -8, 'r', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray12 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray12 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) rem in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd12reg;
-- purpose: "1101" test the srl operator
cmd13reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray13 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray13 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
outarray(0) := in1array(3) srl to_integer(in2array(3));
end if;
end process cmd13reg;
-- purpose: "1110" test the sra operator
cmd14reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray14 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray14 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
outarray(0) := in1array(3) sra to_integer(in2array(3));
end if;
end process cmd14reg;
-- purpose: "1111" test the sra operator
cmd15reg : process (clk, rst_n) is
constant match_data : sfixed16 := "01HL----10HL----"; -- for ?= command
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray15 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray15 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
-- compare test
if (in1array(3) = in2array(3)) then
outarray(0)(-8) := '1';
else
outarray(0)(-8) := '0';
end if;
if (in1array(3) /= in2array(3)) then
outarray(0)(-7) := '1';
else
outarray(0)(-7) := '0';
end if;
if (in1array(3) < in2array(3)) then
outarray(0)(-6) := '1';
else
outarray(0)(-6) := '0';
end if;
if (in1array(3) > in2array(3)) then
outarray(0)(-5) := '1';
else
outarray(0)(-5) := '0';
end if;
if (in1array(3) <= in2array(3)) then
outarray(0)(-4) := '1';
else
outarray(0)(-4) := '0';
end if;
if (in1array(3) >= in2array(3)) then
outarray(0)(-3) := '1';
else
outarray(0)(-3) := '0';
end if;
if (in1array(3) = 45) then
outarray(0)(-2) := '1';
else
outarray(0)(-2) := '0';
end if;
if (in1array(3) = 3.125) then
outarray(0)(-1) := '1';
else
outarray(0)(-1) := '0';
end if;
-- add integer and real
outarray(0)(0) := \?=\ (in1array(3), in2array(3) + 45);
if (in1array(3) = in2array(3) + 3.125) then
outarray(0)(1) := '1';
else
outarray(0)(1) := '0';
end if;
if (std_match (in1array(3), match_data)) then
outarray(0)(2) := '1';
else
outarray(0)(2) := '0';
end if;
outarray(0)(3) := nor_reduce (in1array(3) or in2array(3));
outarray(0)(4) := xnor_reduce (in1array(3) xor in2array(3));
outarray(0)(5) := nand_reduce (not in1array(3));
outarray(0)(6) := or_reduce ('1' and ufixed(in1array(3)));
if find_leftmost(in1array(3), '1') = 3 then
outarray(0)(7) := '1';
else
outarray(0)(7) := '0';
end if;
end if;
end process cmd15reg;
-- purpose: register the inputs and the outputs
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg : process (clk, rst_n) is
variable outreg : sfixed16; -- register stages
variable in1reg, in2reg : sfixed16; -- register stages
variable in1reg2, in2reg2 : sfixed16; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := (others => '0');
in2reg := (others => '0');
in1reg2 := (others => '0');
in2reg2 := (others => '0');
in1reg3 <= (others => '0');
in2reg3 <= (others => '0');
out1 <= (others => '0');
outreg := (others => '0');
rcloop : for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc : case cmdarray (13) is
when "0000" => outreg := outarray0;
when "0001" => outreg := outarray1;
when "0010" => outreg := outarray2;
when "0011" => outreg := outarray3;
when "0100" => outreg := outarray4;
when "0101" => outreg := outarray5;
when "0110" => outreg := outarray6;
when "0111" => outreg := outarray7;
when "1000" => outreg := outarray8;
when "1001" => outreg := outarray9;
when "1010" => outreg := outarray10;
when "1011" => outreg := outarray11;
when "1100" => outreg := outarray12;
when "1101" => outreg := outarray13;
when "1110" => outreg := outarray14;
when "1111" => outreg := outarray15;
when others => null;
end case outregc;
cmdpipe : for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= STD_ULOGIC_VECTOR(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_sfixed (in1, in1reg);
in2reg := to_sfixed (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
Common/sim/ieee_proposed/modelsim/float_pkg_c.vhdl
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Common/sim/ieee_proposed/modelsim/float_synth.vhdl
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@@ -1,709 +0,0 @@
-------------------------------------------------------------------------------
-- Synthesis test for the floating point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $
-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $
-------------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
use ieee.math_real.all;
entity float_synth is
port (
in1, in2 : in std_logic_vector (31 downto 0); -- inputs
out1 : out std_logic_vector (31 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end entity float_synth;
architecture rtl of float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 15) of float32; -- arrays
signal outx : cry_type;
signal in1reg3, in2reg3 : float32; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(0) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(0) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 + in2reg3;
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(1) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(1) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 - in2reg3;
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(2) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(2) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 * in2reg3;
end if;
end process cmd2reg;
-- purpose: "0011" performs test the "/" operator
cmd3reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(3) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(3) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
if (cmdarray(4) = "0011") then
outarray(0) := in1reg3 / in2reg3;
else
outarray(0) := (others => '0');
end if;
end if;
end process cmd3reg;
-- purpose: "0100" test the "resize" function
cmd4reg: process (clk, rst_n) is
variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(4) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(4) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_zero);
when "001" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "010" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "011" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_inf);
when "100" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_neginf);
when "101" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
check_error => false,
round_style => round_zero);
when "110" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low);
when "111" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low
-- size_res => tmpfp161
);
when others => null;
end case;
outarray(0)(-8 downto -23) := tmpfp161;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(6 downto -7) := (others => '0');
end if;
end process cmd4reg;
-- purpose: "0101" Conversion function test
cmd5reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(5) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(5) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := to_unsigned (in1reg3, uns'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "001" =>
uns := to_unsigned (in1reg3, uns);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "010" =>
s := to_signed (in1reg3, s'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "011" =>
s := to_signed (in1reg3, s);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "100" =>
uf := to_ufixed (in1reg3, uf'high, uf'low);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "101" =>
uf := to_ufixed (in1reg3, uf);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "110" =>
sf := to_sfixed (in1reg3, sf'high, sf'low);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when "111" =>
sf := to_sfixed (in1reg3, sf);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when others => null;
end case;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(5 downto -7) := (others => '0');
end if;
end process cmd5reg;
-- purpose: "0110" to_float()
cmd6reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(6) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(6) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, 8, 23);
when "001" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, in1reg3);
when "010" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, 8, 23);
when "011" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, in1reg3);
when "100" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);
outarray(0) := to_float(uf, 8, 23);
when "101" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);
outarray(0) := to_float(uf, in1reg3);
when "110" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);
outarray(0) := to_float(sf, 8, 23);
when "111" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);
outarray(0) := to_float(sf, in1reg3);
when others => null;
end case;
end if;
end process cmd6reg;
-- purpose: "0111" mod function
cmd7reg: process (clk, rst_n) is
variable tmpuns : unsigned (31 downto 0); -- unsigned number
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(7) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(7) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 mod in2reg3;
end if;
end process cmd7reg;
-- purpose: "1000" rem function
cmd8reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(8) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(8) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 rem in2reg3;
end if;
end process cmd8reg;
-- purpose: "1001" to_float (constants) test
cmd9reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(9) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(9) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := to_float(0, 8, 23);
when "001" =>
outarray(0) := to_float(0.0, 8, 23);
when "010" =>
outarray(0) := to_float(8, in1reg3);
when "011" =>
outarray(0) := to_float(8.0, in1reg3);
when "100" =>
outarray(0) := to_float(-8, 8, 23);
when "101" =>
outarray(0) := to_float(-8.0, 8, 23);
when "110" =>
outarray(0) := to_float(27000, in2reg3);
when "111" =>
-- outarray(0) := "01000000010010010000111111011011";
outarray(0) := to_float(MATH_PI, in2reg3);
when others => null;
end case;
end if;
end process cmd9reg;
-- purpose: "1010" data manipulation (+, -, scalb, etc)
cmd10reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable s : SIGNED (7 downto 0); -- signed number
variable outarray : cry_type; -- array for output
constant posinf : float32 := "01111111100000000000000000000000"; -- +inf
constant neginf : float32 := "11111111100000000000000000000000"; -- +inf
constant onept5 : float32 := "00111111110000000000000000000000"; -- 1.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(10) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(10) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := - in1reg3;
when "001" =>
outarray(0) := abs( in1reg3);
when "010" =>
if (cmdarray(4) = "1010") then
s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);
outarray(0) := Scalb (in1reg3, s);
else
outarray(0) := (others => '0');
end if;
when "011" =>
if (cmdarray(4) = "1010") then
s := logb (in1reg3);
outarray(0) := (others => '0');
outarray(0)(-16 downto -23) := float(std_logic_vector(s));
else
outarray(0) := (others => '0');
end if;
when "100" =>
outarray(0) := Nextafter ( in1reg3, onept5);
when "101" =>
outarray(0) := Nextafter ( in1reg3, -onept5);
when "110" =>
outarray(0) := Nextafter ( x => in1reg3, y => posinf,
check_error => false,
denormalize => false);
when "111" =>
outarray(0) := Nextafter (x => in1reg3, y => neginf,
check_error => false,
denormalize => false);
when others => null;
end case;
end if;
end process cmd10reg;
-- purpose "1011" copysign
cmd11reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(11) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(11) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := Copysign (in1reg3, in2reg3);
end if;
end process cmd11reg;
-- purpose "1100" compare test
cmd12reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
constant fifteenpt5 : float32 := "01000001011110000000000000000000";-- 15.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(12) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(12) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := (others => '0');
if (in1reg3 = in2reg3) then
outarray(0)(outarray(0)'high) := '1';
else
outarray(0)(outarray(0)'high) := '0';
end if;
if (in1reg3 /= in2reg3) then
outarray(0)(outarray(0)'high-1) := '1';
else
outarray(0)(outarray(0)'high-1) := '0';
end if;
if (in1reg3 > in2reg3) then
outarray(0)(outarray(0)'high-2) := '1';
else
outarray(0)(outarray(0)'high-2) := '0';
end if;
if (in1reg3 < in2reg3) then
outarray(0)(outarray(0)'high-3) := '1';
else
outarray(0)(outarray(0)'high-3) := '0';
end if;
if (in1reg3 >= in2reg3) then
outarray(0)(outarray(0)'high-4) := '1';
else
outarray(0)(outarray(0)'high-4) := '0';
end if;
if (in1reg3 <= in2reg3) then
outarray(0)(outarray(0)'high-5) := '1';
else
outarray(0)(outarray(0)'high-5) := '0';
end if;
outarray(0)(outarray(0)'high-6) := \?=\ (in1reg3, 15);
outarray(0)(outarray(0)'high-7) := \?=\ (in1reg3, 15.5);
if (Unordered (in1reg3, in2reg3)) then
outarray(0)(outarray(0)'high-8) := '1';
else
outarray(0)(outarray(0)'high-8) := '0';
end if;
if (Finite (in1reg3)) then
outarray(0)(outarray(0)'high-9) := '1';
else
outarray(0)(outarray(0)'high-9) := '0';
end if;
if (Isnan (in1reg3)) then
outarray(0)(outarray(0)'high-10) := '1';
else
outarray(0)(outarray(0)'high-10) := '0';
end if;
end if;
end process cmd12reg;
-- purpose "1101" boolean test
cmd13reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(13) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(13) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := not (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3;
when "010" =>
outarray(0) := in1reg3 or in2reg3;
when "011" =>
outarray(0) := in1reg3 nand in2reg3;
when "100" =>
outarray(0) := in1reg3 nor in2reg3;
when "101" =>
outarray(0) := in1reg3 xor in2reg3;
when "110" =>
outarray(0) := in1reg3 xnor in2reg3;
when "111" =>
outarray(0) := in1reg3 xor '1';
when others => null;
end case;
end if;
end process cmd13reg;
-- purpose "1110" reduce and vector test
cmd14reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(14) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(14) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := (others => '0');
outarray(0)(outarray(0)'high) := and_reduce (in1reg3);
outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);
outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);
outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);
outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);
outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3(in2reg3'high);
when "010" =>
outarray(0) := in1reg3 or in2reg3(in2reg3'high);
when "011" =>
outarray(0) := in1reg3 nand in2reg3(in2reg3'high);
when "100" =>
outarray(0) := in1reg3 nor in2reg3(in2reg3'high);
when "101" =>
outarray(0) := in2reg3(in2reg3'high) xor in1reg3;
when "110" =>
outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;
when "111" =>
outarray(0) := in2reg3(in2reg3'high) and in1reg3;
when others => null;
end case;
end if;
end process cmd14reg;
-- purpose "1111" + constant
cmd15reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(15) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(15) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := in1reg3 + 1;
when "001" =>
outarray(0) := 1 + in1reg3;
when "010" =>
outarray(0) := in1reg3 + 1.0;
when "011" =>
outarray(0) := 1.0 + in1reg3;
when "100" =>
outarray(0) := in1reg3 * 1;
when "101" =>
outarray(0) := 1 * in1reg3;
when "110" =>
outarray(0) := in1reg3 * 1.0;
when "111" =>
outarray(0) := 1.0 * in1reg3;
when others => null;
end case;
end if;
end process cmd15reg;
-- purpose: multiply floating point
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg: process (clk, rst_n) is
variable outreg : float32; -- register stages
variable in1reg, in2reg : float32; -- register stages
variable in1reg2, in2reg2 : float32; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := ( others => '0');
in2reg := ( others => '0');
in1reg2 := ( others => '0');
in2reg2 := ( others => '0');
in1reg3 <= ( others => '0');
in2reg3 <= ( others => '0');
out1 <= ( others => '0');
outreg := (others => '0');
rcloop: for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc: case cmdarray (13) is
when "0000" => outreg := outx (0);
when "0001" => outreg := outx (1);
when "0010" => outreg := outx (2);
when "0011" => outreg := outx (3);
when "0100" => outreg := outx (4);
when "0101" => outreg := outx (5);
when "0110" => outreg := outx (6);
when "0111" => outreg := outx (7);
when "1000" => outreg := outx (8);
when "1001" => outreg := outx (9);
when "1010" => outreg := outx (10);
when "1011" => outreg := outx (11);
when "1100" => outreg := outx (12);
when "1101" => outreg := outx (13);
when "1110" => outreg := outx (14);
when "1111" => outreg := outx (15);
when others => null;
end case outregc;
cmdpipe: for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= std_ulogic_vector(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_float (in1, in1reg);
in2reg := to_float (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
Common/sim/ieee_proposed/modelsim/modeltech.html
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<pre>
Tested with Modeltech 6.5b
When you compile you will get a warning:
(vcom-1246) Range 0 downto 1 is null.
To suppress this warning compile with "-suppress 1236"
In the MTI install you will find a premapped library called
"floatfixlib". This contains an old version of "fixed_pkg" and "float_pkg".
The versions in this release are newer.
To compile: source the "compile.mti" script. This will create the
IEEE_PROPOSED VHDL library.
See the README for an explination of the new functions in these packages.
</pre>
Common/sim/ieee_proposed/modelsim/numeric_std_additions.vhdl
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Common/sim/ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
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Common/sim/ieee_proposed/modelsim/standard_additions_c.vhdl
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Common/sim/ieee_proposed/modelsim/standard_textio_additions_c.vhdl
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------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
procedure FLUSH (file F : TEXT);
function MINIMUM (L, R : SIDE) return SIDE;
function MAXIMUM (L, R : SIDE) return SIDE;
function TO_STRING (VALUE : SIDE) return STRING;
function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
procedure TEE (file F : TEXT; L : inout LINE);
procedure WRITE (L : inout LINE; VALUE : in REAL;
FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
-- pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
swrite ( L => L,
VALUE => to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
Common/sim/ieee_proposed/modelsim/std_logic_1164_additions.vhdl
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Common/sim/ieee_proposed/modelsim/test_fixed_synth.vhdl
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-- Test vectors for the synthesis test for the fixed point math package
-- This test is designed to test fixed_synth and exercise much of the entity.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
-- --------------------------------------------------------------------
entity test_fixed_synth is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity test_fixed_synth;
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_pkg.all;
architecture testbench of test_fixed_synth is
procedure report_error (
constant errmes : in string; -- error message
actual : in sfixed; -- data from algorithm
constant expected : in sfixed) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & CR
& "Actual: " & to_string(actual)
& " (" & real'image(to_real(actual)) & ")" & CR
& " /= " & to_string(expected)
& " (" & real'image(to_real(expected)) & ")"
severity error;
return;
end procedure report_error;
-- Device under test. Note that all inputs and outputs are std_logic_vector.
-- This entity can be use both pre and post synthesis.
component fixed_synth is
port (
in1, in2 : in std_logic_vector (15 downto 0); -- inputs
out1 : out std_logic_vector (15 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end component fixed_synth;
constant clock_period : time := 500 ns; -- clock period
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
signal stop_clock : boolean := false; -- stop the clock
signal clk, rst_n : std_ulogic; -- clk and reset
signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
signal in1, in2 : sfixed16; -- inputs
signal out1 : sfixed16; -- output
signal cmd : std_logic_vector (3 downto 0); -- command string
begin -- architecture testbench
-- From fixed point to Std_logic_vector
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
-- Std_logic_vector to fixed point.
out1 <= to_sfixed(out1slv, out1'high, out1'low);
DUT: fixed_synth
port map (
in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
cmd => cmd, -- [in std_logic_vector (2 downto 0)]
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- purpose: clock driver
clkprc: process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
reset_proc: process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
tester: process is
begin -- process tester
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0001"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0010"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0011"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
cmd <= "0100"; -- unsigned add
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0101"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0110"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0100"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0111"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
-- resize
cmd <= "1000";
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-5.25, in2);
wait for clock_period;
in1 <= to_sfixed (21.125, in1);
in2 <= to_sfixed (21.125, in2);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (3, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-5.5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010"; -- abs (mod)
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-42, in1);
wait for clock_period;
cmd <= "1011"; -- mod
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1100"; -- REM
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1101"; -- srl
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-1, in2);
wait for clock_period;
cmd <= "1110"; -- sra
in1 <= to_sfixed (-7.25, in1);
in2 <= to_sfixed (1, in2);
wait for clock_period;
cmd <= "1111"; -- compare
in1 <= to_sfixed (42, in1);
in2 <= to_sfixed (42, in1);
wait for clock_period;
in1 <= to_sfixed (45, in1);
in2 <= to_sfixed (90, in1);
wait for clock_period;
in1 <= to_sfixed (3.125, in1);
in2 <= (others => '0');
wait for clock_period;
in1 <= "0110111110101111";
in2 <= "1111111111111111";
wait for clock_period;
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
in1 <= "0000111000000000";
in2 <= "0000111000000000";
wait for clock_period;
in1 <= (others => '1');
in2 <= (others => '1');
wait for clock_period;
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest: process is
constant fxzero : sfixed16 := (others => '0'); -- zero
variable chks16 : sfixed16; -- variable
variable sm1, sm2 : sfixed7; -- small fixed point
begin -- process checktest
wait for clock_period/2.0;
wait for clock_period;
wait for clock_period;
waitloop: while (out1 = fxzero) loop
wait for clock_period;
end loop waitloop;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
report_error ( "-0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
report_error ( "6.5/0.5 error",
out1,
chks16);
wait for clock_period;
-- resize test
sm1 := out1 (7 downto 1);
sm2 := to_sfixed (5.25, sm2);
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := to_sfixed (-5.25, sm2);
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
sm1 := out1 (7 downto 1);
sm2 := "0101001"; -- wrapped
-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := "0111111"; -- saturate
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
-- to_signed and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_unsigned and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
-- to_integer and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_integer(ufixed) and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
wait for clock_period;
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
wait for clock_period;
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
wait for clock_period;
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
wait for clock_period;
report_error ("abs(-42)", out1, to_sfixed (42, out1));
wait for clock_period;
report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
chks16 := "0000101010000000";
report_error ("5.25 srl -1", out1, chks16);
wait for clock_period;
chks16 := "1111110001100000";
report_error ("-7.25 sra 1", out1, chks16);
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "42=42 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------0001010110";
assert (std_match (out1, chks16))
report "45=90 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------1010101010";
assert (std_match (out1, chks16))
report "3.125=0 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0--1010000101010";
assert (std_match (out1, chks16))
report "pattern1 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0001100000110001";
assert (std_match (out1, chks16))
report "zero = zero " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "1111000000110001";
assert (std_match (out1, chks16))
report "pattern2 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "-1 = -1 " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
Common/sim/ieee_proposed/modelsim/test_float_synth.vhdl
-892
View File
@@ -1,892 +0,0 @@
-------------------------------------------------------------------------------
-- test routine for the post synthesis 32 bit multiply
-------------------------------------------------------------------------------
entity test_float_synth is
generic (
quiet : BOOLEAN := false);
end entity test_float_synth;
use std.textio.all;
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
--library modelsim_lib;
--use modelsim_lib.util.all;
architecture testbench of test_float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
function reverse (
inpvec : STD_LOGIC_VECTOR (0 to 31))
return float32 is
variable result : float32;
begin
for i in 0 to 31 loop
result (i-23) := inpvec(i);
end loop; -- i
return result;
end function reverse;
-- purpose: converts an float32 into a std_logic_vector
-- function to_slv (
-- input : float32) -- float32 input
-- return std_logic_vector is
-- variable result : std_logic_vector (31 downto 0); -- result
-- begin -- function to_slv
-- floop: for i in float32'range loop
-- result (i + fp_fraction_width) := input (i);
-- end loop floop;
-- return result;
-- end function to_slv;
-- purpose: converts a std_logic_vector to an float32
function to_float32x (
signal input : STD_LOGIC_VECTOR (31 downto 0))
return float32 is
variable result : float32;
begin -- function to_float32x
return to_float (input, float32'high, -float32'low);
end function to_float32x;
procedure report_error (
constant errmes : STRING; -- error message
actual : in float32; -- data from algorithm
constant expected : float32) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error;
procedure report_error16 (
constant errmes : STRING; -- error message
actual : in fp16; -- data from algorithm
constant expected : fp16) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & " miscompare" & CR &
"Actual " & to_string (actual) & " ("
& REAL'image(to_real(actual))& ") /= " & CR &
"Expected " & to_string (expected) & " ("
& REAL'image(to_real(expected))& ")"
severity error;
return;
end procedure report_error16;
component float_synth is
port (
in1, in2 : in STD_LOGIC_VECTOR(31 downto 0); -- inputs
out1 : out STD_LOGIC_VECTOR(31 downto 0); -- output
cmd : in STD_LOGIC_VECTOR (3 downto 0);
clk, rst_n : in STD_ULOGIC); -- clk and reset
end component float_synth;
for all : float_synth
use entity work.float_synth(rtl);
constant clock_period : TIME := 500 ns; -- clock period
signal stop_clock : BOOLEAN := false; -- stop the clock
signal out1real : REAL; -- real version
signal in1, in2 : float32; -- inputs
signal out1 : float32; -- output
constant zero0 : float32 := (others => '0'); -- zero
signal cmd : STD_LOGIC_VECTOR (3 downto 0); -- command
signal clk, rst_n : STD_ULOGIC; -- clk and reset
signal in1slv, in2slv, out1slv : STD_LOGIC_VECTOR(31 downto 0);
signal indelay : float32; -- spied signal
begin -- architecture testbench
out1real <= to_real (out1);
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
out1 <= to_float32x(out1slv);
DUT : float_synth
port map (
in1 => in1slv, -- [in float32] inputs
in2 => in2slv, -- [in float32] inputs
out1 => out1slv, -- [out float32] output
cmd => cmd,
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- spy_process : process
-- begin
-- signal_force ("/DUT/in2reg3", "00000000000000000000000000000000",
-- 500 ns, freeze, 5000 ns, 1);
-- wait;
-- end process spy_process;
-- purpose: clock driver
-- type : combinational
-- inputs :
-- outputs:
clkprc : process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
-- type : combinational
-- inputs :
-- outputs:
reset_proc : process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
-- type : combinational
-- inputs :
-- outputs:
tester : process is
begin -- process tester
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101111"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop1: for i in 1 to 100 loop
wait for clock_period;
end loop floop1;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
floop2: for i in 1 to 100 loop
wait for clock_period;
end loop floop2;
cmd <= "0010";
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000001010001000010"); -- 42
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000011"); -- -6.5
wait for clock_period;
in1 <= reverse("10000000000000000000000000000000"); -- 2**-149
in2 <= "11000000000000000000000000000000"; -- -2.0
wait for clock_period;
in1 <= reverse("00000000000000000000001000000000"); -- 2**-127
in2 <= "00111110100000000000000000000000"; -- 0.25
wait for clock_period;
in1 <= reverse("00000000000000000001010001000010"); -- 42
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
wait for clock_period;
cmd <= "0001"; -- subtract mode
in2 <= "01001011111001110011000110011011"; -- 30303030
in1 <= "01001011111001110011000110011100"; -- 30303033
wait for clock_period;
in1 <= reverse("00000000000000000000101100000010"); -- 6.5
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in2 <= reverse("00000000000000000000101100000010"); -- 6.5
in1 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00111110101010101010101010101011"; -- 1/3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "00111110101010101010101010101011"; -- 1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in2 <= "00111110101010101010101010101011"; -- 1/3
in1 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
in1 <= "00000000100000000000000000000001"; -- 2**-126
in2 <= "01000000100000000000000000000001"; -- 4+
wait for clock_period;
cmd <= "0011"; -- divide mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000010000000000000000000000"; -- 3.0
wait for clock_period;
in1 <= "01001100000011001011110001001111"; -- 36892987
in2 <= "00000000010000000000000000000000"; -- 2**-127
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "01000000000000000000000000000000"; -- 2
wait for clock_period;
cmd <= "0100"; -- 32 to 16 conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= (others => '0');
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3, no round
wait for clock_period;
in1 <= "10111110101010101010101010101011"; -- -1/3
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
cmd <= "0101"; -- conversion mode
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "01000000000000000000000000000000"; -- opcode zero
wait for clock_period;
in1 <= "01000010001010000000000000000000"; -- 42.0
in2 <= "00000000000000000000000000000001"; -- opcode 1
wait for clock_period;
in1 <= "10111111100000000000000000000000"; -- -1.0
in2 <= "00000000000000000000000000000010"; -- 2
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000011"; -- 3
wait for clock_period;
in1 <= "01000000100010101010101010101011"; -- 4.333333
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "00000000000000000000000000000110"; -- 6 to_sfixed
wait for clock_period;
in1 <= "00111111100000000000000000000000"; -- 1.0
in2 <= "00000000000000000000000000000111"; -- 7 to_sfixed
wait for clock_period;
cmd <= "0110"; -- 16 bit to float32 mode
in1 <= "00000000000000000000000000000011"; -- 3
in2 <= "01000000000000000000000000000000"; -- mode 0
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000001"; -- 1
wait for clock_period;
in1 <= "00000000000000001111111111111110"; -- -2
in2 <= "01000000000000000000000000000010"; -- 2 to_float(signed)
wait for clock_period;
in1 <= "00000000000000000000000000000100"; -- 4
in2 <= "01000000000000000000000000000011"; -- mode 3
wait for clock_period;
in1 <= "10000000000000000000001000101011"; -- 4.33 ufixed
in2 <= "00000000000000000000000000000100"; -- 4
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 ufixed
in2 <= "00000000000000000000000000000101"; -- 5
wait for clock_period;
in1 <= "11000000000000001111110111010101"; -- -4.333 sfixed
in2 <= "00000000000000000000000000000110"; -- 6
wait for clock_period;
in1 <= "10100000000000000000000010000000"; -- 1.0 sfixed
in2 <= "00000000000000000000000000000111"; -- 7
wait for clock_period;
cmd <= "0111"; -- Mod
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1000"; -- rem
in1 <= "00000000000000000000000000000011"; --
in2 <= "00000000000000000000000000000011"; --
wait for clock_period;
in1 <= "00000010001100101111000100111011"; -- 36892987
in2 <= "00000010001100101111000100111011"; -- 36892987
wait for clock_period;
in1 <= "11000000100010101010101010101011"; -- -4.333333
in2 <= "01000000100000000000000000000000"; -- 4
wait for clock_period;
cmd <= "1001"; -- constants conversion
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in2 <= "11000000000000000000000000000010"; -- command 2
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- command 4
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- command 5
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- command 6
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- command 7
wait for clock_period;
cmd <= "1010"; -- conversions
in1 <= to_float (1, in1);
in2 <= "11000000000000000000000000000000"; -- command 0
wait for clock_period;
in1 <= to_float (-2, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000001"; -- command 1
wait for clock_period;
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "00010000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11110000000000000000000000000010"; -- command 2 scalb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (1, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000011"; -- command 3 logb
in1 <= to_float (0.25, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000100"; -- 4 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000101"; -- 5 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000110"; -- 6 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (4, in1);
wait for clock_period;
in2 <= "11000000000000000000000000000111"; -- 7 nextafter
in1 <= to_float (1, in1);
wait for clock_period;
in1 <= to_float (-4, in1);
wait for clock_period;
cmd <= "1011"; -- copy sign
in1 <= to_float (2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= to_float (-3, in1);
in2 <= to_float (3, in1);
wait for clock_period;
in1 <= to_float (4, in1);
in2 <= to_float (-4, in1);
wait for clock_period;
in1 <= to_float (-5, in1);
in2 <= to_float (-5, in1);
wait for clock_period;
cmd <= "1100"; -- compare test
in1 <= to_float (15, in1);
in2 <= to_float (15, in1);
wait for clock_period;
in1 <= to_float (15.5, in1);
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= to_float (-2, in1);
in2 <= to_float (2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= to_float (-2, in1);
wait for clock_period;
in1 <= "01111111100000000000000000000001"; -- NAN
in2 <= to_float (-2, in1);
wait for clock_period;
cmd <= "1101"; -- boolean test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0 , not
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and
wait for clock_period;
in1 <= "01111111000000000000000000000000"; -- + inf
in2 <= "00111111000000000000000000000010"; -- command 2, or
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000011"; -- command 3, nand
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000100"; -- command 4, nor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000101"; -- command 5, xor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000110"; -- command 6, xnor
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000111"; -- command 7, xor '1'
wait for clock_period;
cmd <= "1110"; -- reduce and vector test test
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000000"; -- command 0,
wait for clock_period;
in1 <= "11111111111111111111111111111111"; -- all 1
wait for clock_period;
in1 <= "10000000000000000000000000000000"; -- -0
wait for clock_period;
in1 <= "00000000000000000000000000000000"; -- 0
wait for clock_period;
in1 <= "01111111100000000000000000000000"; -- + inf
in2 <= "00111111100000000000000000000001"; -- command 1, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, and '1'
wait for clock_period;
in2 <= "00111111100000000000000000000010"; -- command 2, or '0'
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, or '1'
wait for clock_period;
in2 <= "00111111100000000000000000000011"; -- command 3, nand '0'
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, nand '1'
wait for clock_period;
in2 <= "00111111100000000000000000000100"; -- command 4, nor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, nor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000101"; -- command 5, xor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, xor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000110"; -- command 6, xnor '0'
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, xnor '1'
wait for clock_period;
in2 <= "00111111100000000000000000000111"; -- command 7, and '0'
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, and '1'
wait for clock_period;
cmd <= "1111"; -- add and mult by constant
in2 <= "10111111100000000000000000000000"; -- command 0, + 1
in1 <= to_float (2, in1);
wait for clock_period;
in2 <= "10111111100000000000000000000001"; -- command 1, 1 +
wait for clock_period;
in2 <= "10111111100000000000000000000010"; -- command 2, + 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000011"; -- command 3, 1.0 +
wait for clock_period;
in2 <= "10111111100000000000000000000100"; -- command 4, * 1
wait for clock_period;
in2 <= "10111111100000000000000000000101"; -- command 5, 1 *
wait for clock_period;
in2 <= "10111111100000000000000000000110"; -- command 6, * 1.0
wait for clock_period;
in2 <= "10111111100000000000000000000111"; -- command 7, 1.0 *
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest : process is
variable out16, out16t : fp16; -- 16 bit fp variables
variable out1t, out2t : float32; -- 32 bit float
variable s16, s16t : SIGNED(7 downto 0); -- 7 bit SIGNED
variable latency : INTEGER := 0;
begin -- process checktest
wait for clock_period/2.0;
floop3: for i in 1 to 100 loop
wait for clock_period;
end loop floop3;
latency := 0;
out2t := "01000000100010101100000000000000";
wl1: while out1 /= out2t loop
wait for clock_period;
latency := latency + 1;
assert latency /= 100 report "After 100 loops, pattern never found"
severity failure;
end loop wl1;
report "Latency was " & INTEGER'image(latency) severity note;
floop4: for i in 1 to 100 loop
wait for clock_period;
end loop floop4;
report_error ("42 * 6.5 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1'high, -out1'low));
wait for clock_period;
report_error ("Multiply 42.25 miscompare",
out1,
"01000010001010010000000000000000"); -- 42.25
wait for clock_period;
report_error ("Multiply 84 miscompare",
out1,
"01000010101010000000000000000000"); -- 84
wait for clock_period;
report_error ("Multiply 2/3 miscompare",
out1,
"00111111001010101010101010101011"); -- 2/3
wait for clock_period;
report_error ("Multiply -273 miscompare",
out1,
"11000011100010001000000000000000"); -- -273
wait for clock_period;
report_error ("mult 2**-148 test miscompare",
out1,
reverse("01000000000000000000000000000001")); -- -2*-148
wait for clock_period;
report_error ("Multiply 2**-129 miscompare",
out1,
reverse("00000000000000000000100000000000")); -- 2**-129
wait for clock_period;
report_error ("6.5 * 42 error",
out1,
to_float (273, out1));
wait for clock_period;
report_error ("Subtract 30303033 - 30303030 miscompare",
out1,
"01000000000000000000000000000000"); -- 2 (not 3, rounding)
wait for clock_period;
report_error ("Subtract 6.5 - 4 miscompare",
out1,
"01000000001000000000000000000000"); -- 2.5
wait for clock_period;
report_error ("Subtract 4 - 6.5 miscompare",
out1,
"11000000001000000000000000000000"); -- -2.5
wait for clock_period;
report_error ("Subtract 4.333 - 1/3 miscompare",
out1,
"01000000100000000000000000000000"); -- 4
wait for clock_period;
report_error ("Add 2.333 miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 2.333 rev miscompare",
out1,
"01000000000101010101010101010101"); -- 2.333333
wait for clock_period;
report_error ("Add 4 + miscompare",
out1,
"01000000100000000000000000000001"); -- 4
wait for clock_period;
report_error ("div 1/3 test miscompare",
out1,
"00111110101010101010101010101011"); -- 1/3
wait for clock_period;
report_error ("div 369297/2**-126 test miscompare",
out1,
"01111111100000000000000000000000");
wait for clock_period;
report_error ("-1/6 test miscompare",
out1, "10111110001010101010101010101011"); -- -1/6
wait for clock_period;
-- resize function
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (1, out16t);
report_error16 ("1.0 fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (arg => -1.0/3.0, size_res => out16t,
round_style => round_zero);
report_error16 ("-1/3 not rounded fp16 converserion",
out16, out16t);
wait for clock_period;
out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);
out16t := to_float (-1.0/3.0, out16t);
report_error16 ("-1/3 fp16 converserion",
out16, out16t);
-- conversion test
wait for clock_period;
report_error ("1.0 to unsigned miscompare",
out1, "00000000000000000000000000000001");
wait for clock_period;
report_error ("42 to unsigned miscompare",
out1, "00100000000000000000000000101010");
wait for clock_period;
report_error ("-1.0 to signed miscompare",
out1, "01000000000000001111111111111111");
wait for clock_period;
report_error ("1.0 to signed miscompare",
out1, "01100000000000000000000000000001");
wait for clock_period;
report_error ("4.33 to ufixed miscompare",
out1, "10000000000000000000001000101011");
wait for clock_period;
report_error ("1.0 to ufixed miscompare",
out1, "10100000000000000000000010000000");
wait for clock_period;
report_error ("4.333 to sfixed miscompare",
out1, "11000000000000001111110111010101");
wait for clock_period;
report_error ("1.0 to sfixed miscompare",
out1, "11100000000000000000000010000000");
wait for clock_period;
report_error ("unsigned 3 to float miscompare",
out1, to_float(3, out1));
wait for clock_period;
report_error ("unsigned 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("signed -2 to float miscompare",
out1, to_float(-2, out1));
wait for clock_period;
report_error ("signed 4 to float miscompare",
out1, to_float(4, out1));
wait for clock_period;
report_error ("ufixed 4.333 to float miscompare",
out1, "01000000100010101100000000000000"); -- 4.333333
wait for clock_period;
report_error ("ufixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("sfixed -4.333 to float miscompare",
out1, "11000000100010101100000000000000"); -- -4.333333
wait for clock_period;
report_error ("sfixed 1.0 to float miscompare",
out1, "00111111100000000000000000000000"); -- 1.0
wait for clock_period;
report_error ("denormal mod denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large mod large miscompare",
out1, zero0);
wait for clock_period;
report_error ("-4.333 mod 4 miscompare",
out1,
from_string ("01000000011010101010101010101010", out1));
wait for clock_period;
report_error ("denormal rem denormal miscompare",
out1, zero0);
wait for clock_period;
report_error ("large rem large miscompare",
out1, zero0);
wait for clock_period;
out1t := "10111110101010101010101010110000";
report_error ("-4.333 rem 4 miscompare",
out1, out1t);
wait for clock_period;
report_error ("to_float(0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(0.0) miscompare",
out1, zero0);
wait for clock_period;
report_error ("to_float(8) miscompare",
out1, to_float(8.0, out1));
wait for clock_period;
report_error ("to_float(8.0) miscompare",
out1, to_float(8, out1));
wait for clock_period;
report_error ("to_float(-8) miscompare",
out1, to_float(-8.0, out1));
wait for clock_period;
report_error ("to_float(-8.0) miscompare",
out1, to_float(-8, out1));
wait for clock_period;
report_error ("to_float(27000) miscompare",
out1, to_float(27000.0, out1));
wait for clock_period;
report_error ("to_float(PI) miscompare",
out1, to_float(3.141592653589, out1));
-- Conversion test
wait for clock_period;
report_error ("-1 miscompare",
out1, to_float(-1, out1));
wait for clock_period;
report_error ("-(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(-2) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("abs(1) miscompare",
out1, to_float(1, out1));
wait for clock_period;
report_error ("scalb (1, 1) miscompare",
out1, to_float(2, out1));
wait for clock_period;
report_error ("scalb (1, -1) miscompare",
out1, to_float(0.5, out1));
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = 0) report "logb (1) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
s16 := SIGNED (to_slv (out1(-16 downto -23)));
assert (s16 = -2) report "logb (0.25) returned "
& to_string(to_sfixed(s16)) severity error;
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, 1.5)", out1, out1t);
wait for clock_period;
out1t := "01000000011111111111111111111111";
report_error ("nextafter (4, 1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, -1.5)", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111";
report_error ("nextafter (-4, -1.5)", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000001";
report_error ("nextafter (1, inf)", out1, out1t);
wait for clock_period;
out1t := "01000000100000000000000000000001";
report_error ("nextafter (4, inf)", out1, out1t);
wait for clock_period;
out1t := "00111111011111111111111111111111";
report_error ("nextafter (1, neginf)", out1, out1t);
wait for clock_period;
out1t := "11000000100000000000000000000001";
report_error ("nextafter (-4, neginf)", out1, out1t);
wait for clock_period;
report_error ("Copysign (2,2)", out1, to_float(2, out1));
wait for clock_period;
report_error ("Copysign (-3,3)", out1, to_float(3, out1));
wait for clock_period;
report_error ("Copysign (4,-4)", out1, to_float(-4, out1));
wait for clock_period;
report_error ("Copysign (-5,-5)", out1, to_float(-5, out1));
wait for clock_period;
out1t := "10001110000000000000000000000000";
report_error ("compare test 15, 15", out1, out1t);
wait for clock_period;
out1t := "01101001000000000000000000000000";
report_error ("compare test 15.5, -2", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000";
report_error ("compare test -2, 2", out1, out1t);
wait for clock_period;
out1t := "01101000010000000000000000000000";
report_error ("compare test inf, -2", out1, out1t);
wait for clock_period;
out1t := "01000000101000000000000000000000";
report_error ("compare test NAN, -2", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- not + inf
report_error ("not +inf", out1, out1t);
wait for clock_period;
out1t := "00111111100000000000000000000000"; -- and
report_error ("and +inf", out1, out1t);
wait for clock_period;
out1t := "01111111000000000000000000000010"; -- or
report_error ("or +inf", out1, out1t);
wait for clock_period;
out1t := "11000000011111111111111111111111"; -- nand
report_error ("nand +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111011"; -- nor
report_error ("nor +inf", out1, out1t);
wait for clock_period;
out1t := "01000000000000000000000000000101"; -- xor
report_error ("xor +inf", out1, out1t);
wait for clock_period;
out1t := "10111111111111111111111111111001"; -- xnor
report_error ("xnor +inf", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- xnor '1'
report_error ("+inf xor '1'", out1, out1t);
wait for clock_period;
out1t := "01100100000000000000000000000000"; -- reduce test
report_error ("_reduce test", out1, out1t);
wait for clock_period;
out1t := "10100100000000000000000000000000"; -- reduce test
report_error ("_reduce all 1 test", out1, out1t);
wait for clock_period;
out1t := "01101000000000000000000000000000"; -- reduce test
report_error ("_reduce -0 test", out1, out1t);
wait for clock_period;
out1t := "01010100000000000000000000000000"; -- reduce test
report_error ("_reduce 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("or 0 test", out1, out1t);
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "or 1 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "11111111111111111111111111111111"; -- all 1
assert (to_slv (out1) = to_slv (out1t))
report "nand 0 test error " & to_string (out1) & " /= "
& to_string (out1t) severity error;
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nand 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("nor 0 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("nor 1 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xor 0 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xor 1 test", out1, out1t);
wait for clock_period;
out1t := "10000000011111111111111111111111"; -- - denormal
report_error ("xnor 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("xnor 1 test", out1, out1t);
wait for clock_period;
out1t := "00000000000000000000000000000000"; -- 0
report_error ("and 0 test", out1, out1t);
wait for clock_period;
out1t := "01111111100000000000000000000000"; -- + inf
report_error ("and 1 test", out1, out1t);
wait for clock_period;
out1t := to_float(3, out1t);
report_error ("2 + 1 test", out1, out1t);
wait for clock_period;
report_error ("1 + 2 test", out1, out1t);
wait for clock_period;
report_error ("2 + 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 + 2 test", out1, out1t);
wait for clock_period;
out1t := to_float(2, out1t);
report_error ("2 * 1 test", out1, out1t);
wait for clock_period;
report_error ("1 * 2 test", out1, out1t);
wait for clock_period;
report_error ("2 * 1.0 test", out1, out1t);
wait for clock_period;
report_error ("1.0 * 2 test", out1, out1t);
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
Common/sim/unisim.make
-27
View File
@@ -1,27 +0,0 @@
# -------------------------------------------------
# Compile script for GHDL
# -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -------------------------------------------------
# Global options
# -------------------------------------------------
LANG_STD := 93c
IEEE_STD := standard
WORK_LIB := unisim
TARGET := ghdl
STD_LIB_PATH := xilinx/libsrc/unisims
# -------------------------------------------------
# Target options
# -------------------------------------------------
SRCS := $(STD_LIB_PATH)/unisim_VPKG.vhd
SRCS += $(STD_LIB_PATH)/unisim_VCOMP.vhd
SRCS += $(STD_LIB_PATH)/unisim_SMODEL.vhd
SRCS += $(STD_LIB_PATH)/unisim_VITAL.vhd
GHDL_OPTS := -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk
Common/sim/xilinx/libsrc/unisims/unisim_SECUREIP.vhd
-66369
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File diff suppressed because it is too large Load Diff
Common/sim/xilinx/libsrc/unisims/unisim_SMODEL.vhd
-41318
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File diff suppressed because it is too large Load Diff
Common/sim/xilinx/libsrc/unisims/unisim_VCOMP.vhd
-28337
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File diff suppressed because it is too large Load Diff
Common/sim/xilinx/libsrc/unisims/unisim_VITAL.vhd
-196520
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File diff suppressed because it is too large Load Diff
Common/sim/xilinx/libsrc/unisims/unisim_VPKG.vhd
-1463
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File diff suppressed because it is too large Load Diff
Common/sim/xilinx/libsrc/unisims/unisim_virtex5_SMODEL.vhd
-66348
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File diff suppressed because it is too large Load Diff
Common/tools/jcpu/eval_scan.rb
-42
View File
@@ -1,42 +0,0 @@
#!/usr/bin/env ruby
str1 = %Q!lbl: dc "Hallo", ", ", 0, 1, " der","Jens"!
i=0;
def get_stri_lit (str)
res = [""];
state = "out"
j = 0;
k = 0;
for i in (0..str.length-1)
c = str[i];
nstate = state
case state
when "out"
if c == "\""[0]
nstate = "in"
end
when "in"
if c == "\""[0]
nstate = "out"
if j > 0
k = k + 1;
res[k] = ""
end
else
res[k] = res[k] + format("%c", c);
j = j + 1;
end
end
state = nstate
end;
return res
end
get_stri_lit(str1).each do |word|
puts word
end
Common/tools/jcpu/insrom.rb
-46
View File
@@ -1,46 +0,0 @@
#!/usr/bin/env ruby
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: Insertion of code fragments into templates
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
arg = $*
rom_filename = arg[0].to_s
tpl_filename = arg[1].to_s
subst_pattern = "JASM_ROM_INSERT_HERE"
# --------------------------------------------------------
# Open file
# --------------------------------------------------------
romfile = File.open(rom_filename, "r")
tplfile = File.open(tpl_filename, "r")
re = Regexp.new(subst_pattern)
while (line = tplfile.gets)
puts line
line.scan(re).each do |word|
romfile.each do |raw_line|
puts raw_line
end
end
end
Common/tools/jcpu/irom.vhd.tpl
-32
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@@ -1,32 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.cpu_pkg.all;
-- JASM_ROM_INSERT_HERE
Common/tools/jcpu/irom_ld.vhd.tpl
-151
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@@ -1,151 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: loadable ROM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.cpu_pkg.all;
ENTITY irom IS
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in inst_addr_t;
dout : out inst_t
);
END irom;
ARCHITECTURE loadable OF irom IS
-- JASM_ROM_INSERT_HERE
signal jtag_ld_clk : STD_LOGIC;
signal jtag_ld_we : STD_LOGIC;
signal jtag_ld_addr : inst_addr_t;
signal jtag_ld_dout : inst_t;
signal jtag_ld_din : inst_t;
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (31 downto 0);
constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
begin
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
jtag_ld_clk <= bs_update1;
jtag_ld_we <= bs_sel;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;
-- user_rego <= id;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ:
process(clk, ce)
begin
if rising_edge(clk) and ce = '1' then
dout <= imem_rom(to_integer(addr));
end if;
end process;
PROM_WRITE:
process(jtag_ld_clk, jtag_ld_we)
begin
if rising_edge(jtag_ld_clk) then
if jtag_ld_we = '1' then
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
else
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
end if;
end if;
end process;
--------------------------------------------------------------------------
end loadable;
Common/tools/jcpu/jasm.bak.rb
-494
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@@ -1,494 +0,0 @@
#!/usr/bin/env ruby
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: A small assembler for the JCPU
# Copyright (C) 2007 J. Ahrensfeld
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
# For questions and ideas, please contact the author at jens@jayfield.org
# ---------------------------------------------------------------------
arg = $*
MAX_SIZE_ROM = 1024
PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
ENTITY_NAME = "rom"
ENTITY_DATA_TYPE = "inst_t"
ENTITY_ADDR_TYPE = "inst_addr_t"
OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
# --------------------------------------------------------
# Open file
# --------------------------------------------------------
filename = arg.to_s
if !File.exists?(filename)
STDERR.puts "#{filename} does not exist"
exit 1
end
# --------------------------------------------------------
# Pass 1
# --------------------------------------------------------
lc = 0 # Line counter
pc = 0 # Program counter
chip_dc = [0,0,0,0] # chip data counter
xmem_dc = 0 # xmem data counter
curr_segment = "UNDEF";
page = 0
label_list=[[],[]]
instr_list=[nil]
file = File.open(filename, "r")
file.each do |raw_line|
lc += 1
# Make all upper case
iline = "#{raw_line}".strip.upcase
# Remove comments
iline = iline.gsub(/;.*/, "")
# Split instruction at spaces
iline_member = iline.split(" ")
if iline_member[0] == nil
next
end
mc = 0;
label = nil
clean_line = nil
if (iline_member[0] =~ /\w+:/)
mc += 1
label = iline_member[0].delete(":")
if label_list.rindex(label) != nil
STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
exit 1
end
end
case iline_member[mc]
when nil
value = format("0x%3.3X",pc)
when "EQU"
if 0 == (iline_member[mc+1] =~ /\d+/)
value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
else
value = iline_member[mc+1]
end
when "ORG", "CODE"
pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
value = format("0x%3.3X",pc)
when "CDATA", "CMEM"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
exit 1
end
curr_segment = "CMEM";
page = iline_member[mc+1].to_i(16)
when "XDATA", "XMEM"
curr_segment = "XMEM";
when "DC"
len = 0;
iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte|
len += 1
end
if curr_segment == "CMEM"
STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
exit 1
else
value = format("0x%2.2X",xmem_dc)
puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
xmem_dc += len
end
when "DB"
len = iline_member[mc+1].to_i
if curr_segment == "CMEM"
value = format("0x%2.2X",chip_dc[page])
puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
chip_dc[page] += len
else
value = format("0x%2.2X",xmem_dc)
puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
xmem_dc += len
end
else
op_line = iline_member[mc+1..iline_member.nitems].to_s
value = format("0x%3.3X",pc)
opc = iline_member[mc]
if iline_member[mc+1] != nil
op1 = op_line.gsub(/,+.*$/, "")
end
if iline_member[mc+2] != nil
op2 = op_line.scan(/,.+$/).to_s.delete(", ")
end
if instr_list[pc] == nil
instr_list[pc] = [lc, pc, opc , op1 , op2]
pc += 1
else
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
exit 1
end
end;
# Push labels
if label
label_list = label_list + [label, value]
end
end
file.close
# --------------------------------------------------------
def instr(opcode)
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
end
def tcl_bits(pc, opcode)
return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
end
def instr_k(opcode, k)
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
end
def tcl_bits_k(pc, opcode, k)
return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
end
def instr_r(opcode, r)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
end
def tcl_bits_r(pc, opcode, r)
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
end
def instr_kr(opcode, k, r)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
end
def tcl_bits_kr(pc, opcode, k, r)
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
end
def instr_rk(opcode, r, k)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
end
def tcl_bits_rk(pc, opcode, r, k)
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
end
def instr_rr(opcode, ra, rb)
return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
end
def tcl_bits_rr(pc, opcode, ra, rb)
return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
end
# --------------------------------------------------------
# Read mnemonic set
# --------------------------------------------------------
filename = OPC_LIST_NAME
if !File.exists?(filename)
STDERR.puts "#{filename} does not exist"
exit 1
end
mnemo_list = []
num_opcodes = 0
file = File.open(filename, "r")
file.each do |raw_line|
mnemo_list[num_opcodes] = raw_line.split(" ")[1]
num_opcodes += 1
end
# --------------------------------------------------------
# Pass 2
# --------------------------------------------------------
pc = 0
opc_start = 2
num_errors = 0
vhdl_trans_list = [nil]
vhdl_comment_list = [nil]
vhdl_tcl_list = [nil]
instr_list.each do |instruct|
# puts instruct
if instruct == nil
vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
vhdl_comment_list[pc] = format("0x%3.3X:", pc)
vhdl_tcl_list[pc] = tcl_bits(pc, 0)
pc += 1
next
end
# determine arglen of instruction
ilen = 0
if instruct[opc_start+1] == nil
arglen = 0
elsif instruct[opc_start+2] == nil
arglen = 1
elsif instruct[opc_start+3] == nil
arglen = 2
end
# Symbol substitution
error = false
for i in (1..3)
subst_pos = opc_start+i
if instruct[subst_pos] == nil
next
end
expr_token = ""
expr_subst = nil
is_direct = true;
# instruct[subst_pos] = instruct[subst_pos].delete(" ")
# checks R0 .. R16, Mnemonics
instr_str = instruct[subst_pos]
if 0 == (instr_str =~ /\(.+\)/)
instr_str = instr_str.delete("()")
is_direct = false;
end
expr_token = instr_str.split(/\+|\-|\*|\//)[0]
if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
idx = label_list.rindex(expr_token)
if idx != nil
expr_subst = label_list[idx+1]
instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
else
STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
error = true
end
end
if expr_subst != nil
if 0 == (expr_subst =~ /\d+/)
if is_direct == true
instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
else
instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
end
else
if 0 != (expr_subst =~ /R[0-9]+/)
STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
error = true
end
end
end
end
# Parse operands
reg = [0,0]
kk = 0
format = instruct[opc_start]
for i in (0..1)
if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
# Check indirect addressing
reg[i] = instruct[opc_start+i+1].delete("R()").to_i
format += "|R"
if reg[i] > 15
STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
error = true
end
else
if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
kk = instruct[opc_start+i+1].delete("()").to_i(16)
format += "|K"
end
end
if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
format += "i";
end
end
# Output instruction
opcode = mnemo_list.rindex(format).to_i
mnemo = instruct[2];
case format
when "NOP", "HALT", "RET", "RETI"
vhdl_trans_list[pc] = instr(opcode)
vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
when "MOVC|R|Ri", "MOVX|R|Ri"
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
when "MOVC|Ri|R", "MOVX|Ri|R"
vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
vhdl_trans_list[pc] = instr_k(opcode, kk)
vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
vhdl_trans_list[pc] = instr_r(opcode, reg[0])
vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
when "TST|R"
kk = 0
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("CMP|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "INC|R"
kk = 1
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("ADD|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "DEC|R"
kk = 1
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("SUB|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
else
STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
error = true
end
if error
num_errors += 1
break
end
vhdl_comment_list[pc] = minstr_comment
puts vhdl_trans_list[pc] + " -- " + minstr_comment
pc += 1
end
# --------------------------------------------------------
# Output ROM file
# --------------------------------------------------------
if num_errors == 0
filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("ENTITY %s IS\n", ENTITY_NAME)
file.puts format("\tPort (\n")
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE)
file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
file.puts format("\t);\n")
file.puts format("END %s;\n", ENTITY_NAME)
file.puts format("\n")
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
file.puts format("\n")
file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
file.puts format("\n")
file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..pc-2)
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
end;
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
file.puts format("\t);\n")
file.puts format("\n")
file.puts format("begin")
file.puts format("\n")
file.puts format("PROM_READ:")
file.puts format("\tprocess(clk, ce)\n")
file.puts format("\tbegin\n")
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
file.puts format("\t\tend if;\n")
file.puts format("\tend process;\n")
file.puts format("\n")
file.puts format("end %s;\n", PROJECT_NAME)
puts format("ROM file written to \"%s\"\n",filename)
file.close
end
if num_errors == 0
filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..pc-2)
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
end;
if pc < (MAX_SIZE_ROM-1)
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
for i in (pc..(MAX_SIZE_ROM-2))
file.puts "\t\t" + instr(0) + ",\n"
end;
file.puts "\t\t" + instr(0) + "\n"
else
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
end
file.puts format("\t);\n")
puts format("PREINIT file written to \"%s\"\n",filename)
file.close
end
if num_errors == 0
filename = format("rom_%s.tcl.snip", PROJECT_NAME)
file = File.open(filename, "w")
for i in (0..pc-1)
# Chipscope 8.1
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
# Chipscope 9.1
file.puts format("\# %s", vhdl_comment_list[i])
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
end;
puts format("TCL snippet written to \"%s\"\n",filename)
file.close
end
# --------------------------------------------------------
# Output final statistics
# --------------------------------------------------------
if num_errors == 0
puts "Program uses #{pc} instruction addresses"
puts "No errors found"
exit 0
else
puts "#{num_errors} errors found"
exit 1
end
Common/tools/jcpu/jasm.rb
-811
View File
@@ -1,811 +0,0 @@
#!/usr/bin/env ruby
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: A small assembler for the JCPU
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
arg = $*
FILE_SUFFIX = "jsm"
IROM_MAX_SIZE = 1024
IROM_ENTITY_NAME = "irom"
IROM_DATA_TYPE = "inst_t"
IROM_ADDR_TYPE = "inst_addr_t"
XROM_MAX_SIZE = 256
XROM_DATA_TYPE = "dmem_data_t"
XROM_ADDR_TYPE = "dmem_addr_t"
XROM_ENTITY_NAME = "xrom"
OPC_LIST_NAME = __dir__ + "/opc.list"
# --------------------------------------------------------
class Parser
def curr_segment
@curr_segment
end
def curr_segment=(arg)
@curr_segment=arg
end
def add_label(labelname, addr)
@label_list = @label_list + [labelname, addr]
end
def getLabelIdByName(label)
return @label_list.rindex(label)
end
def getLabelNameById(id)
return @label_list[id]
end
def put_instr(name, lc, opc , op1 , op2)
if get_instr != nil
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
exit 1
end
@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
end
def get_instr
return @instr_list[@pc]
end
def put_xmem(value, lc)
if get_xmem != nil
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
exit 1
end
@xmem[xmem_dc] = value
@xmem_dc = xmem_dc + 1
end
def get_xmem
return @xmem[xmem_dc]
end
def xmem
return @xmem
end
def put_cmem(value, lc)
if get_cmem(page) != nil
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
exit 1
end
@cmem[page][cmem_dc] = value
@cmem_dc[page] = cmem_dc + 1
end
def get_cmem(pg)
return @cmem[pg][cmem_dc]
end
def cmem(page)
return @cmem[page]
end
def cmem_dc=(addr)
@cmem_dc[page] = addr
end
def cmem_dc
@cmem_dc[page]
end
def xmem_dc=(addr)
@xmem_dc = addr
end
def xmem_dc
@xmem_dc
end
def page=(page)
@page = page;
end
def page
@page;
end
def pc=(pc)
@pc = pc;
if (pc > @pc_max)
@pc_max = pc
end
end
def pc
@pc;
end
def pc_max
@pc_max;
end
def instr_list
@instr_list
end
def label_list
@label_list
end
def initialize()
@pc_max = 0
@pc = 0 # Program counter
@cmem_dc = [0,0,0,0] # chip data counter
@xmem_dc = 0 # xmem data counter
@curr_segment = "UNDEF";
@page = 0
@label_list=[[],[]]
@instr_list=[nil]
@cmem = [[],[]];
@xmem = [];
end
def method_missing(name, *args)
puts "I don't know the method #{name}"
end
end
# --------------------------------------------------------
def parse(name, obj)
lc = 0 # Line counter
file = File.open(name, "r")
file.each do |raw_line|
lc += 1
# Make all upper case
iline = "#{raw_line}".strip
# Remove comments
iline = iline.gsub(/;.*/, "")
# Split instruction at spaces
iline_member = iline.split(" ")
if iline_member[0] == nil
next
end
mc = 0;
label = nil
clean_line = nil
if (iline_member[0] =~ /\w+:/)
mc += 1
label = iline_member[0].delete(":")
if obj.getLabelIdByName(label) != nil
STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
exit 1
end
end
token = iline_member[mc]
mcnt = iline_member.count{|x| !x.nil?}
if token
token = token.upcase
end
case token
when nil
if obj.curr_segment == "CMEM"
curr_addr = format("0x%3.3X",obj.cmem_dc)
elsif obj.curr_segment == "XMEM"
curr_addr = format("0x%3.3X",obj.xmem_dc)
elsif obj.curr_segment == "CODE"
curr_addr = format("0x%3.3X",obj.pc)
else
STDERR.puts format("Error in line %d: Undefined segment", lc)
exit 1
end
when "INCLUDE"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
inc_name = iline_member[mc+1].delete("\"")
puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
parse(inc_name, obj)
when "EQU"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
if 0 == (iline_member[mc+1] =~ /\d+/)
curr_addr = format("0x%2.2X",eval(iline_member[mc+1..mcnt][0].to_s))
else
curr_addr = iline_member[mc+1]
end
when "ORG"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
offset = eval(iline_member[mc+1..mcnt][0].to_s)
case obj.curr_segment
when "CODE"
obj.pc = offset
curr_addr = format("0x%3.3X",obj.pc)
when "CMEM"
obj.cmem_dc = offset
when "XMEM"
obj.xmem_dc = offset
end
when "CODE"
curr_addr = format("0x%3.3X",obj.pc)
obj.curr_segment = "CODE";
when "CDATA", "CMEM"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
obj.curr_segment = "CMEM";
obj.page = iline_member[mc+1].to_i(16)
when "XDATA", "XMEM"
obj.curr_segment = "XMEM";
when "DC"
len = 0;
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
if obj.curr_segment == "CMEM"
STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
exit 1
elsif obj.curr_segment == "XMEM"
curr_addr = format("0x%2.2X",obj.xmem_dc)
dc_old = obj.xmem_dc;
val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
# Parse string literals
val_array.each do |item|
if 0 == (item =~ /.*\".*\"/)
str = item.delete("\"")
for nn in (0..str.length-1)
value = str[nn].ord
obj.put_xmem(value, lc);
len += 1
end;
else
argument = item
obj.put_xmem(eval(argument), lc);
len += 1
end
end
puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
else
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
exit 1
end
when "DB"
if iline_member[mc+1] == nil
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
exit 1
end
len = eval(iline_member[mc+1]).to_i
if obj.curr_segment == "CMEM"
curr_addr = format("0x%2.2X",obj.cmem_dc)
puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
for nn in (1..len)
obj.put_cmem(0, lc)
end
elsif obj.curr_segment == "XMEM"
curr_addr = format("0x%2.2X",obj.xmem_dc)
puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
for nn in (1..len)
obj.put_xmem(0, lc)
end
else
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
exit 1
end
else
if obj.curr_segment != "CODE"
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
exit 1
end
op_line = iline_member[mc+1..mcnt]
curr_addr = format("0x%3.3X",obj.pc)
opc = token
if iline_member[mc+1] != nil
op1 = op_line[0].to_s.gsub(/,+.*$/, "")
end
if iline_member[mc+2] != nil
op2 = op_line[1].to_s.gsub(/,+.*$/, "")
end
obj.put_instr(name, lc, opc, op1, op2)
obj.pc = obj.pc + 1
end;
# Push labels
if label
obj.add_label(label, curr_addr)
end
end
file.close
return obj
end
# --------------------------------------------------------
# Instruction formatting
# --------------------------------------------------------
def instr(opcode)
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
end
def tcl_bits(pc, opcode)
return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
end
def instr_k(opcode, k)
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
end
def tcl_bits_k(pc, opcode, k)
return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
end
def instr_r(opcode, r)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
end
def tcl_bits_r(pc, opcode, r)
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
end
def instr_kr(opcode, k, r)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
end
def tcl_bits_kr(pc, opcode, k, r)
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
end
def instr_rk(opcode, r, k)
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
end
def tcl_bits_rk(pc, opcode, r, k)
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
end
def instr_rr(opcode, ra, rb)
return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
end
def tcl_bits_rr(pc, opcode, ra, rb)
return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
end
# --------------------------------------------------------
# Open file
# --------------------------------------------------------
filename = arg[0].to_s
if !File.exists?(filename)
STDERR.puts "#{filename} does not exist"
exit 1
end
PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
# --------------------------------------------------------
# Pass 1
# --------------------------------------------------------
first_pass = Parser.new();
parse(filename, first_pass)
# --------------------------------------------------------
# Read mnemonic set
# --------------------------------------------------------
filename = OPC_LIST_NAME
if !File.exists?(filename)
STDERR.puts "#{filename} does not exist"
exit 1
end
mnemo_list = []
num_opcodes = 0
file = File.open(filename, "r")
file.each do |raw_line|
mnemo_list[num_opcodes] = raw_line.split(" ")[1]
num_opcodes += 1
end
# --------------------------------------------------------
# Pass 2
# --------------------------------------------------------
pc = 0
opc_start = 2
num_errors = 0
vhdl_trans_list = [nil]
vhdl_comment_list = [nil]
vhdl_tcl_list = [nil]
# ToDo: Use class-methods
label_list = first_pass.label_list
instr_list = first_pass.instr_list
instr_list.each do |instruct|
# puts instruct
if instruct == nil
vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
vhdl_comment_list[pc] = format("0x%3.3X:", pc)
vhdl_tcl_list[pc] = tcl_bits(pc, 0)
pc += 1
next
end
# determine arglen of instruction
ilen = 0
if instruct[opc_start+1] == nil
arglen = 0
elsif instruct[opc_start+2] == nil
arglen = 1
elsif instruct[opc_start+3] == nil
arglen = 2
end
# Symbol substitution
error = false
for i in (1..2)
subst_pos = opc_start+i
if instruct[subst_pos] == nil
next
end
expr_token = ""
expr_subst = nil
is_direct = true;
# checks R0 .. R16, Mnemonics
instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
if (nil != (instruct[subst_pos] =~ /'high/))
instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
end
instr_str = instruct[subst_pos]
if 0 == (instr_str =~ /\(.+\)/)
instr_str = instr_str.delete("()")
is_direct = false;
end
expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
idx = label_list.rindex(expr_token)
if idx != nil
expr_subst = label_list[idx+1]
instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
else
STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
error = true
end
end
if expr_subst != nil
if 0 == (expr_subst =~ /\d+/)
if is_direct == true
instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
else
instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
end
else
if 0 != (expr_subst =~ /R[0-9]+/)
STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
error = true
end
end
end
end
# Parse operands
reg = [0,0]
kk = 0
format = instruct[opc_start]
for i in (0..1)
if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
# Check indirect addressing
reg[i] = instruct[opc_start+i+1].delete("R()").to_i
format += "|R"
if reg[i] > 15
STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
error = true
end
else
if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
kk = eval(instruct[opc_start+i+1].delete("()"))
format += "|K"
end
end
if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
format += "i";
end
end
if error
num_errors += 1
break
end
# Output instruction
opcode = mnemo_list.rindex(format).to_i
mnemo = instruct[2];
case format
# Native instructions
when "NOP", "HALT", "RET", "RETI", "SETC"
vhdl_trans_list[pc] = instr(opcode)
vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
when "MOVC|R|Ri", "MOVX|R|Ri"
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
when "MOVC|Ri|R", "MOVX|Ri|R"
vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
kk = kk % 256;
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
kk = kk % 256;
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
when "SUB|K|R", "SUBC|K|R"
kk = kk % 256;
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
vhdl_trans_list[pc] = instr_k(opcode, kk)
vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
vhdl_trans_list[pc] = instr_r(opcode, reg[0])
vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
# Synthetic instructions
when "CLRC"
kk = 0;
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
opcode = mnemo_list.rindex("SUB|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "TST|R"
kk = 0
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("CMP|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "NEG|R"
kk = 0
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("SUB|K|R").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "NOT|R"
kk = 0
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("XOR|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "INC|R"
kk = 1
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("ADD|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
when "DEC|R"
kk = 1
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
opcode = mnemo_list.rindex("SUB|R|K").to_i
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
else
STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
error = true
end
if error
num_errors += 1
break
end
vhdl_comment_list[pc] = minstr_comment
puts vhdl_trans_list[pc] + " -- " + minstr_comment
pc += 1
end
# --------------------------------------------------------
# Output ROM file
# --------------------------------------------------------
if num_errors == 0
# I-ROM VHDL-ROM
filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
file.puts format("\tPort (\n")
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE)
file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
file.puts format("\t);\n")
file.puts format("END %s;\n", IROM_ENTITY_NAME)
file.puts format("\n")
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
file.puts format("\n")
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
file.puts format("\n")
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..[IROM_MAX_SIZE, pc].min-2)
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
end;
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
file.puts format("\t);\n")
file.puts format("\n")
file.puts format("begin")
file.puts format("\n")
file.puts format("PROM_READ:")
file.puts format("\tprocess(clk, ce)\n")
file.puts format("\tbegin\n")
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
file.puts format("\t\tend if;\n")
file.puts format("\tend process;\n")
file.puts format("\n")
file.puts format("end %s;\n", PROJECT_NAME)
puts format("I-ROM file written to \"%s\"\n",filename)
file.close
# I-ROM VHDL-ROM (loadable)
filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..pc-2)
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
end;
if pc < (IROM_MAX_SIZE-1)
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
for i in (pc..(IROM_MAX_SIZE-2))
file.puts "\t\t" + instr(0) + ",\n"
end;
file.puts "\t\t" + instr(0) + "\n"
else
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
end
file.puts format("\t);\n")
puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
file.close
# I-ROM TCL-Loader
filename = format("%s.irom.tcl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("# ---------------------------------------------------------------");
file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
file.puts format("# User 1")
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
for i in (0..pc-1)
# Chipscope 8.1
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
# Chipscope 9.1
file.puts format("\# %s", vhdl_comment_list[i])
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
end;
puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
file.close
# X-ROM VHDL-ROM
filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
file.puts format("\tPort (\n")
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE)
file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
file.puts format("\t);\n")
file.puts format("END %s;\n", XROM_ENTITY_NAME)
file.puts format("\n")
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
file.puts format("\n")
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
file.puts format("\n")
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..XROM_MAX_SIZE-2)
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
end;
i = XROM_MAX_SIZE-1
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
file.puts format("\t);\n")
file.puts format("\n")
file.puts format("begin")
file.puts format("\n")
file.puts format("PROM_READ:")
file.puts format("\tprocess(clk, ce)\n")
file.puts format("\tbegin\n")
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
file.puts format("\t\tend if;\n")
file.puts format("\tend process;\n")
file.puts format("\n")
file.puts format("end %s;\n", PROJECT_NAME)
puts format("X-ROM file written to \"%s\"\n",filename)
file.close
# X-ROM VHDL-ROM (loadable)
filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
file.puts format("\t(\n");
for i in (0..XROM_MAX_SIZE-2)
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
end;
i = XROM_MAX_SIZE-1
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i].to_i(), i)
file.puts format("\t);\n")
puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
file.close
# X-ROM JTAG-Loader
filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
file = File.open(filename, "w")
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
file.puts format("# ---------------------------------------------------------------");
file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
file.puts format("# User 2")
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
for i in (0..first_pass.xmem.length-1)
# Chipscope 8.1
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
# Chipscope 9.1
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
end;
puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
file.close
end
# --------------------------------------------------------
# Output final statistics
# --------------------------------------------------------
if num_errors == 0
puts "Program uses #{first_pass.pc_max} instruction addresses"
puts "No errors found"
exit 0
else
puts "#{num_errors} errors found"
exit 1
end
Common/tools/jcpu/lib/cg.inc.jsm
-72
View File
@@ -1,72 +0,0 @@
; -------------------------------------------------
; lcd.inc.jsm
; -------------------------------------------------
; needs xio-address equates for
; reg_cg_char_addr: equ 0xXX ; RW
; reg_cg_line_addr: equ 0xXX ; RW
; reg_cg_data: equ 0xXX ; RW
; reg_cg_ctrl: equ 0xXX ; WO
; needs delay.inc.jsm
; -------------------------------------------------
cg_clr_line: push R0
mov R0, 2
xout (reg_cg_ctrl), R0
pop R0
ret
; -------------------------------------------------
cg_clr_screen: push R0
mov R0, 1
xout (reg_cg_ctrl), R0
pop R0
ret
; -------------------------------------------------
; R0 : char address
; R1 : line address
cg_set_addr: call cg_wait_rdy
xout (reg_cg_line_addr), R1
xout (reg_cg_char_addr), R0
ret
; -------------------------------------------------
; R0 : character
cg_putchar: call cg_wait_rdy
xout (reg_cg_data), R0
ret
; -------------------------------------------------
; R1 : ptr to string
cg_puts: push R0
cg_p_lp: movx R0, (R1)
inc R1
tst R0
jz ex_cgp
call cg_putchar
jmp cg_p_lp
ex_cgp: pop R0
ret
; -------------------------------------------------
; R1 : ptr to string
cg_clr_puts: call cg_clr_line
call cg_puts
ret
; -------------------------------------------------
; R1 : ptr to string
cg_puts_clr: call cg_puts
call cg_clr_line
ret
; -------------------------------------------------
cg_wait_rdy: push R0
cg_wr_lp: xin R0, (reg_hwstat)
and R0, 0x02
jz cg_wr_lp
pop R0
ret
; -------------------------------------------------
Common/tools/jcpu/lib/cregs.inc.jsm
-7
View File
@@ -1,7 +0,0 @@
; JCPU On-Chip register
cpu_revision: equ 0x00 ; RO
cpu_control: equ 0x01 ; R/W
cpu_status: equ 0x02 ; RO
cpu_int_ctrl: equ 0x03 ; RW
cpu_cmem_high: equ 0x04 ; RW
cpu_stack_high: equ 0x05 ; RW
Common/tools/jcpu/lib/delays.inc.jsm
-64
View File
@@ -1,64 +0,0 @@
; -------------------------------------------------
; Delays
; -------------------------------------------------
delay1s: push R15
mov R15, 10
loop1s: call delay100ms
dec R15
jnz loop1s
pop R15
ret
delay100ms: push R15
mov R15, 10
loop100ms: call delay10ms
dec R15
jnz loop100ms
pop R15
ret
delay10ms: push R15
mov R15, 10
loop10ms: call delay1ms
dec R15
jnz loop10ms
pop R15
ret
delay1ms: push R15
mov R15, 10
loop1ms: call delay100us
dec R15
jnz loop1ms
pop R15
ret
delay100us: push R15
mov R15, 10
loop100us: call delay10us
dec R15
jnz loop100us
pop R15
ret
delay10us: push R15
mov R15, 99
loop10us: nop
nop
nop
dec R15
jnz loop10us
pop R15
ret
delay1us: push R15
mov R15, 9
loop1us: nop
nop
nop
dec R15
jnz loop1us
pop R15
ret
; -------------------------------------------------
Common/tools/jcpu/lib/lcd.inc.jsm
-208
View File
@@ -1,208 +0,0 @@
; -------------------------------------------------
; lcd.inc.jsm
; -------------------------------------------------
; needs xmem-address definition for
; - lcd_port (LCD-Base)
; needs delay.inc.jsm
; -------------------------------------------------
lcd_cmd: equ 0x00
lcd_rd: equ 0x20
lcd_data: equ 0x40
lcd_enable: equ 0x80
LCD_CMD_Z1: equ 0x80
LCD_CMD_Z2: equ 0xC0
LCD_CMD_CLEAR: equ 0x01
; -------------------------------------------------
; Init LCD
; -------------------------------------------------
LCD_init: mov R2, 0x00
mov R0, 0x03
call _write_lcd
call delay10ms
mov R2, 0x00
mov R0, 0x03
call _write_lcd
call delay10ms
mov R2, 0x00
mov R0, 0x02
call _write_lcd
call delay1ms
; 1. Function set: 4-Bit mode, two display lines
mov R0, 0x28
call LCD_writecmd
; 2. Display on, no cursor
mov R0, 0x0C
call LCD_writecmd
; 3. Cursor shift during write
mov R0, 0x06
call LCD_writecmd
; 4. Display clear
mov R0, 0x01
call LCD_writecmd
ret
; -------------------------------------------------
; LCD_waitbsy
; -------------------------------------------------
LCD_waitbsy: push R0
bsy_loop: call LCD_readstat
and R0, 0x80
jz ex_bsy
call delay1us
jmp bsy_loop
ex_bsy: pop R0
ret
; -------------------------------------------------
; LCD_writecmd
; -------------------------------------------------
; R0 = cmd
LCD_writeaddr:
LCD_writecmd: push R2
mov R2, lcd_cmd
call LCD_write
pop R2
ret
; -------------------------------------------------
; LCD_putsx
; -------------------------------------------------
; R1 = address of null-terminated string in XMEM
LCD_putsx: push R0
putsx_loop: movx R0, (R1)
inc R1
tst R0
jz putsx_ex
call LCD_writechar
jmp putsx_loop
putsx_ex: pop R0
ret
; -------------------------------------------------
; LCD_putsc
; -------------------------------------------------
; R1 = address of null-terminated string in CMEM
LCD_putsc: push R0
putsc_loop: movc R0, (R1)
inc R1
tst R0
jz putsc_ex
call LCD_writechar
jmp putsc_loop
putsc_ex: pop R0
ret
; -------------------------------------------------
; LCD_writechar
; -------------------------------------------------
; R0 = char
LCD_writedata:
LCD_writechar: push R2
mov R2, lcd_data
call LCD_write
pop R2
ret
; -------------------------------------------------
; LCD_write
; -------------------------------------------------
; R0 = input
; R2 = register
LCD_write: call LCD_waitbsy
push R0
swap R0
call _write_lcd
pop R0
call _write_lcd
ret
; -------------------------------------------------
; LCD_readstat
; -------------------------------------------------
; R0 = status
LCD_readstat: push R2
mov R2, lcd_cmd
call LCD_read
pop R2
ret
; -------------------------------------------------
; LCD_read
; -------------------------------------------------
; R0 = output
; R2 = register
LCD_read: call _read_lcd
swap R0
push R0
call _read_lcd
pop R2
or R0, R2
ret
; -------------------------------------------------
; _write
; -------------------------------------------------
; R0 = input
_write_lcd: push R1
and R0, 0x0F
mov R1, R0
or R1, R2
xout (lcd_port), R1
call delay1us
mov R1, R0
or R1, R2
or R1, lcd_enable
xout (lcd_port), R1
call delay1us
mov R1, R0
or R1, R2
xout (lcd_port), R1
call delay1us
or R1, lcd_rd
xout (lcd_port), R1
pop R1
ret
; -------------------------------------------------
; _read
; -------------------------------------------------
; R0 = output
_read_lcd: push R1
mov R1, lcd_rd
or R1, R2
xout (lcd_port), R1
call delay1us
mov R1, lcd_rd
or R1, R2
or R1, lcd_enable
xout (lcd_port), R1
call delay1us
xin R0, (lcd_port)
and R0, 0x0F
mov R1, lcd_rd
or R1, R2
xout (lcd_port), R1
call delay1us
pop R1
ret
Common/tools/jcpu/lib/mul8x8.inc.jsm
-42
View File
@@ -1,42 +0,0 @@
; -------------------------------------------------
; mul8x8.inc.jsm
; -------------------------------------------------
; -------------------------------------------------
; Parameter:
; R0 : operand 1
; R1 : operand 2
; Return:
; R0 : product low
; R1 : product high
mul8x8: push R2
push R3
push R4
mov R4, R1
mov R1, 0
mov R2, 0
mov R3, 0
loop1: cmp R4, 0x01
jeq ende1
shr R4
jnc next1
add R2, R0
addc R3, R1
next1: shl R0
rolc R1
jmp loop1
ende1: add R0, R2
addc R1, R3
pop R4
pop R3
pop R2
ret
; -------------------------------------------------
Common/tools/jcpu/lib/uart.inc.jsm
-58
View File
@@ -1,58 +0,0 @@
; -------------------------------------------------
; uart.inc.jsm
; -------------------------------------------------
; needs xmem-address definition for
; - uart_status (Status register)
; - uart_data (Data register)
UART_TX_EMPTY: equ 0x01
UART_TX_FULL: equ 0x02
UART_TX_CMPL: equ 0x04
UART_RX_PRESENT: equ 0x10
; -------------------------------------------------
; uart_puts
; -------------------------------------------------
; R1 : ptr to string
uart_puts: push R0
u_p_lp: movx R0, (R1)
inc R1
tst R0
jz ex_ugp
call uart_putchar
jmp u_p_lp
ex_ugp: pop R0
ret
; -------------------------------------------------
; uart_putchar
; -------------------------------------------------
; R0 = input
uart_putchar: jmp sout
; -------------------------------------------------
; sout
; -------------------------------------------------
; R0 = input
sout: push R1
sout1: xin R1, (uart_status)
and R1, UART_TX_FULL
jnz sout1
xout (uart_data), R0
pop R1
ret
; -------------------------------------------------
; sin
; -------------------------------------------------
; R0 = output
sin: push R1
sin1: xin R1, (uart_status)
and R1, UART_RX_PRESENT
jnz sin1
xin R0, (uart_data)
pop R1
ret
; -------------------------------------------------
Common/tools/jcpu/lib/utils.inc.jsm
-32
View File
@@ -1,32 +0,0 @@
; -------------------------------------------------
; utils.inc.jsm
; -------------------------------------------------
; -------------------------------------------------
; Parameter
; R0 : Bin value in lower nibble
; Return
; R0 : Hex character representing lower nibble
nibble2hex: and R0, 0x0F
cmp R0, 0x0A
jlt isNum1
add R0, 0x07
isNum1: add R0, 0x30
ret
; -------------------------------------------------
; Parameter
; R0 : Bin value
; Return
; R0 : Hex character high
; R1 : Hex character low
bin2hex: push R0
call nibble2hex
mov R1, R0
pop R0
swap R0
call nibble2hex
ret
; -------------------------------------------------
Common/tools/jcpu/opc.list
-64
View File
@@ -1,64 +0,0 @@
0 NOP
1 HALT
2 MOV|R|R
3 MOV|R|K
4 MOVX|R|Ri
5 MOVX|R|Ki
6 MOVX|Ri|R
7 MOVX|Ri|K
8 MOVX|Ki|R
9 MOVC|R|Ri
10 MOVC|R|Ki
11 MOVC|Ri|R
12 MOVC|Ri|K
13 MOVC|Ki|R
14 CMP|R|R
15 CMP|R|K
16 ADD|R|R
17 ADD|R|K
18 ADDC|R|R
19 ADDC|R|K
20 SUB|R|R
21 SUB|R|K
22 SUBC|R|R
23 SUBC|R|K
24 AND|R|R
25 AND|R|K
26 OR|R|R
27 OR|R|K
28 XOR|R|R
29 XOR|R|K
30 SHL|R
31 SHR|R
32 ROL|R
33 ROR|R
34 ROLC|R
35 RORC|R
36 XOUT|Ki|R
37 XOUT|Ri|K
38 COUT|Ki|R
39 COUT|Ri|K
40 XIN|R|Ki
41 CIN|R|Ki
42 SWAP|R
43 SETC
44 UNDEF
45 UNDEF
46 SUB|K|R
47 SUBC|K|R
48 JMP|K
49 JZ|K
50 JNZ|K
51 JC|K
52 JNC|K
53 JLT|K
54 JGT|K
55 JLE|K
56 JGE|K
57 JEQ|K
58 JNE|K
59 CALL|K
60 PUSH|R
61 POP|R
62 RET
63 RETI
Common/tools/jcpu/regx.rb
-20
View File
@@ -1,20 +0,0 @@
#!/usr/bin/env ruby
st = "\033[7m"
en = "\033[m"
while TRUE
print "str> "
STDOUT.flush
str = gets
break if not str
str.chop!
print "pat> "
STDOUT.flush
re = gets
break if not re
re.chop!
str.gsub! re, "#{st}\\&#{en}"
print str, "\n"
end
print "\n"
Common/tools/jcpu/rom.tcl.tpl
-61
View File
@@ -1,61 +0,0 @@
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
# ---------------------------------------------------------------------
# For Chipscope 9.1
# ---------------------------------------------------------------------
# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)\\bin\\nt
source csejtag.tcl
namespace import ::chipscope::*
# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
# Create session
set handle [::chipscope::csejtag_session create 0]
# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
set CSE_OP $CSEJTAG_SHIFT_READWRITE
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
# Write Program
# JASM_ROM_INSERT_HERE
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit
Common/tools/jcpu/templates.rb
-44
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@@ -1,44 +0,0 @@
#!/usr/bin/env ruby
template = <<'END'
-- (tv #1342) read output FIFO
(
cycles => 1,
cm_i => bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
sep => msg(""),
cm_o => bus_no_ack,
irq => (others => '0')
),
-- (tv #1343) wait while FIFO is read
(
cycles => 2,
cm_i => bus_wait_ack,
sep => msg(""),
cm_o => bus_no_ack,
irq => (others => '0')
),
-- (tv #1343) wait for ack
(
cycles => 1,
cm_i => bus_wait_ack,
sep => msg(""),
cm_o => bus_read_ack(dat => #{exp_data}),
irq => (others => '0')
),
END
puts "KS-128 testvectors:\n"
puts "\n" * 3
0.upto(10) { |sk_no|
3.downto(0) { |sl_no|
exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
t = template.gsub(/"/, '\\"')
puts eval("format(\"#{t}\")")
}
}
Common/tools/jcpu/xrom.vhd.tpl
-32
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@@ -1,32 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.cpu_pkg.all;
-- JASM_ROM_INSERT_HERE
Common/tools/jcpu/xrom_ld.vhd.tpl
-151
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@@ -1,151 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: loadable ROM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.cpu_pkg.all;
ENTITY xrom IS
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in dmem_addr_t;
dout : out dmem_data_t
);
END xrom;
ARCHITECTURE loadable OF xrom IS
-- JASM_ROM_INSERT_HERE
signal jtag_ld_clk : STD_LOGIC;
signal jtag_ld_we : STD_LOGIC;
signal jtag_ld_addr : dmem_addr_t;
signal jtag_ld_dout : dmem_data_t;
signal jtag_ld_din : dmem_data_t;
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (15 downto 0);
constant id : unsigned (15 downto 0) := X"BEEF";
begin
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
jtag_ld_clk <= bs_update1;
jtag_ld_we <= bs_sel;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
-- user_rego <= id;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ:
process(clk, ce)
begin
if rising_edge(clk) and ce = '1' then
dout <= xmem_rom(to_integer(addr));
end if;
end process;
PROM_WRITE:
process(jtag_ld_clk, jtag_ld_we)
begin
if rising_edge(jtag_ld_clk) then
if jtag_ld_we = '1' then
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
else
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
end if;
end if;
end process;
--------------------------------------------------------------------------
end loadable;
Common/tools/mips/Makefile
-26
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@@ -1,26 +0,0 @@
CFLAGS=-O2
CC=gcc
PREFIX=/usr/local
all: romgen ramgen flashgen flashgen_tlb packhex
romgen: ./src/romgen.c
$(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen
ramgen: ./src/ramgen.c
$(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen
flashgen: ./src/flashgen.c
$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen
flashgen_tlb: ./src/flashgen.c
$(CC) $(CFLAGS) -DSDRAM_BASE=0x80000000 -DFLASH_BASE_MEM=0x88000000 ./src/flashgen.c -lm -o ./flashgen_tlb
packhex: ./src/packhex.c
$(CC) $(CFLAGS) ./src/packhex.c -lm -o ./packhex
install:
cp romgen $(PREFIX)/bin
cp ramgen $(PREFIX)/bin
cp flashgen $(PREFIX)/bin
clean:
rm -rf romgen* ramgen* flashgen*
Common/tools/mips/src/flashgen.c
-187
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@@ -1,187 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <stdint.h>
#ifndef SDRAM_BASE
#define SDRAM_BASE 0x40000000
#endif
#ifndef FLASH_BASE_MEM
#define FLASH_BASE_MEM 0x00000000
#endif
#define MAGIC 0x4A464931 // "JFI1" in big-endian;
uint8_t _g_bytes[4] = {0x12, 0x34, 0x56, 0x78};
uint8_t _g_bytes2[4] = {0};
int IsEndianBig(void)
{
int i, result;
uint8_t *pBuf8;
uint16_t *pBuf16;
uint32_t *pBuf32;
uint16_t halve;
uint32_t word;
halve = 0x1234;
word = 0x12345678;
result = -1;
for (i=0; i < 4; i++)
_g_bytes2[i] = _g_bytes[i];
pBuf8 = (uint8_t*)&word;
if (((*pBuf8+0) == 0x12) && (*(pBuf8+1) == 0x34) && (*(pBuf8+2) == 0x56) && (*(pBuf8+3) == 0x78))
{
pBuf8 = (uint8_t*)&halve;
if (((*pBuf8+0) == 0x12) && (*(pBuf8+1) == 0x34))
{
result = 1;
}
}
pBuf8 = (uint8_t*)&word;
if (((*pBuf8+0) == 0x78) && (*(pBuf8+1) == 0x56) && (*(pBuf8+2) == 0x34) && (*(pBuf8+3) == 0x12))
{
pBuf8 = (uint8_t*)&halve;
if (((*pBuf8+0) == 0x34) && (*(pBuf8+1) == 0x12))
{
result = 0;
}
}
return result;
}
uint32_t conv_endian32(uint32_t src)
{
uint32_t dst;
dst = (0xFF000000 & (src << 24))
| (0x00FF0000 & (src << 8))
| (0x0000FF00 & (src >> 8))
| (0x000000FF & (src >> 24));
return dst;
};
// --------------------------------------------------------------
typedef struct _sflash_img_hdr_t
{
uint32_t magic;
uint32_t target_addr;
uint32_t img_offset;
uint32_t img_size;
uint32_t hdr_next;
uint8_t img_name[128];
uint8_t res[108];
} flash_img_hdr_t;
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
// --------------------------------------------------------------
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_flash[1024];
char name_prj[1024];
char *pBuf;
uint32_t *pBuf32;
flash_img_hdr_t img_hdr = {0};
FILE *pFile;
int filesize;
long start, end;
int i;
if (argc < 2)
{
fprintf(stderr, "Usage: flashgen <input file> [-{EL|EB}]\n");
return 1;
}
pFilenameIn = argv[1];
pFile = fopen(pFilenameIn, "rb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
basename(pFilenameIn, name_prj);
sprintf(name_flash, "%s.flash.bin", name_prj);
// determine filesize
fseek(pFile, 0, SEEK_SET);
start = ftell(pFile);
fseek(pFile, 0, SEEK_END);
end = ftell(pFile);
fseek(pFile, 0, SEEK_SET);
filesize = (end-start);
pBuf = (char*)malloc(filesize);
filesize = fread(pBuf, 1, filesize, pFile);
fclose(pFile);
pFile = fopen(name_flash, "wb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", name_flash);
return 1;
}
img_hdr.magic = MAGIC;
img_hdr.target_addr = SDRAM_BASE;
img_hdr.img_size = filesize;
img_hdr.img_offset = FLASH_BASE_MEM + sizeof(flash_img_hdr_t);
img_hdr.hdr_next = FLASH_BASE_MEM;
if (argc == 3)
{
if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B'))
{
if (1 == IsEndianBig())
{
img_hdr.magic = conv_endian32(MAGIC);
pBuf32 = (uint32_t*)pBuf;
for (i=0; i < filesize/4; i ++)
pBuf32[i] = pBuf32[i]; // don't convert data
}
else
{
pBuf32 = (uint32_t*)pBuf;
for (i=0; i < filesize/4; i ++)
pBuf32[i] = conv_endian32(pBuf32[i]); // convert data
}
}
}
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
fwrite(pBuf, 1, filesize, pFile);
fclose(pFile);
return 0;
}
Common/tools/mips/src/packhex.c
-568
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@@ -1,568 +0,0 @@
/***** P A C K H E X . C ************************************************
*
* Packhex is a hex-file compaction utility. It attempts to concatenate
* hex records to produce more size-efficient packaging.
*
* Limitations: Input files must be correctly formatted. This utility
* is not robust enough to detect hex-record formatting
* errors.
*
* Published: May 1993 Embedded Systems Programming magazine
* "Creating Faster Hex Files"
*
* URL: ESP magazine: http://www.embedded.com
* Source Code: ftp://ftp.mfi.com/pub/espmag/1993/pakhex.zip
*
* Author: Mark Gringrich
*
* Compiler: Microsoft C 6.0
* cl /F 1000 packhex.c
*
*
* $Id: packhex.c,v 1.9 2004/04/20 07:07:08 ralf Exp $
*
**************************************************************************/
/* #define SMALLER_RECORDS */
#ifdef SMALLER_RECORDS
#define MAX_LEN_S1_RECS 128
#define MAX_LEN_S2_RECS 128
#define MAX_LEN_S3_RECS 128
#else
#define MAX_LEN_S1_RECS 252
#define MAX_LEN_S2_RECS 251
#define MAX_LEN_S3_RECS 250
#endif
/*--------------------------------- includes ---------------------------------*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#if 0
#include "config.h"
#ifndef VMS
#ifndef HAVE_STRERROR
extern int sys_nerr;
extern char *sys_errlist[];
#define strerror( _err ) \
((_err) < sys_nerr) ? sys_errlist [(_err)] : "unknown error"
#else /* HAVE_STRERROR */
char *strerror ();
#endif
#else /* VMS */
char *strerror (int,...);
#endif
#endif
#if defined(__unix__) && !defined(EXIT_FAILURE)
#define EXIT_FAILURE -1
#define EXIT_SUCCESS 0
#endif
/*--------------------------------- defines ----------------------------------*/
#define YES 1
#define MAX_LINE_SIZE 600
#define EOS '\0'
/*---------------------------------- macros ----------------------------------*/
/* Convert ASCII hexadecimal digit to value. */
#define HEX_DIGIT( C ) ( ( ( ( C ) > '9' ) ? ( C ) + 25 : ( C ) ) & 0xF )
/*--------------------------------- typedefs ---------------------------------*/
typedef unsigned char Boolean;
typedef unsigned char Uchar;
typedef unsigned int Uint;
typedef unsigned long Ulong;
typedef struct /* Functions and constant returning Hex-record vital stats. */
{
Boolean ( *is_data_record )( char * );
Ulong ( *get_address )( char * );
Uint ( *get_data_count )( char * );
const Uint max_data_count;
char *( *get_data_start )( char * );
void ( *put_data_record )( Uint, Ulong, char * );
} Rec_vitals;
/*--------------------------- function prototypes ----------------------------*/
Rec_vitals * identify_first_data_record( char *, int );
Ulong get_ndigit_hex( char *, int );
/*----------------------------- Intel Hex format -----------------------------*/
/*
* Intel Hex data-record layout
*
* :aabbbbccd...dee
*
* : - header character
* aa - record data byte count, a 2-digit hex value
* bbbb - record address, a 4-digit hex value
* cc - record type, a 2-digit hex value:
* "00" is a data record
* "01" is an end-of-data record
* "02" is an extended-address record
* "03" is a start record
* d...d - data (always an even number of chars)
* ee - record checksum, a 2-digit hex value
* checksum = 2's complement
* [ (sum of bytes: aabbbbccd...d) modulo 256 ]
*/
Boolean is_intel_data_rec( char * rec_str )
{
return( ( rec_str[ 0 ] == ':' ) && ( rec_str[ 8 ] == '0' ) );
}
Uint get_intel_rec_data_count( char * rec_str )
{
return( ( Uint ) get_ndigit_hex( rec_str + 1, 2 ) );
}
Ulong get_intel_rec_address( char * rec_str )
{
return( get_ndigit_hex( rec_str + 3, 4 ) );
}
char * get_intel_rec_data_start( char * rec_str )
{
return( rec_str + 9 );
}
void put_intel_data_rec( Uint count, Ulong address, char * data_str )
{
char *ptr;
Uint sum = count + ( address >> 8 & 0xff ) + ( address & 0xff );
for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
sum += ( Uint ) get_ndigit_hex( ptr, 2 );
printf(
":%02X%04lX00%s%02X\n", count, address, data_str, (~sum + 1) & 0xff
);
}
Rec_vitals intel_hex =
{
is_intel_data_rec,
get_intel_rec_address,
get_intel_rec_data_count,
255, /* Maximum data bytes in a record. */
get_intel_rec_data_start,
put_intel_data_rec
};
/*------------------------- Motorola S1-record format ------------------------*/
/*
* Motorola S-record data-record layout
*
* Sabbc...cd...dee
*
* S - header character
* a - record type, a 1-digit value:
* "0" is a header record
* "1" is a 2-byte-address data record
* "2" is a 3-byte-address data record
* "3" is a 4-byte-address data record
* "7" is a 4-byte-address end-of-data record
* "8" is a 3-byte-address end-of-data record
* "9" is a 2-byte-address end-of-data record
* bb - record length in bytes, a 2-digit hex value
* (record length doesn't count the header/type
* chars and checksum byte)
* c...c - record address, a 4-, 6-, or 8-digit value,
* depending on record type
* d...d - data (always an even number of chars)
* ee - record checksum, a 2-digit hex value
* checksum = 1's complement
* [ (sum of all bytes: bbc..cd...d) modulo 256 ]
*/
#define S1_COUNT_OFFSET 3
Boolean is_moto_s1_data_rec( char * rec_str )
{
return ( ( rec_str[ 0 ] == 'S' ) && ( rec_str[ 1 ] == '1' ) );
}
Uint get_moto_s1_rec_data_count( char * rec_str )
{
return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S1_COUNT_OFFSET );
}
Ulong get_moto_s1_rec_address( char * rec_str )
{
return( get_ndigit_hex( rec_str + 4, 4 ) );
}
char * get_moto_s1_rec_data_start( char * rec_str )
{
return( rec_str + 8 );
}
void put_moto_s1_data_rec( Uint count, Ulong address, char * data_str )
{
char *ptr;
Uint sum = S1_COUNT_OFFSET + count +
( address >> 8 & 0xff ) + ( address & 0xff );
for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
sum += ( Uint ) get_ndigit_hex( ptr, 2 );
printf(
"S1%02X%04lX%s%02X\n",
count + S1_COUNT_OFFSET, address, data_str, ~sum & 0xff
);
}
Rec_vitals motorola_s1_rec =
{
is_moto_s1_data_rec,
get_moto_s1_rec_address,
get_moto_s1_rec_data_count,
MAX_LEN_S1_RECS, /* Maximum data bytes in a record. */
get_moto_s1_rec_data_start,
put_moto_s1_data_rec
};
/*------------------------- Motorola S2-record format ------------------------*/
#define S2_COUNT_OFFSET 4
Boolean is_moto_s2_data_rec( char * rec_str )
{
return ( ( rec_str[ 0 ] == 'S' ) && ( rec_str[ 1 ] == '2' ) );
}
Uint get_moto_s2_rec_data_count( char * rec_str )
{
return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S2_COUNT_OFFSET );
}
Ulong get_moto_s2_rec_address( char * rec_str )
{
return( get_ndigit_hex( rec_str + 4, 6 ) );
}
char * get_moto_s2_rec_data_start( char * rec_str )
{
return( rec_str + 10 );
}
void put_moto_s2_data_rec( Uint count, Ulong address, char * data_str )
{
char *ptr;
Uint sum = S2_COUNT_OFFSET + count + ( address >> 16 & 0xff ) +
( address >> 8 & 0xff ) +
( address & 0xff );
for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
sum += ( Uint ) get_ndigit_hex( ptr, 2 );
printf(
"S2%02X%06lX%s%02X\n",
count + S2_COUNT_OFFSET, address, data_str, ~sum & 0xff
);
}
Rec_vitals motorola_s2_rec =
{
is_moto_s2_data_rec,
get_moto_s2_rec_address,
get_moto_s2_rec_data_count,
MAX_LEN_S2_RECS, /* Maximum data bytes in a record. */
get_moto_s2_rec_data_start,
put_moto_s2_data_rec
};
/*------------------------- Motorola S3-record format ------------------------*/
#define S3_COUNT_OFFSET 5
Boolean is_moto_s3_data_rec( char * rec_str )
{
return ( ( rec_str[ 0 ] == 'S' ) && ( rec_str[ 1 ] == '3' ) );
}
Uint get_moto_s3_rec_data_count( char * rec_str )
{
return( ( Uint ) get_ndigit_hex( rec_str + 2, 2 ) - S3_COUNT_OFFSET );
}
Ulong get_moto_s3_rec_address( char * rec_str )
{
return( get_ndigit_hex( rec_str + 4, 8 ) );
}
char * get_moto_s3_rec_data_start( char * rec_str )
{
return( rec_str + 12 );
}
void put_moto_s3_data_rec( Uint count, Ulong address, char * data_str )
{
char *ptr;
Uint sum = S3_COUNT_OFFSET + count + ( address >> 24 & 0xff ) +
( address >> 16 & 0xff ) +
( address >> 8 & 0xff ) +
( address & 0xff );
for ( ptr = data_str ; *ptr != EOS ; ptr += 2 )
sum += ( Uint ) get_ndigit_hex( ptr, 2 );
printf(
"S3%02X%08lX%s%02X\n",
count + S3_COUNT_OFFSET, address, data_str, ~sum & 0xff
);
}
Rec_vitals motorola_s3_rec =
{
is_moto_s3_data_rec,
get_moto_s3_rec_address,
get_moto_s3_rec_data_count,
MAX_LEN_S3_RECS, /* Maximum data bytes in a record. */
get_moto_s3_rec_data_start,
put_moto_s3_data_rec
};
/*-------------------- Put your favorite hex format here ---------------------*/
/*
* * * * The following is a template for an additional hex format: * * *
*
*
* Boolean is_X_data_rec( char * rec_str ) {}
*
* Uint get_X_rec_data_count( char * rec_str ) {}
*
* Ulong get_X_rec_address( char * rec_str ) {}
*
* char * get_X_rec_data_start( char * rec_str ) {}
*
* void put_X_data_rec( Uint count, Ulong address, char * data_str ) {}
*
* Rec_vitals X_rec =
* {
* is_X_data_rec,
* get_X_rec_address,
* get_X_rec_data_count,
* MAXIMUM DATA BYTES IN A RECORD,
* get_X_rec_data_start,
* put_X_data_rec
* };
*
*/
/*----------------------------------------------------------------------------*/
/*
* Put address of additional Rec_vitals structures
* in this array, before the NULL entry.
*/
Rec_vitals *formats[] =
{
&intel_hex,
&motorola_s1_rec,
&motorola_s2_rec,
&motorola_s3_rec,
( Rec_vitals * ) NULL
};
/**** main *****************************************************************
*
*
* Expects: Nothing (no command-line parameters).
*
* Returns: Exit status (EXIT_SUCCESS or EXIT_FAILURE).
*
* Reads hex records on the standard input and attempts to
* splice adjacent data fields together. Results appear on
* the standard output.
*
*******************************************************************************/
int main(
int argc,
char **argv
)
{
char inbuff[ MAX_LINE_SIZE ], outbuff[ MAX_LINE_SIZE ];
char *in_dptr, *out_dptr;
int d_total, d_count, d_excess, n;
int length;
Ulong in_rec_addr, out_rec_addr = 0;
Rec_vitals *rptr;
/* Sift through file until first hex record is identified. */
rptr = identify_first_data_record( inbuff, MAX_LINE_SIZE );
if ( rptr == NULL )
{
fputs( "No hex records found.\n", stderr );
exit( EXIT_FAILURE );
}
/* Attempt data-record splicing until end-of-file is reached. */
d_total = 0;
for (;;) {
if ( rptr->is_data_record( inbuff ) == YES )
{ /* Input record is a data record. */
d_count = rptr->get_data_count( inbuff );
in_rec_addr = rptr->get_address( inbuff );
in_dptr = rptr->get_data_start( inbuff );
if ( d_total == 0 || in_rec_addr != out_rec_addr + d_total )
{ /* Begin a new output record. */
if ( d_total != 0 )
rptr->put_data_record( d_total, out_rec_addr, outbuff );
out_dptr = outbuff;
n = d_total = d_count;
out_rec_addr = in_rec_addr;
}
else if
( ( d_excess = d_total + d_count - rptr->max_data_count ) > 0 )
{ /* Output a maximum-length record, then start a new record. */
strncat( outbuff, in_dptr, 2 * ( d_count - d_excess ) );
rptr->put_data_record(
rptr->max_data_count, out_rec_addr, outbuff
);
in_dptr += 2 * ( d_count - d_excess );
out_dptr = outbuff;
n = d_total = d_excess;
out_rec_addr += rptr->max_data_count;
}
else
{ /* Append input record's data field with accumulated data. */
out_dptr = outbuff + ( 2 * d_total );
d_total += n = d_count;
}
strncpy( out_dptr, in_dptr, 2 * n );
out_dptr[ 2 * n ] = EOS;
}
else
{ /* Not a data record;
* flush accumulated data then echo non-data record.
*/
if ( d_total != 0 )
{
rptr->put_data_record( d_total, out_rec_addr, outbuff );
d_total = 0;
}
puts( inbuff );
}
inbuff[ MAX_LINE_SIZE - 1 ] = '\0';
if ( !fgets( inbuff, MAX_LINE_SIZE, stdin ) )
break;
if ( inbuff[ MAX_LINE_SIZE - 1 ] ) {
fprintf( stderr, "Input line too long" );
exit( 1 );
}
length = strlen(inbuff);
inbuff[length - 1] = '\0';
}
return ( EXIT_SUCCESS );
}
/**** identify_first_data_record *******************************************
*
* Expects: Pointer to hex-record line buffer.
*
* Returns: Pointer to hex-record structure (NULL if no match found).
*
* Reads the standard input, line by line, searching for a valid
* record header character. If a valid header is found, a pointer
* to the hex-record's type structure is returned, otherwise NULL.
*
* The input-stream pointer is left pointing to the first valid hex record.
*
*******************************************************************************/
Rec_vitals * identify_first_data_record( char * buff_ptr, int max_length )
{
Rec_vitals ** ptr;
int length;
for ( ;; ) {
buff_ptr[ max_length - 1 ] = '\0';
if ( !fgets( buff_ptr, max_length, stdin ) )
break;
if ( buff_ptr[ max_length - 1 ] ) {
fprintf( stderr, "Input line too long" );
exit( 1 );
}
length = strlen(buff_ptr);
buff_ptr[length - 1] = '\0';
for ( ptr = formats ; *ptr != ( Rec_vitals * ) NULL ; ptr++ )
if ( ( *ptr )->is_data_record( buff_ptr ) == YES )
return( *ptr ); /* Successful return. */
puts( buff_ptr ); /* Echo non-hex-record line. */
}
return( ( Rec_vitals * ) NULL ); /* Unsuccessful return. */
}
/**** get_ndigit_hex *******************************************************
*
* Expects: Pointer to first ASCII hexadecimal digit, number of digits.
*
* Returns: Value of hexadecimal string as an unsigned long.
*
*******************************************************************************/
Ulong get_ndigit_hex( char * cptr, int digits )
{
Ulong value;
for ( value = 0 ; --digits >= 0 ; cptr++ )
value = ( value * 16L ) + HEX_DIGIT( *cptr );
return( value );
}
Common/tools/mips/src/ramgen.c
-387
View File
@@ -1,387 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "ram"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) then\n");
fprintf(pFileOut, "\t\t\tif ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 2\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom_tcl[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
return 1;
}
pFilenameIn = argv[1];
if (argc == 3)
nbits_addr = atoi(argv[2]);
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
Common/tools/mips/src/romgen.c
-430
View File
@@ -1,430 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define INT8 char
#define INT16 short
#define INT32 long
#define UINT8 unsigned char
#define UINT16 unsigned short
#define UINT32 unsigned long
#define INT int
#define UINT unsigned int
#define FLOAT32 float
#define FLOAT64 double
#define ARCH_NAME "data"
#define ENT_NAME "rom"
#define JTAG_ADDR_WIDTH 16
UINT32 g_endianess_EB;
// --------------------------------------------------------------
UINT32 conv_endian32(UINT32 src)
{
UINT32 dst;
dst = (0xFF000000 & (src << 24))
| (0x00FF0000 & (src << 8))
| (0x0000FF00 & (src >> 8))
| (0x000000FF & (src >> 24));
return dst;
};
UINT32 to_big_endian32(UINT32 src)
{
#ifndef NATIVE_IS_BIG_ENDIAN
return conv_endian32(src);
#else
return src;
#endif
}
UINT32 from_big_endian32(UINT32 src)
{
#ifndef NATIVE_IS_BIG_ENDIAN
return conv_endian32(src);
#else
return src;
#endif
}
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
if (g_endianess_EB)
fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
else
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) then\n");
fprintf(pFileOut, "\t\t\tif ce = '1' then\n");
fprintf(pFileOut, "\t\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
if (g_endianess_EB)
fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
else
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, word_addr, filesize, romsize;
char binstr_addr[33];
char binstr_data[33];
char tpl[] =
{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fputs(tpl, pFileOut);
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
fprintf(pFileOut, "# User 1\n");
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
word_addr = 0;
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
if (g_endianess_EB)
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word));
else
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
word_addr++;
}
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
fprintf(pFileOut, "exit\n");
return 0;
}
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_prj[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
char name_rom_tcl[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
long start, end;
int word, i;
if (argc < 2)
{
fprintf(stderr, "Usage: romgen <input file> <num. word address bits> [-{EL|EB}]\n");
return 1;
}
pFilenameIn = argv[1];
nbits_addr = atoi(argv[2]);
g_endianess_EB = 0;
if (argc == 4)
{
if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B'))
g_endianess_EB = 1;
}
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
return 0;
}
Makefile
-23
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@@ -1,23 +0,0 @@
FOLDER ?= lib
TARGETS = $(shell find $(FOLDER)/ -name "*.make")
INSTR := $(foreach number,$(TARGETS),make -C $(shell dirname $(number)) -f $(shell basename $(number)) $(MAKECMDGOALS) &&) true
all:
$(INSTR)
elaborate:
$(INSTR)
run:
$(INSTR)
run_wave:
$(INSTR)
clean:
$(INSTR)
mrproper:
$(INSTR)
defs.mk
-3
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@@ -1,3 +0,0 @@
LIB_PATH := $(VHDL_HOME)/lib
VHDL_MAKE_HOME := $(VHDL_HOME)/Common/make
lib/CPUs/J1/doc/j1.pdf
BIN
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Binary file not shown.
lib/CPUs/J1/sim/tb_j1.do
-15
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@@ -1,15 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/ram_2c_2r_2w.vhd"
vcom -explicit -93 "../src/core/j1.vhd"
vcom -explicit -93 "../src/tb_j1.vhd"
vmap work
vsim -t 1ps -lib work tb_j1
do {tb_j1.wave.do}
view wave
view structure
view signals
run 1us
lib/CPUs/J1/sim/tb_j1.wave.do
-58
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@@ -1,58 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_j1/sys_clk_i
add wave -noupdate -format Logic /tb_j1/sys_rst_i
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_din
add wave -noupdate -format Logic /tb_j1/io_rd
add wave -noupdate -format Logic /tb_j1/io_wr
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_din
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_din
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_dout
add wave -noupdate -format Logic /tb_j1/data_we
add wave -noupdate -format Logic /tb_j1/data_en
add wave -noupdate -divider {J1 internals}
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/insn
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/immediate
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/ramrd
add wave -noupdate -format Literal /tb_j1/uut/dsp
add wave -noupdate -format Literal /tb_j1/uut/dsp2
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st0
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st02
add wave -noupdate -format Logic /tb_j1/uut/dstkw2
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc2
add wave -noupdate -format Literal /tb_j1/uut/rsp
add wave -noupdate -format Literal /tb_j1/uut/rsp2
add wave -noupdate -format Logic /tb_j1/uut/rstkw2
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstkd2
add wave -noupdate -format Logic /tb_j1/uut/ramwe2
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc_plus_1
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/dstack
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstack
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st1
add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rst0
add wave -noupdate -format Literal /tb_j1/uut/st0sel
add wave -noupdate -format Logic /tb_j1/uut/is_alu
add wave -noupdate -format Logic /tb_j1/uut/is_lit
add wave -noupdate -format Literal /tb_j1/uut/dd
add wave -noupdate -format Literal /tb_j1/uut/rd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1600185 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {1050 ns}
lib/CPUs/J1/src/core/j1.v
-187
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@@ -1,187 +0,0 @@
module j1(
input sys_clk_i, input sys_rst_i, input [15:0] io_din,
output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
wire [15:0] insn;
wire [15:0] immediate = { 1'b0, insn[14:0] };
wire [15:0] ramrd;
reg [4:0] dsp; // Data stack pointer
reg [4:0] _dsp;
reg [15:0] st0; // Return stack pointer
reg [15:0] _st0;
wire _dstkW; // D stack write
reg [12:0] pc;
reg [12:0] _pc;
reg [4:0] rsp;
reg [4:0] _rsp;
reg _rstkW; // R stack write
reg [15:0] _rstkD;
wire _ramWE; // RAM write enable
wire [15:0] pc_plus_1;
assign pc_plus_1 = pc + 1;
// The D and R stacks
reg [15:0] dstack[0:31];
reg [15:0] rstack[0:31];
always @(posedge sys_clk_i)
begin
if (_dstkW)
dstack[_dsp] = st0;
if (_rstkW)
rstack[_rsp] = _rstkD;
end
wire [15:0] st1 = dstack[dsp];
wire [15:0] rst0 = rstack[rsp];
// st0sel is the ALU operation. For branch and call the operation
// is T, for 0branch it is N. For ALU ops it is loaded from the instruction
// field.
reg [3:0] st0sel;
always @*
begin
case (insn[14:13])
2'b00: st0sel = 0; // ubranch
2'b10: st0sel = 0; // call
2'b01: st0sel = 1; // 0branch
2'b11: st0sel = insn[11:8]; // ALU
default: st0sel = 4'bxxxx;
endcase
end
`define RAMS 3
genvar i;
`define w (16 >> `RAMS)
`define w1 (`w - 1)
generate
for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram
// RAMB16_S18_S18
RAMB16_S2_S2
ram(
.DIA(0),
// .DIPA(0),
.DOA(insn[`w*i+`w1:`w*i]),
.WEA(0),
.ENA(1),
.CLKA(sys_clk_i),
.ADDRA({_pc}),
.DIB(st1[`w*i+`w1:`w*i]),
// .DIPB(2'b0),
.WEB(_ramWE & (_st0[15:14] == 0)),
.ENB(|_st0[15:14] == 0),
.CLKB(sys_clk_i),
.ADDRB(_st0[15:1]),
.DOB(ramrd[`w*i+`w1:`w*i]));
end
endgenerate
// Compute the new value of T.
always @*
begin
if (insn[15])
_st0 = immediate;
else
case (st0sel)
4'b0000: _st0 = st0;
4'b0001: _st0 = st1;
4'b0010: _st0 = st0 + st1;
4'b0011: _st0 = st0 & st1;
4'b0100: _st0 = st0 | st1;
4'b0101: _st0 = st0 ^ st1;
4'b0110: _st0 = ~st0;
4'b0111: _st0 = {16{(st1 == st0)}};
4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
4'b1001: _st0 = st1 >> st0[3:0];
4'b1010: _st0 = st0 - 1;
4'b1011: _st0 = rst0;
4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
4'b1101: _st0 = st1 << st0[3:0];
4'b1110: _st0 = {rsp, 3'b000, dsp};
4'b1111: _st0 = {16{(st1 < st0)}};
default: _st0 = 16'hxxxx;
endcase
end
wire is_alu = (insn[15:13] == 3'b011);
wire is_lit = (insn[15]);
assign io_rd = (is_alu & (insn[11:8] == 4'hc));
assign io_wr = _ramWE;
assign io_addr = st0;
assign io_dout = st1;
assign _ramWE = is_alu & insn[5];
assign _dstkW = is_lit | (is_alu & insn[7]);
wire [1:0] dd = insn[1:0]; // D stack delta
wire [1:0] rd = insn[3:2]; // R stack delta
always @*
begin
if (is_lit) begin // literal
_dsp = dsp + 1;
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end else if (is_alu) begin
_dsp = dsp + {dd[1], dd[1], dd[1], dd};
_rsp = rsp + {rd[1], rd[1], rd[1], rd};
_rstkW = insn[6];
_rstkD = st0;
end else begin // jump/call
// predicated jump is like DROP
if (insn[15:13] == 3'b001) begin
_dsp = dsp - 1;
end else begin
_dsp = dsp;
end
if (insn[15:13] == 3'b010) begin // call
_rsp = rsp + 1;
_rstkW = 1;
_rstkD = {pc_plus_1[14:0], 1'b0};
end else begin
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end
end
end
always @*
begin
if (sys_rst_i)
_pc = pc;
else
if ((insn[15:13] == 3'b000) |
((insn[15:13] == 3'b001) & (|st0 == 0)) |
(insn[15:13] == 3'b010))
_pc = insn[12:0];
else if (is_alu & insn[12])
_pc = rst0[15:1];
else
_pc = pc_plus_1;
end
always @(posedge sys_clk_i)
begin
if (sys_rst_i) begin
pc <= 0;
dsp <= 0;
st0 <= 0;
rsp <= 0;
end else begin
dsp <= _dsp;
pc <= _pc;
st0 <= _st0;
rsp <= _rsp;
end
end
endmodule // j1
lib/CPUs/J1/src/core/j1.vhd
-282
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@@ -1,282 +0,0 @@
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity j1 is
Generic
(
R_STACK_SIZE : natural := 32;
D_STACK_SIZE : natural := 32
);
Port
(
sys_clk_i : in std_logic;
sys_rst_i : in std_logic;
io_din : in unsigned(15 downto 0);
io_rd : out std_logic;
io_wr : out std_logic;
io_addr : out unsigned(15 downto 0);
io_dout : out unsigned(15 downto 0);
inst_din : in unsigned(15 downto 0);
inst_addr : out unsigned(12 downto 0);
data_addr : out unsigned(12 downto 0);
data_we : out std_logic;
data_en : out std_logic;
data_din : in unsigned(15 downto 0);
data_dout : out unsigned(15 downto 0)
);
end j1;
architecture behave of j1 is
signal insn : unsigned(15 downto 0);
signal immediate : unsigned(15 downto 0);
signal ramrd : unsigned(15 downto 0);
signal dsp : unsigned(4 downto 0); -- Data stack pointer (register)
signal dsp2 : unsigned(4 downto 0); -- register
signal st0 : unsigned(15 downto 0); -- Return stack pointer (register)
signal st02 : unsigned(15 downto 0); -- register
signal dstkW2 : std_logic; -- D stack write
signal pc : unsigned(12 downto 0); -- register
signal pc2 : unsigned(12 downto 0); -- register
signal rsp : unsigned(4 downto 0); -- register
signal rsp2 : unsigned(4 downto 0); -- register
signal rstkW2 : std_logic; -- register
signal rstkD2 : unsigned(15 downto 0); -- register
signal ramWE2 : std_logic; -- RAM write enable
signal pc_plus_1 : unsigned(15 downto 0);
type stack_t is array (integer range <>) of unsigned(15 downto 0);
signal dstack : stack_t(0 to D_STACK_SIZE-1); -- register
signal rstack : stack_t(0 to R_STACK_SIZE-1); -- register
signal st1 : unsigned(15 downto 0);
signal rst0 : unsigned(15 downto 0);
signal st0sel : unsigned(3 downto 0);
signal is_alu : BOOLEAN;
signal is_lit : BOOLEAN;
signal dd : unsigned(1 downto 0); -- D stack delta
signal rd : unsigned(1 downto 0); -- R stack delta
signal stack_ram_en : std_logic; -- helper for RAM R/W
signal stack_ram_we : std_logic; -- helper for RAM R/W
begin
-- LINE 25:
pc_plus_1 <= ("000" & pc) + 1;
-- LINE 37:
st1 <= dstack(to_integer(dsp));
rst0 <= rstack(to_integer(rsp));
immediate <= '1' & insn(14 downto 0);
-- LINE 112:
is_alu <= (insn(15 downto 13) = "011");
is_lit <= (insn(15) = '1');
-- LINE 115:
io_rd <= '1' when (is_alu and (insn(11 downto 8) = X"C")) else '0';
io_wr <= ramWE2;
io_addr <= st0;
io_dout <= st1;
ramWE2 <= '1' when (is_alu and (insn(5) = '1')) else '0';
dstkW2 <= '1' when (is_lit or (is_alu and insn(7) = '1')) else '0';
dd <= insn(1 downto 0);
rd <= insn(3 downto 2);
-- LINE 27:
-- The D and R stacks
proc_d_and_r_stack:
process(sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if dstkW2 = '1' then
dstack(to_integer(dsp2)) <= st0;
end if;
if rstkW2 = '1' then
rstack(to_integer(rsp2)) <= rstkD2;
end if;
end if;
end process;
-- LINE 40:
-- st0sel is the ALU operation. For branch and call the operation
-- is T, for 0branch it is N. For ALU ops it is loaded from the instruction
-- field.
proc_aluop_sel:
process(insn)
begin
case insn(14 downto 13) is
when "00" => st0sel <= "0000";
when "10" => st0sel <= "0000";
when "01" => st0sel <= "0001";
when "11" => st0sel <= insn(11 downto 8);
when others => st0sel <= "XXXX";
end case;
end process;
-- LINE 55:
-- define RAMS outside this module
insn <= inst_din;
inst_addr <= pc2(12 downto 0);
data_en <= not (st02(15) or st02(14));
data_we <= ramWE2 and not (st02(15) or st02(14));
ramrd <= data_din;
data_dout <= st1;
data_addr <= st02(13 downto 1);
-- LINE 85:
-- Compute the new value of T.
proc_alu:
process(insn, immediate, st0sel, st0, st1, rst0, rsp, dsp)
begin
if insn(15) = '1' then
st02 <= immediate;
else
case st0sel is
when "0000" => st02 <= st0;
when "0001" => st02 <= st1;
when "0010" => st02 <= st0 + st1;
when "0011" => st02 <= st0 and st1;
when "0100" => st02 <= st0 or st1;
when "0101" => st02 <= st0 xor st1;
when "0110" => st02 <= not st0;
when "0111" =>
if st1 = st0 then
st02 <= X"FFFF";
else
st02 <= X"0000";
end if;
when "1000" =>
if signed(st1) < signed(st0) then
st02 <= X"FFFF";
else
st02 <= X"0000";
end if;
when "1001" => st02 <= st1 srl to_integer(st0(3 downto 0));
when "1010" => st02 <= st0 - 1;
when "1011" => st02 <= rst0;
when "1100" =>
if st0(15) = '1' or st0(14) = '1' then -- LINE 104: ????
st02 <= io_din;
else
st02 <= ramrd;
end if;
when "1101" => st02 <= st1 sll to_integer(st0(3 downto 0));
when "1110" => st02 <= "000" & rsp & "000" & dsp; -- LINE 106: ????
when "1111" =>
if st1 < st0 then
st02 <= X"FFFF";
else
st02 <= X"0000";
end if;
when others => st02 <= "XXXXXXXXXXXXXXXX";
end case;
end if;
end process;
-- LINE 126:
proc_stack_ctrl:
process(is_lit, is_alu, pc2, dd, rd, insn, st0, pc_plus_1, rsp, dsp)
begin
if is_lit then -- literal
dsp2 <= dsp + 1;
rsp2 <= rsp;
rstkW2 <= '0';
rstkD2 <= "000" & pc2;
elsif is_alu then
dsp2 <= dsp + (dd(1) & dd(1) & dd(1) & dd);
rsp2 <= rsp + (rd(1) & rd(1) & rd(1) & rd);
rstkW2 <= insn(6);
rstkD2 <= st0;
else -- jump/call
-- predicated jump is like DROP
if insn(15 downto 13) = "001" then
dsp2 <= dsp - 1;
else
dsp2 <= dsp; -- *default
end if;
if insn(15 downto 13) = "010" then -- call
rsp2 <= rsp + 1;
rstkW2 <= '1';
rstkD2 <= pc_plus_1(14 downto 0) & '0';
else
rsp2 <= rsp; -- *default
rstkW2 <= '0'; -- *default
rstkD2 <= "000" & pc2; -- *default
end if;
end if;
end process;
-- LINE 157:
proc_pc:
process(sys_rst_i, is_alu, insn, pc, st0, rst0, pc_plus_1)
begin
if sys_rst_i = '1' then
pc2 <= pc;
else
if ((insn(15 downto 13) = "000")
or ((insn(15 downto 13) = "001")
and (st0 = X"0000"))
or (insn(15 downto 13) = "010")) then
pc2 <= insn(12 downto 0);
elsif is_alu and (insn(12) = '1') then -- return
pc2 <= rst0(13 downto 1); -- LINE 167: ????
else
pc2 <= pc_plus_1(12 downto 0); -- LINE 169: truncation ????
end if;
end if;
end process;
-- LINE 172:
proc_next:
process(sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_i = '1' then
pc <= (others => '0');
dsp <= (others => '0');
st0 <= (others => '0');
rsp <= (others => '0');
else
dsp <= dsp2;
pc <= pc2;
st0 <= st02;
rsp <= rsp2;
end if;
end if;
end process;
end behave;
lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd
-84
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@@ -1,84 +0,0 @@
--------------------------------------------------------------------------
-- Project: Generic RAM. Infers BlockRAM for Xilinx
-- This file: On-chip RAM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity ram_2c_2r_2w is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end ram_2c_2r_2w;
architecture Behavioral of ram_2c_2r_2w is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/CPUs/J1/src/tb_j1.vhd
-150
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@@ -1,150 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for embedded cpu with rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
ENTITY tb_j1 IS
END tb_j1;
ARCHITECTURE behavior OF tb_j1 IS
constant CLK_PERIOD : time := 10 ns;
-- Inputs
signal sys_clk_i : std_logic := '0';
signal sys_rst_i : std_logic := '1';
signal io_din : unsigned(15 downto 0) := (others => '0');
signal inst_din : unsigned(15 downto 0) := (others => '0');
signal data_din : unsigned(15 downto 0) := (others => '0');
-- Outputs
signal io_rd : std_logic;
signal io_wr : std_logic;
signal io_addr : unsigned(15 downto 0);
signal io_dout : unsigned(15 downto 0);
signal data_dout : unsigned(15 downto 0);
signal inst_addr : unsigned(12 downto 0);
signal data_addr : unsigned(12 downto 0);
signal data_we : std_logic;
signal data_en : std_logic;
type rom_t is array (integer range <>) of unsigned(15 downto 0);
signal rom : rom_t(0 to 15) :=
(
X"8123", -- 0000
X"0002", -- 0001
X"0005", -- 0002
X"8456", -- 0003
X"4008", -- 0004
X"0003", -- 0005
X"0000", -- 0006
X"0000", -- 0007
X"8456", -- 0008
X"8451", -- 0009
X"7000", -- 000A
X"0000", -- 000B
X"0000", -- 000C
X"0000", -- 000D
X"0000", -- 000E
X"0000" -- 000F
);
BEGIN
-- Instruction rom
process(sys_clk_i)
begin
if rising_edge(sys_clk_i) then
inst_din <= rom(to_integer(inst_addr(3 downto 0)));
end if;
end process;
uut: entity work.j1
PORT MAP
(
sys_clk_i => sys_clk_i,
sys_rst_i => sys_rst_i,
io_din => io_din,
io_rd => io_rd,
io_wr => io_wr,
io_addr => io_addr,
inst_din => inst_din,
inst_addr => inst_addr,
data_addr => data_addr,
data_we => data_we,
data_en => data_en,
data_din => data_din,
data_dout => data_dout
);
inst_ram: entity work.ram_2c_2r_2w
GENERIC MAP
(
addr_width => 13,
data_width => 16
)
PORT MAP(
clka => sys_clk_i,
clkb => sys_clk_i,
en_a => '1',
en_b => data_en,
we_a => '0',
we_b => data_we,
addr_a => (others => '0'), --inst_addr
addr_b => data_addr,
din_a => (others => '0'),
din_b => data_dout,
dout_a => open, -- inst_din
dout_b => data_din
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
sys_clk_i <= not sys_clk_i;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
sys_rst_i <= '0';
wait for 2*CLK_PERIOD;
wait for 1000*CLK_PERIOD;
assert false report "Test finished" severity error;
wait;
end process;
end behavior;
lib/CPUs/JCpu/Makefile
-17
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@@ -1,17 +0,0 @@
include $(VHDL_HOME)/defs.mk
TOOL_PATH := $(VHDL_HOME)/tools/jcpu
.PHONY: install uninstall
all: install
$(TOOL_PATH):
mkdir -p $@
install: $(TOOL_PATH)
cp -r tools/* $(TOOL_PATH)
chmod +x $(TOOL_PATH)/*.rb
uninstall:
rm -rf $(TOOL_PATH)
lib/CPUs/JCpu/asm/hallo_welt_uart.jsm
-74
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@@ -1,74 +0,0 @@
; -------------------------------------------------
; Constants
; -------------------------------------------------
; External RAM/ROM
xmem
crlf: dc 13, 10, 0
msg_txt1: dc "J-CPU V1.", 0
msg_txt2: dc "Ready.", 13, 10, 0
msg_txt3: dc "Mimi ist eine liebe Katze !!!", 13, 10, 0
; -------------------------------------------------
; Program
; -------------------------------------------------
code
reset: jmp init
org 0x001
; nop
reti
; -------------------------------------------------
; Main
; -------------------------------------------------
init: xin R0, (cpu_status)
call bin2hex
call uart_putchar
mov R0, R1
call uart_putchar
mov R1, crlf
call uart_puts
loop:
; Print line 0
mov R1, msg_txt1
call uart_puts
cin R0, (cpu_revision)
add R0, 0x30
call uart_putchar
mov R1, crlf
call uart_puts
; Print line 1
mov R1, msg_txt2
call uart_puts
; Print line 3
mov R1, msg_txt3
call uart_puts
mov R15, 160
fill_lp: tst R15
jz ex_fill
dec R15
mov R1, 48
ct_loop: cmp R1, 58
jeq ex_ct
mov R0, R1
inc R1
call uart_putchar
jmp ct_loop
ex_ct: jmp fill_lp
ex_fill: mov R1, crlf
call uart_puts
jmp loop
; -------------------------------------------------
include "./xregs.inc.jsm"
include "../../../../tools/jcpu/lib/cregs.inc.jsm"
include "../../../../tools/jcpu/lib/utils.inc.jsm"
include "../../../../tools/jcpu/lib/uart.inc.jsm"
include "../../../../tools/jcpu/lib/delays.inc.jsm"
lib/CPUs/JCpu/asm/hallo_welt_uart.tcl
-502
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@@ -1,502 +0,0 @@
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
# ---------------------------------------------------------------------
# For Chipscope 9.1
# ---------------------------------------------------------------------
# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)\\bin\\nt
source csejtag.tcl
namespace import ::chipscope::*
# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
# Create session
set handle [::chipscope::csejtag_session create 0]
# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
set CSE_OP $CSEJTAG_SHIFT_READWRITE
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
# Write Program
# JASM_ROM_INSERT_HERE
# Assembled from hallo_welt_uart.jsm
# ---------------------------------------------------------------
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
# User 1
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
# 0x000: JMP 0x002
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
# 0x001: RETI
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
# 0x002: XIN R00, (0x02)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00228020"
# 0x003: CALL 0x029
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B029"
# 0x004: CALL 0x039
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0043B039"
# 0x005: MOV R00, R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00502010"
# 0x006: CALL 0x039
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063B039"
# 0x007: MOV R01, 0x00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00703001"
# 0x008: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B030"
# 0x009: MOV R01, 0x03
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903031"
# 0x00A: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3B030"
# 0x00B: CIN R00, (0x00)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B29000"
# 0x00C: ADD R00, 0x30
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C11300"
# 0x00D: CALL 0x039
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D3B039"
# 0x00E: MOV R01, 0x00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E03001"
# 0x00F: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F3B030"
# 0x010: MOV R01, 0x0D
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "010030D1"
# 0x011: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113B030"
# 0x012: MOV R01, 0x16
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01203161"
# 0x013: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B030"
# 0x014: MOV R15, 0xA0
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403A0F"
# 0x015: TST R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0150F00F"
# 0x016: JZ 0x020
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01631020"
# 0x017: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0171501F"
# 0x018: MOV R01, 0x30
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01803301"
# 0x019: CMP R01, 0x3A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0190F3A1"
# 0x01A: JEQ 0x01F
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3901F"
# 0x01B: MOV R00, R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B02010"
# 0x01C: INC R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C11011"
# 0x01D: CALL 0x039
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D3B039"
# 0x01E: JMP 0x019
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E30019"
# 0x01F: JMP 0x015
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F30015"
# 0x020: MOV R01, 0x00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003001"
# 0x021: CALL 0x030
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0213B030"
# 0x022: JMP 0x009
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02230009"
# 0x023: AND R00, 0x0F
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "023190F0"
# 0x024: CMP R00, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0240F0A0"
# 0x025: JLT 0x027
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02535027"
# 0x026: ADD R00, 0x07
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02611070"
# 0x027: ADD R00, 0x30
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02711300"
# 0x028: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283E000"
# 0x029: PUSH R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0293C000"
# 0x02A: CALL 0x023
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A3B023"
# 0x02B: MOV R01, R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B02001"
# 0x02C: POP R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C3D000"
# 0x02D: SWAP R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D2A000"
# 0x02E: CALL 0x023
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B023"
# 0x02F: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F3E000"
# 0x030: PUSH R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0303C000"
# 0x031: MOVX R00, (R01)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03104010"
# 0x032: INC R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03211011"
# 0x033: TST R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0330F000"
# 0x034: JZ 0x037
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03431037"
# 0x035: CALL 0x039
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0353B039"
# 0x036: JMP 0x031
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03630031"
# 0x037: POP R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373D000"
# 0x038: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0383E000"
# 0x039: JMP 0x03A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0393003A"
# 0x03A: PUSH R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A3C001"
# 0x03B: XIN R01, (0x06)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B28061"
# 0x03C: AND R01, 0x02
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C19021"
# 0x03D: JNZ 0x03B
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D3203B"
# 0x03E: XOUT (0x02), R00
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E24020"
# 0x03F: POP R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F3D001"
# 0x040: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0403E000"
# 0x041: PUSH R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0413C001"
# 0x042: XIN R01, (0x06)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04228061"
# 0x043: AND R01, 0x10
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04319101"
# 0x044: JNZ 0x042
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04432042"
# 0x045: XIN R00, (0x02)
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04528020"
# 0x046: POP R01
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0463D001"
# 0x047: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0473E000"
# 0x048: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0483C00F"
# 0x049: MOV R15, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "049030AF"
# 0x04A: CALL 0x04F
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A3B04F"
# 0x04B: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B1501F"
# 0x04C: JNZ 0x04A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C3204A"
# 0x04D: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D3D00F"
# 0x04E: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3E000"
# 0x04F: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F3C00F"
# 0x050: MOV R15, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "050030AF"
# 0x051: CALL 0x056
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0513B056"
# 0x052: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0521501F"
# 0x053: JNZ 0x051
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05332051"
# 0x054: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0543D00F"
# 0x055: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0553E000"
# 0x056: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563C00F"
# 0x057: MOV R15, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "057030AF"
# 0x058: CALL 0x05D
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0583B05D"
# 0x059: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0591501F"
# 0x05A: JNZ 0x058
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A32058"
# 0x05B: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B3D00F"
# 0x05C: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C3E000"
# 0x05D: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D3C00F"
# 0x05E: MOV R15, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E030AF"
# 0x05F: CALL 0x064
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F3B064"
# 0x060: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0601501F"
# 0x061: JNZ 0x05F
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0613205F"
# 0x062: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623D00F"
# 0x063: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0633E000"
# 0x064: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0643C00F"
# 0x065: MOV R15, 0x0A
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "065030AF"
# 0x066: CALL 0x06B
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663B06B"
# 0x067: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0671501F"
# 0x068: JNZ 0x066
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06832066"
# 0x069: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0693D00F"
# 0x06A: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3E000"
# 0x06B: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B3C00F"
# 0x06C: MOV R15, 0x63
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C0363F"
# 0x06D: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D00000"
# 0x06E: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E00000"
# 0x06F: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F00000"
# 0x070: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0701501F"
# 0x071: JNZ 0x06D
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0713206D"
# 0x072: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723D00F"
# 0x073: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0733E000"
# 0x074: PUSH R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0743C00F"
# 0x075: MOV R15, 0x09
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750309F"
# 0x076: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07600000"
# 0x077: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07700000"
# 0x078: NOP
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07800000"
# 0x079: DEC R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0791501F"
# 0x07A: JNZ 0x076
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A32076"
# 0x07B: POP R15
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B3D00F"
# 0x07C: RET
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C3E000"
# Assembled from hallo_welt_uart.jsm
# ---------------------------------------------------------------
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
# User 2
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "000D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "010A"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "034A"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "042D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0543"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0650"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0755"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0820"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0956"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A31"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B2E"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D52"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E65"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F61"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1064"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1179"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "122E"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "130D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "140A"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "164D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1769"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "186D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1969"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A20"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B69"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C73"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D74"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E20"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F65"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2069"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2265"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2320"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "246C"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2569"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2665"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2762"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2865"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2920"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A4B"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B61"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D7A"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E65"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F20"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3021"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3121"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3221"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "330D"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "340A"
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500"
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit
lib/CPUs/JCpu/asm/make
+1 -1
View File
@@ -26,7 +26,7 @@
TARGET=$2
DSTDIR=$1
JASM_HOME=$VHDL_HOME/tools/jcpu
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
$JASM_HOME/jasm.rb $TARGET.jsm
lib/CPUs/JCpu/asm/opc.list
-64
View File
@@ -1,64 +0,0 @@
0 NOP
1 HALT
2 MOV|R|R
3 MOV|R|K
4 MOVX|R|Ri
5 MOVX|R|Ki
6 MOVX|Ri|R
7 MOVX|Ri|K
8 MOVX|Ki|R
9 MOVC|R|Ri
10 MOVC|R|Ki
11 MOVC|Ri|R
12 MOVC|Ri|K
13 MOVC|Ki|R
14 CMP|R|R
15 CMP|R|K
16 ADD|R|R
17 ADD|R|K
18 ADDC|R|R
19 ADDC|R|K
20 SUB|R|R
21 SUB|R|K
22 SUBC|R|R
23 SUBC|R|K
24 AND|R|R
25 AND|R|K
26 OR|R|R
27 OR|R|K
28 XOR|R|R
29 XOR|R|K
30 SHL|R
31 SHR|R
32 ROL|R
33 ROR|R
34 ROLC|R
35 RORC|R
36 XOUT|Ki|R
37 XOUT|Ri|K
38 COUT|Ki|R
39 COUT|Ri|K
40 XIN|R|Ki
41 CIN|R|Ki
42 SWAP|R
43 SETC
44 UNDEF
45 UNDEF
46 SUB|K|R
47 SUBC|K|R
48 JMP|K
49 JZ|K
50 JNZ|K
51 JC|K
52 JNC|K
53 JLT|K
54 JGT|K
55 JLE|K
56 JGE|K
57 JEQ|K
58 JNE|K
59 CALL|K
60 PUSH|R
61 POP|R
62 RET
63 RETI
lib/CPUs/JCpu/asm/xregs.inc.jsm
-41
View File
@@ -1,41 +0,0 @@
; External registers
btn_port: equ 0x00 ; RO
led_port: equ 0x01 ; R/W
uart_data: equ 0x02 ; R/W
lcd_port: equ 0x03 ; R/W
ctrl_reg: equ 0x04 ; R/W
CTRL_VGA_ENABLE: equ 0x04
CTRL_TIMER_ENABLE: equ 0x02
dip_port: equ 0x05 ; RO
uart_status: equ 0x06 ; RO
sdram_reg: equ 0x07 ; R/W
FIFO_CTRL_IS_CMD: equ 0x04
FIFO_CTRL_IS_WRITE: equ 0x10
FIFO_CTRL_IS_READ: equ 0x20
FIFO_STAT_CMD_FULL: equ 0x01
FIFO_STAT_CMD_EMPTY: equ 0x02
FIFO_STAT_WRITE_DATA_FULL: equ 0x04
FIFO_STAT_WRITE_DATA_EMPTY: equ 0x08
FIFO_STAT_READ_DATA_FULL: equ 0x10
FIFO_STAT_READ_DATA_EMPTY: equ 0x20
sdram_addr: equ 0x08 ; R/W
sdram_addr0: equ 0x08 ; R/W
sdram_addr1: equ 0x09 ; R/W
sdram_addr2: equ 0x0A ; R/W
reg_cg_char_addr: equ 0x0B ; RW
reg_cg_line_addr: equ 0x0C ; RW
reg_cg_data: equ 0x0D ; RW
reg_cg_ctrl: equ 0x0E ; WO
reg_hwstat: equ 0x0E ; RO
reg_color_red: equ 0x10 ; RW
reg_color_grn: equ 0x11 ; RW
reg_color_blu: equ 0x12 ; RW
uart_baudrate: equ 0x13 ; R/W
vga_read_addr: equ 0x14 ; R/W
vga_read_addr0: equ 0x14 ; R/W
vga_read_addr1: equ 0x15 ; R/W
vga_read_addr2: equ 0x16 ; R/W
timer_reload: equ 0x17 ; R/W
timer_reload0: equ 0x17 ; R/W
timer_reload1: equ 0x18 ; R/W
timer_reload2: equ 0x19 ; R/W
lib/CPUs/JCpu/ghdl/.gitignore.templ
-4
View File
@@ -1,4 +0,0 @@
.gitignore
build/
.gitignore
build/
lib/CPUs/JCpu/ghdl/cpu_itest.gtkw
-26
View File
@@ -1,26 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Sun Mar 21 20:23:20 2021
[*]
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_itest/cpu_itest.ghw"
[dumpfile_mtime] "Sun Mar 21 20:23:14 2021"
[dumpfile_size] 23880
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/cpu_itest/cpu_itest.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
*-28.353857 33340 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_cpu.
[treeopen] top.tb_cpu.uut.
[treeopen] top.tb_cpu.uut.inst_pc.
[sst_width] 233
[signals_width] 134
[sst_expanded] 1
[sst_vpaned_height] 144
@22
#{top.tb_cpu.xmem_din[7:0]} top.tb_cpu.xmem_din[7] top.tb_cpu.xmem_din[6] top.tb_cpu.xmem_din[5] top.tb_cpu.xmem_din[4] top.tb_cpu.xmem_din[3] top.tb_cpu.xmem_din[2] top.tb_cpu.xmem_din[1] top.tb_cpu.xmem_din[0]
@23
#{top.tb_cpu.uut.inst_pc.pc_next[11:0]} top.tb_cpu.uut.inst_pc.pc_next[11] top.tb_cpu.uut.inst_pc.pc_next[10] top.tb_cpu.uut.inst_pc.pc_next[9] top.tb_cpu.uut.inst_pc.pc_next[8] top.tb_cpu.uut.inst_pc.pc_next[7] top.tb_cpu.uut.inst_pc.pc_next[6] top.tb_cpu.uut.inst_pc.pc_next[5] top.tb_cpu.uut.inst_pc.pc_next[4] top.tb_cpu.uut.inst_pc.pc_next[3] top.tb_cpu.uut.inst_pc.pc_next[2] top.tb_cpu.uut.inst_pc.pc_next[1] top.tb_cpu.uut.inst_pc.pc_next[0]
[pattern_trace] 1
[pattern_trace] 0
lib/CPUs/JCpu/ghdl/cpu_itest.make
-18
View File
@@ -1,18 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/defs.mk
# -----------------------------------------------------------
include jcpu_core.inc
SRCS += $(JCPU_CORE_SRCS)
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
SRCS += ../src/itest_irom.vhdl
SRCS += ../src/tb_cpu_itest.vhd
# Compile
TARGET := cpu_itest
ENTITY := tb_cpu
WAVE_FORMAT := ghw
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/jcpu_core.inc
-20
View File
@@ -1,20 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := JCPU_CORE
# -----------------------------------------------------------
MOD_PATH := $(LIB_PATH)/CPUs/JCpu/src/core
$(PKG_NAME)_SRCS += $(MOD_PATH)/cpu_pkg.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/cpu.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/alu.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/chipram.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/chipreg.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/dpath_ctrl.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/int_ctrl.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/pc.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/reg_dual.vhd
$(PKG_NAME)_SRCS += $(MOD_PATH)/stack_ctrl.vhd
# -----------------------------------------------------------
lib/CPUs/JCpu/ghdl/mul8x8.gtkw
-32
View File
@@ -1,32 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Mon Mar 22 20:01:47 2021
[*]
[dumpfile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/mul8x8/mul8x8.ghw"
[dumpfile_mtime] "Mon Mar 22 20:00:48 2021"
[dumpfile_size] 25852
[savefile] "/home/jens/work/vhdl/trunk/lib/CPUs/JCpu/ghdl/build/mul8x8/mul8x8.gtkw"
[timestart] 0
[size] 1173 600
[pos] -1 -1
*-28.009827 724000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_cpu_embedded.
[treeopen] top.tb_cpu_embedded.uut.
[sst_width] 233
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 144
@28
top.tb_cpu_embedded.rst
top.tb_cpu_embedded.clk
@22
#{top.tb_cpu_embedded.uut.irom_addr[11:0]} top.tb_cpu_embedded.uut.irom_addr[11] top.tb_cpu_embedded.uut.irom_addr[10] top.tb_cpu_embedded.uut.irom_addr[9] top.tb_cpu_embedded.uut.irom_addr[8] top.tb_cpu_embedded.uut.irom_addr[7] top.tb_cpu_embedded.uut.irom_addr[6] top.tb_cpu_embedded.uut.irom_addr[5] top.tb_cpu_embedded.uut.irom_addr[4] top.tb_cpu_embedded.uut.irom_addr[3] top.tb_cpu_embedded.uut.irom_addr[2] top.tb_cpu_embedded.uut.irom_addr[1] top.tb_cpu_embedded.uut.irom_addr[0]
@23
#{top.tb_cpu_embedded.uut.irom_data[17:0]} top.tb_cpu_embedded.uut.irom_data[17] top.tb_cpu_embedded.uut.irom_data[16] top.tb_cpu_embedded.uut.irom_data[15] top.tb_cpu_embedded.uut.irom_data[14] top.tb_cpu_embedded.uut.irom_data[13] top.tb_cpu_embedded.uut.irom_data[12] top.tb_cpu_embedded.uut.irom_data[11] top.tb_cpu_embedded.uut.irom_data[10] top.tb_cpu_embedded.uut.irom_data[9] top.tb_cpu_embedded.uut.irom_data[8] top.tb_cpu_embedded.uut.irom_data[7] top.tb_cpu_embedded.uut.irom_data[6] top.tb_cpu_embedded.uut.irom_data[5] top.tb_cpu_embedded.uut.irom_data[4] top.tb_cpu_embedded.uut.irom_data[3] top.tb_cpu_embedded.uut.irom_data[2] top.tb_cpu_embedded.uut.irom_data[1] top.tb_cpu_embedded.uut.irom_data[0]
@22
#{top.tb_cpu_embedded.xmem_addr[7:0]} top.tb_cpu_embedded.xmem_addr[7] top.tb_cpu_embedded.xmem_addr[6] top.tb_cpu_embedded.xmem_addr[5] top.tb_cpu_embedded.xmem_addr[4] top.tb_cpu_embedded.xmem_addr[3] top.tb_cpu_embedded.xmem_addr[2] top.tb_cpu_embedded.xmem_addr[1] top.tb_cpu_embedded.xmem_addr[0]
#{top.tb_cpu_embedded.xmem_dout[7:0]} top.tb_cpu_embedded.xmem_dout[7] top.tb_cpu_embedded.xmem_dout[6] top.tb_cpu_embedded.xmem_dout[5] top.tb_cpu_embedded.xmem_dout[4] top.tb_cpu_embedded.xmem_dout[3] top.tb_cpu_embedded.xmem_dout[2] top.tb_cpu_embedded.xmem_dout[1] top.tb_cpu_embedded.xmem_dout[0]
#{top.tb_cpu_embedded.xmem_din[7:0]} top.tb_cpu_embedded.xmem_din[7] top.tb_cpu_embedded.xmem_din[6] top.tb_cpu_embedded.xmem_din[5] top.tb_cpu_embedded.xmem_din[4] top.tb_cpu_embedded.xmem_din[3] top.tb_cpu_embedded.xmem_din[2] top.tb_cpu_embedded.xmem_din[1] top.tb_cpu_embedded.xmem_din[0]
[pattern_trace] 1
[pattern_trace] 0
lib/CPUs/JCpu/ghdl/mul8x8.make
-17
View File
@@ -1,17 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/defs.mk
# -----------------------------------------------------------
include jcpu_core.inc
SRCS += $(JCPU_CORE_SRCS)
SRCS += ../src/mul8x8_irom.vhdl
SRCS += ../src/cpu_embedded.vhd
SRCS += ../src/tb_cpu_embedded.vhd
# Compile
TARGET := mul8x8
ENTITY := tb_cpu_embedded
WAVE_FORMAT := ghw
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/reti_issue.gtkw
-33
View File
@@ -1,33 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Sat Jul 2 11:00:05 2022
[*]
[dumpfile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/build/reti_issue/reti_issue.ghw"
[dumpfile_mtime] "Sat Jul 2 10:56:29 2022"
[dumpfile_size] 22085
[savefile] "/home/jens/work/projects/vhdl/lib/CPUs/JCpu/ghdl/reti_issue.gtkw"
[timestart] 0
[size] 1854 1136
[pos] -51 -51
*-28.221537 446000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_cpu.
[sst_width] 233
[signals_width] 266
[sst_expanded] 1
[sst_vpaned_height] 330
@28
top.tb_cpu.uut.clk
top.tb_cpu.uut.rst
top.tb_cpu.uut.cio_sel
top.tb_cpu.uut.stk_pop
top.tb_cpu.uut.stk_push
top.tb_cpu.uut.was_pop2pc
top.tb_cpu.uut.was_pcld
@420
top.tb_cpu.uut.ctrl_iphase
@22
#{top.tb_cpu.irom_addr[11:0]} top.tb_cpu.irom_addr[11] top.tb_cpu.irom_addr[10] top.tb_cpu.irom_addr[9] top.tb_cpu.irom_addr[8] top.tb_cpu.irom_addr[7] top.tb_cpu.irom_addr[6] top.tb_cpu.irom_addr[5] top.tb_cpu.irom_addr[4] top.tb_cpu.irom_addr[3] top.tb_cpu.irom_addr[2] top.tb_cpu.irom_addr[1] top.tb_cpu.irom_addr[0]
#{top.tb_cpu.irom_data[17:0]} top.tb_cpu.irom_data[17] top.tb_cpu.irom_data[16] top.tb_cpu.irom_data[15] top.tb_cpu.irom_data[14] top.tb_cpu.irom_data[13] top.tb_cpu.irom_data[12] top.tb_cpu.irom_data[11] top.tb_cpu.irom_data[10] top.tb_cpu.irom_data[9] top.tb_cpu.irom_data[8] top.tb_cpu.irom_data[7] top.tb_cpu.irom_data[6] top.tb_cpu.irom_data[5] top.tb_cpu.irom_data[4] top.tb_cpu.irom_data[3] top.tb_cpu.irom_data[2] top.tb_cpu.irom_data[1] top.tb_cpu.irom_data[0]
[pattern_trace] 1
[pattern_trace] 0
lib/CPUs/JCpu/ghdl/reti_issue.make
-18
View File
@@ -1,18 +0,0 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/defs.mk
# -----------------------------------------------------------
include jcpu_core.inc
SRCS += $(JCPU_CORE_SRCS)
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
SRCS += ../src/reti_issue_irom.vhdl
SRCS += ../src/tb_cpu_itest.vhd
# Compile
TARGET := reti_issue
ENTITY := tb_cpu
WAVE_FORMAT := ghw
include $(VHDL_MAKE_HOME)/ghdl.mk

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