jens
538c115367
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@376 cc03376c-175c-47c8-b038-4cd826a8556b
37 lines
1.2 KiB
Plaintext
37 lines
1.2 KiB
Plaintext
-----------------------------------------------------------------
|
|
Changes in release 11
|
|
-----------------------------------------------------------------
|
|
- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset
|
|
(fixes CPU unrecoverable state after reset)
|
|
- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
|
|
- new example source: test_exception
|
|
- minor changes in libsys
|
|
- added async_port_timing in doc
|
|
- examples/testbench: date set now really works
|
|
|
|
-----------------------------------------------------------------
|
|
Changes in release 10b
|
|
-----------------------------------------------------------------
|
|
- fixed compiler bug (missing nop after lw) in bootloader,
|
|
which caused exception during boot
|
|
|
|
-----------------------------------------------------------------
|
|
Changes in release 10a
|
|
-----------------------------------------------------------------
|
|
async_port_wb:
|
|
- added byte enable for async_port
|
|
|
|
bootloader.c
|
|
- fixed compiler bug (missing nop after lw)
|
|
|
|
mips-core
|
|
- SEL_O lines are also asserted correctly during reads
|
|
|
|
tools/romgen
|
|
- TCL-Jtage now compatible with Chipscope 10.1
|
|
|
|
mips_sys.c
|
|
- use byte enable for sram and flash
|
|
|
|
|