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- fixed path to altera dp ram

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jens
2022-08-07 12:31:32 +02:00
parent d54a810a4a
commit fb4ca98ad3
1 changed files with 2 additions and 2 deletions
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projects/mips_de0_nano/quartus/mips/JMips.qsf
+2 -2
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@@ -286,8 +286,8 @@ set_global_assignment -name VHDL_FILE ../../../../lib/misc/gpio_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/rom_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/ram_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_1w1r2c_ra_alt.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_2w2r2c_ra_alt.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_1w1r2c_ra.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_2w2r2c_ra.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd