From fb4ca98ad300b6c4786cc4848c4f36d4e884ec5c Mon Sep 17 00:00:00 2001 From: jens Date: Sun, 7 Aug 2022 12:31:32 +0200 Subject: [PATCH] - fixed path to altera dp ram --- projects/mips_de0_nano/quartus/mips/JMips.qsf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/mips_de0_nano/quartus/mips/JMips.qsf b/projects/mips_de0_nano/quartus/mips/JMips.qsf index cd17cd5..9a4b901 100644 --- a/projects/mips_de0_nano/quartus/mips/JMips.qsf +++ b/projects/mips_de0_nano/quartus/mips/JMips.qsf @@ -286,8 +286,8 @@ set_global_assignment -name VHDL_FILE ../../../../lib/misc/gpio_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/rom_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/ram_wb.vhd -set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_1w1r2c_ra_alt.vhd -set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_2w2r2c_ra_alt.vhd +set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_1w1r2c_ra.vhd +set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_2w2r2c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd