jens b1dfffbc2a renamed clock entity ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1170 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-23 08:42:51 +00:00

..

ddr_clk_virtex4.vhd

renamed clock entity

2015-05-23 08:42:51 +00:00

ddr_phy_virtex4.vhd

renamed clock entity

2015-05-23 08:42:51 +00:00

mt46v16m16.vhd

Intital revision

2008-10-02 13:37:55 +00:00

mt48lc16m4.vhd

- added SDRAM model

2015-05-22 06:16:03 +00:00

sdram_cmd.vhd

Minor changes to max cycle count

2010-02-09 09:56:44 +00:00

sdram_config.vhd

- made time specs in nano seconds

2010-02-07 15:53:23 +00:00

sdram_ctrl_frontend64_wb.vhd

- reverted: SRDY dependent on SDRAM_RST0

2015-05-23 08:05:31 +00:00

sdram_ctrl_frontend_wb.vhd

- reverted: SRDY dependent on SDRAM_RST0

2015-05-23 08:05:31 +00:00

sdram_ctrl_top.vhd

- added reset out

2015-05-22 19:35:46 +00:00

sdram_ctrl.vhd

- changed frequencies into MHz units (real data type)

2010-02-09 07:50:27 +00:00

sdram_types.vhd

- to_cycles() now correctly rounded

2010-02-09 08:42:21 +00:00

tb_sdram_ctrl_frontend64_wb.vhd

[SDRAM-Controller]

2015-05-22 17:49:58 +00:00

tb_sdram_ctrl_frontend_wb.vhd

[SDRAM-Controller]

2015-05-22 17:49:58 +00:00