jens 11fa96a4e7 [Uart] ...

- uart_wb instantiates uart
- merged uart_tx, uart_rx into uart
- added uart implementations for Xilinx (kcuart) and Altera (JTAG)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1239 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-27 15:50:32 +00:00

Common

- fixed compile scripts

2015-05-23 16:04:34 +00:00

lib

[Uart]

2015-05-27 15:50:32 +00:00

projects/mips_sys

- fixed project files

2015-05-25 11:48:26 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%