jens
0afb7b1758
git-svn-id: http://moon:8086/svn/vhdl/trunk@1097 cc03376c-175c-47c8-b038-4cd826a8556b
243 lines
7.1 KiB
VHDL
243 lines
7.1 KiB
VHDL
-----------------------------------------------------------------------------
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-- --
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-- Copyright (c) 1996 by Altera Corp. All rights reserved. --
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-- --
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-- --
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-- Description: Package file for Altera mega functions. --
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-- --
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-- --
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package megacore is
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component a16450
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port (
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mr : IN std_logic;
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clk : IN std_logic;
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a : IN std_logic_vector(2 downto 0);
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din : IN std_logic_vector(7 downto 0);
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cs0 : IN std_logic;
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cs1 : IN std_logic;
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ncs2 : IN std_logic;
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nads : IN std_logic;
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rd : IN std_logic;
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nrd : IN std_logic;
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wr : IN std_logic;
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nwr : IN std_logic;
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sin : IN std_logic;
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rclk : IN std_logic;
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ncts : IN std_logic;
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ndsr : IN std_logic;
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ndcd : IN std_logic;
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nri : IN std_logic;
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dout : OUT std_logic_vector(7 downto 0);
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ddis : OUT std_logic;
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csout : OUT std_logic;
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sout : OUT std_logic;
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nbaudout : OUT std_logic;
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nrts : OUT std_logic;
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ndtr : OUT std_logic;
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nout1 : OUT std_logic;
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nout2 : OUT std_logic;
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intr : OUT std_logic
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);
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end component;
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component a6402
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port (
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cls1 : IN std_logic;
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cls2 : IN std_logic;
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crl : IN std_logic;
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ndrr : IN std_logic;
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epe : IN std_logic;
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mr : IN std_logic;
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pi : IN std_logic;
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rrc : IN std_logic;
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rri : IN std_logic;
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sbs : IN std_logic;
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tbr : IN std_logic_vector(7 downto 0);
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ntbrl : IN std_logic;
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trc : IN std_logic;
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dr : OUT std_logic;
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fe : OUT std_logic;
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oe : OUT std_logic;
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pe : OUT std_logic;
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rbr : OUT std_logic_vector(7 downto 0);
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tbre : OUT std_logic;
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tro : OUT std_logic;
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tre : OUT std_logic
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);
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end component;
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component a6850
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port (
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nreset : IN std_logic;
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di : IN std_logic_vector(7 downto 0);
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e : IN std_logic;
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rnw : IN std_logic;
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cs : IN std_logic_vector(2 downto 0);
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rs : IN std_logic;
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txclk : IN std_logic;
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rxclk : IN std_logic;
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rxdata : IN std_logic;
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ncts : IN std_logic;
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ndcd : IN std_logic;
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do : OUT std_logic_vector(7 downto 0);
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nirq : OUT std_logic;
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txdata : OUT std_logic;
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nrts : OUT std_logic
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);
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end component;
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component a8237
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port (
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reset : IN std_logic;
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clk : IN std_logic;
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ncs : IN std_logic;
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niorin : IN std_logic;
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niowin : IN std_logic;
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ready : IN std_logic;
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hlda : IN std_logic;
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neopin : IN std_logic;
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ain : IN std_logic_vector(3 downto 0);
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dreq : IN std_logic_vector(3 downto 0);
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dbin : IN std_logic_vector(7 downto 0);
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dbout : OUT std_logic_vector(7 downto 0);
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dben : OUT std_logic;
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aout : OUT std_logic_vector(7 downto 0);
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hrq : OUT std_logic;
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dack : OUT std_logic_vector(3 downto 0);
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aen : OUT std_logic;
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adstb : OUT std_logic;
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niorout : OUT std_logic;
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niowout : OUT std_logic;
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nmemr : OUT std_logic;
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nmemw : OUT std_logic;
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neopout : OUT std_logic;
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dmaenable : OUT std_logic
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);
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end component;
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component a8251
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port (
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clk : IN std_logic;
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nreset : IN std_logic;
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nwr : IN std_logic;
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nrd : IN std_logic;
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ncs : IN std_logic;
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cnd : IN std_logic;
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ndsr : IN std_logic;
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ncts : IN std_logic;
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extsyncd : IN std_logic;
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ntxc : IN std_logic;
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nrxc : IN std_logic;
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rxd : IN std_logic;
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din : IN std_logic_vector(7 downto 0);
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txd : OUT std_logic;
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txrdy : OUT std_logic;
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txempty : OUT std_logic;
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rxrdy : OUT std_logic;
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ndtr : OUT std_logic;
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nrts : OUT std_logic;
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syn_brk : OUT std_logic;
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nen : OUT std_logic;
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dout : OUT std_logic_vector(7 downto 0)
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);
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end component;
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component a8255
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port (
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reset : IN std_logic;
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clk : IN std_logic;
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ncs : IN std_logic;
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nrd : IN std_logic;
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nwr : IN std_logic;
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a : IN std_logic_vector(1 downto 0);
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din : IN std_logic_vector(7 downto 0);
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pain : IN std_logic_vector(7 downto 0);
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pbin : IN std_logic_vector(7 downto 0);
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pcin : IN std_logic_vector(7 downto 0);
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dout : OUT std_logic_vector(7 downto 0);
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paout : OUT std_logic_vector(7 downto 0);
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paen : OUT std_logic;
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pbout : OUT std_logic_vector(7 downto 0);
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pben : OUT std_logic;
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pcout : OUT std_logic_vector(7 downto 0);
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pcen : OUT std_logic_vector(7 downto 0)
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);
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end component;
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component rgb2ycrcb
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port (
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R : IN std_logic_vector(7 downto 0);
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G : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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CLOCK : IN std_logic := '0';
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ACLR : IN std_logic := '0';
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Y : OUT std_logic_vector(15 downto 0);
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Cr: OUT std_logic_vector(14 downto 0);
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Cb: OUT std_logic_vector(14 downto 0)
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);
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end component;
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component ycrcb2rgb
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port (
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Y : IN std_logic_vector(7 downto 0);
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CR : IN std_logic_vector(7 downto 0);
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CB : IN std_logic_vector(7 downto 0);
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CLOCK : IN std_logic := '0';
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ACLR : IN std_logic := '0';
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R : OUT std_logic_vector(16 downto 0);
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G: OUT std_logic_vector(16 downto 0);
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B: OUT std_logic_vector(16 downto 0)
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);
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end component;
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component a8259
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port (
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nmrst, clk, ncs, nwr, nrd, a0, nsp, ninta : IN std_logic;
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casin : IN std_logic_vector(2 downto 0);
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din, ir : IN std_logic_vector(7 downto 0);
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nen, cas_en, int : OUT std_logic;
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dout : OUT std_logic_vector(7 downto 0);
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casout : OUT std_logic_vector(7 downto 0)
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);
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end component;
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component fft
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generic (
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WIDTH_DATA : POSITIVE;
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WIDTH_TWIDDLE : POSITIVE;
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PIPE_DATA : INTEGER;
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PIPE_TWIDDLE : INTEGER;
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WIDTH_EXPONENT : POSITIVE;
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WIDTH_ADD : POSITIVE;
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EXPONENT_INITIAL_VALUE : INTEGER
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);
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port (
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clock : IN std_logic := '0';
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start_fft : IN std_logic;
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data_left_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
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data_left_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
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data_right_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
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data_right_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
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twiddle_re : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
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twiddle_im : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
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done : OUT std_logic;
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data_direction : OUT std_logic;
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we_left : OUT std_logic;
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add_left : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
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we_right : OUT std_logic;
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add_right : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
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add_twiddle : OUT std_logic_vector(WIDTH_ADD-2 downto 0);
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data_out_re : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
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data_out_im : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
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exponent : OUT std_logic_vector(WIDTH_EXPONENT-1 downto 0)
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);
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end component;
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end megacore;
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