Compare commits
25
Commits
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@@ -0,0 +1,48 @@
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## NOTE: Do not edit this file.
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||||
##
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vlib work
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||||
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# Packages
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vcom -explicit -93 "../src/core/mips_util_pkg.vhd"
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../../../misc/utils_pkg.vhd"
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||||
vcom -explicit -93 "../../../JBUS/src/busmaster_types.vhd"
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||||
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||||
# RAMS
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||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
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||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
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||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
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||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
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vcom -explicit -93 "../../../misc/ram_sim.vhd"
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||||
vcom -explicit -93 "../../../misc/ram_wb.vhd"
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||||
vcom -explicit -93 "../../../misc/rom_sim.vhd"
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||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
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||||
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||||
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||||
# FIFOS
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||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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||||
vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
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||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
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# MIPS Cache
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vcom -explicit -93 "../src/core/mips_icache.vhd"
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vcom -explicit -93 "../src/core/mips_dcache.vhd"
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# MIPS TLB
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vcom -explicit -93 "../src/core/mips_cam.vhd"
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vcom -explicit -93 "../src/core/mips_tlb.vhd"
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# Busmaster
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vcom -explicit -93 "../../../JBUS/src/busmaster_async.vhd"
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vcom -explicit -93 "../src/core/mips_biu.vhd"
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vcom -explicit -93 "../src/tb_mips_biu.vhd"
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vsim -t 1ps -lib work tb_biu
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do {tb_mips_biu.wdo}
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view wave
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view structure
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view signals
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run 10us
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@@ -0,0 +1,160 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_biu/clk
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add wave -noupdate -format Logic /tb_biu/rst
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add wave -noupdate -format Logic /tb_biu/int_o
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add wave -noupdate -format Logic /tb_biu/cyc_o
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add wave -noupdate -format Logic /tb_biu/stb_o
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add wave -noupdate -format Logic /tb_biu/we_o
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add wave -noupdate -format Literal /tb_biu/sel_o
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add wave -noupdate -format Logic /tb_biu/ack_i
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add wave -noupdate -format Logic /tb_biu/mrdy_o
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add wave -noupdate -format Logic /tb_biu/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/mdat_i
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/mdat_o
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||||
add wave -noupdate -format Literal /tb_biu/index_in
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||||
add wave -noupdate -format Logic /tb_biu/entry_we
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/entry_lo_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/entry_hi_in
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add wave -noupdate -format Literal /tb_biu/index_out
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add wave -noupdate -format Logic /tb_biu/entry_re
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/entry_lo_out
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/entry_hi_out
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||||
add wave -noupdate -format Logic /tb_biu/cpu_imem_err
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||||
add wave -noupdate -format Logic /tb_biu/cpu_imem_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_imem_addr
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_imem_dout
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add wave -noupdate -format Logic /tb_biu/cpu_imem_rdy
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add wave -noupdate -format Logic /tb_biu/cpu_dmem_err
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add wave -noupdate -format Logic /tb_biu/cpu_dmem_en
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add wave -noupdate -format Logic /tb_biu/cpu_dmem_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_dmem_addr
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||||
add wave -noupdate -format Literal /tb_biu/cpu_dmem_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_dmem_din
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_dmem_dout
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add wave -noupdate -format Logic /tb_biu/cpu_dmem_rdy
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/ctrl_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_biu/ctrl_out
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add wave -noupdate -divider BIU
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add wave -noupdate -format Logic /tb_biu/inst_biu/clk_i
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add wave -noupdate -format Logic /tb_biu/cpu_imem_din_vld
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_imem_din_reg
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||||
add wave -noupdate -format Logic /tb_biu/cpu_dmem_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/cpu_dmem_din_reg
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||||
add wave -noupdate -format Literal /tb_biu/op_descr
|
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add wave -noupdate -format Logic /tb_biu/inst_biu/imem_err
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/imem_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/imem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/imem_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/imem_dout
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/dmem_err
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/dmem_en
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/dmem_we
|
||||
add wave -noupdate -format Literal /tb_biu/inst_biu/dmem_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/dmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/dmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/dmem_addr
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/rst_i
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/clk_i
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/srdy_i
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/stb_o
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/addr_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/mdat_i
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/ack_i
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/mdat_o
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/we_o
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||||
add wave -noupdate -format Literal /tb_biu/inst_biu/sel_o
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/cyc_o
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/mrdy_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/ctrl_out
|
||||
add wave -noupdate -format Literal /tb_biu/inst_biu/s
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||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_idle
|
||||
add wave -noupdate -format Literal /tb_biu/inst_biu/bus_timeout_cnt
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_timeout
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/rst
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/bus_din
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/bus_dout
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_dout_vld
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_dout_re
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/bus_cmd
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/bus_cyc_complete
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/i_bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/i_bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/i_bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/i_bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/i_bus_cmd
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/d_bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/d_bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/d_bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/d_bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/d_bus_cmd
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/icache_bus_gnt
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/dcache_bus_gnt
|
||||
add wave -noupdate -divider BUS-Master
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/clk
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/rst
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/cmd_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/din
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/din_rdy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/dout
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/dout_vld
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/dout_re
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/ack_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/mdat_o
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/srdy_i
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/stb_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/addr_o
|
||||
add wave -noupdate -format Literal /tb_biu/inst_biu/inst_busmaster/sel_o
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/we_o
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cyc_o
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/mrdy_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_biu/inst_biu/inst_busmaster/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/read_fifo_re
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/read_fifo_we
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/read_fifo_full
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_en
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_biu/inst_biu/inst_busmaster/read_cnt
|
||||
add wave -noupdate -format Logic /tb_biu/inst_biu/inst_busmaster/write
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3126068 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {10500 ns}
|
||||
@@ -0,0 +1,24 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
|
||||
|
||||
|
||||
# FIFOS
|
||||
|
||||
# MIPS
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_cam.vhd"
|
||||
|
||||
vcom -explicit -93 "../src/tb_mips_cam.vhd"
|
||||
vsim -t 1ps -lib work tb_cam
|
||||
do {tb_mips_cam.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 80us
|
||||
@@ -0,0 +1,69 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cam/clk_o
|
||||
add wave -noupdate -format Logic /tb_cam/rst_o
|
||||
add wave -noupdate -format Logic /tb_cam/cam_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_addr
|
||||
add wave -noupdate -format Logic /tb_cam/cam_vld
|
||||
add wave -noupdate -format Logic /tb_cam/cam_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_wtag
|
||||
add wave -noupdate -format Logic /tb_cam/cam_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_rtag
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_hit
|
||||
add wave -noupdate -format Logic /tb_cam/cam_hit_vld
|
||||
add wave -noupdate -divider CAM
|
||||
add wave -noupdate -format Literal /tb_cam/inst_cam/state
|
||||
add wave -noupdate -format Literal /tb_cam/inst_cam/debug
|
||||
add wave -noupdate -format Literal /tb_cam/inst_cam/num_entries
|
||||
add wave -noupdate -format Literal /tb_cam/inst_cam/data_width
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/rst
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/clk
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/rdy
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/re
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/we
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/hit
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/cam_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_result
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_addr
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/clear_count_en
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/clear_count_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/vld_cam
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe3
|
||||
add wave -noupdate -divider Track-RAM
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/over_write
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/track_ram_re
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/track_ram_we
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/rdy
|
||||
add wave -noupdate -format Logic /tb_cam/inst_cam/we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cam/inst_cam/inst_track_ram/ram
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {Cursor {34938145 ps} 0}
|
||||
configure wave -namecolwidth 137
|
||||
configure wave -valuecolwidth 214
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {84 us}
|
||||
@@ -0,0 +1,45 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
|
||||
vcom -explicit -93 "../src/core/mips_util_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_types.vhd"
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/ram_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/ram_wb.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
|
||||
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
|
||||
|
||||
# MIPS Cache
|
||||
vcom -explicit -93 "../src/core/mips_dcache.vhd"
|
||||
|
||||
# MIPS TLB
|
||||
vcom -explicit -93 "../src/core/mips_cam.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_tlb.vhd"
|
||||
|
||||
# Busmaster
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_sync.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_dcache.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_dcache
|
||||
do {tb_mips_dcache.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -0,0 +1,263 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_dcache/clk
|
||||
add wave -noupdate -format Logic /tb_dcache/rst
|
||||
add wave -noupdate -format Logic /tb_dcache/int_o
|
||||
add wave -noupdate -format Logic /tb_dcache/cyc_o
|
||||
add wave -noupdate -format Logic /tb_dcache/stb_o
|
||||
add wave -noupdate -format Logic /tb_dcache/we_o
|
||||
add wave -noupdate -format Literal /tb_dcache/sel_o
|
||||
add wave -noupdate -format Logic /tb_dcache/ack_i
|
||||
add wave -noupdate -format Logic /tb_dcache/mrdy_o
|
||||
add wave -noupdate -format Logic /tb_dcache/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/addr_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/mdat_o
|
||||
add wave -noupdate -format Logic /tb_dcache/ce
|
||||
add wave -noupdate -format Literal /tb_dcache/index_in
|
||||
add wave -noupdate -format Logic /tb_dcache/entry_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_lo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_hi_in
|
||||
add wave -noupdate -format Literal /tb_dcache/index_out
|
||||
add wave -noupdate -format Logic /tb_dcache/entry_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_lo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_hi_out
|
||||
add wave -noupdate -format Literal /tb_dcache/tlb_index_hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/tlb_pa
|
||||
add wave -noupdate -format Literal -expand /tb_dcache/tlb_flags
|
||||
add wave -noupdate -format Logic /tb_dcache/tlb_hit
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_addr
|
||||
add wave -noupdate -format Literal /tb_dcache/cpu_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/dcache_ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_din
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_dout_vld
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_dout_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_cmd
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cyc_complete
|
||||
add wave -noupdate -divider TLB
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/rst
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/clk
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/ce
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/index_in
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/entry_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/entry_lo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/entry_hi_in
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/index_out
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/entry_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/entry_lo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/entry_hi_out
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/tlb_blk_entry_we
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/tlb_blk_hit
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/tlb_blk_flags
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/tlb_blk_pfn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/tlb_blk_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/tlb_blk_entry_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_tlb/pa
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_tlb/hit
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_tlb/flags
|
||||
add wave -noupdate -divider D-Cache
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/rst
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dcache/inst_dcache/debug
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/cache_busy_state
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/cache_ctrl_state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_din_reg
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/request_va
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/request_pa
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_req_rd
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_req_wr
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/single_read_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/single_read_set
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/single_read_reg_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/din
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/we
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/addr
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/tlb_exc
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/tlb_exc_type
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/read_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/dout
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_hit
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_req_rd
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_req_wr
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/we_reg
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/tag_match
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dcache/inst_dcache/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/bus_din
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_din_vld
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/bus_cmd_out
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/bus_cyc_complete
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/cache_hit_inv
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/cache_entry_out_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/data_ram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/data_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/data_reg
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/be_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/ctrl_data_ram_addr
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/ctrl_data_ram_we
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_ram_dout_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/tag_ram_din
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/tag_ram_we
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/fill_count
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/flush_count
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_dcache/request_count
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/was_miss
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/invalidate_req
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/hit_cache_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/req_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/fill_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/inst_tag_ram/ram
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/write_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_dcache/write_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_data_avail
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/read_write_buffer
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_dcache/write_through_en
|
||||
add wave -noupdate -divider Bus-Master
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/clk
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/rst
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/cmd_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/din
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/din_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/dout
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/dout_vld
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/dout_re
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/ack_i
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/addr_o
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_busmaster_sync/sel_o
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/we_o
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cyc_o
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/stb_o
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/mrdy_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/inst_busmaster_sync/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/read_fifo_re
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/read_fifo_we
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/read_fifo_full
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_en
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_dcache/inst_busmaster_sync/read_cnt
|
||||
add wave -noupdate -format Logic /tb_dcache/inst_busmaster_sync/write
|
||||
add wave -noupdate -format Logic /tb_dcache/clk
|
||||
add wave -noupdate -format Logic /tb_dcache/rst
|
||||
add wave -noupdate -format Logic /tb_dcache/int_o
|
||||
add wave -noupdate -format Logic /tb_dcache/cyc_o
|
||||
add wave -noupdate -format Logic /tb_dcache/stb_o
|
||||
add wave -noupdate -format Logic /tb_dcache/we_o
|
||||
add wave -noupdate -format Literal /tb_dcache/sel_o
|
||||
add wave -noupdate -format Logic /tb_dcache/ack_i
|
||||
add wave -noupdate -format Logic /tb_dcache/mrdy_o
|
||||
add wave -noupdate -format Logic /tb_dcache/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/addr_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/mdat_o
|
||||
add wave -noupdate -format Logic /tb_dcache/ce
|
||||
add wave -noupdate -format Literal /tb_dcache/index_in
|
||||
add wave -noupdate -format Logic /tb_dcache/entry_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_lo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_hi_in
|
||||
add wave -noupdate -format Literal /tb_dcache/index_out
|
||||
add wave -noupdate -format Logic /tb_dcache/entry_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_lo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/entry_hi_out
|
||||
add wave -noupdate -format Literal /tb_dcache/tlb_index_hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/tlb_pa
|
||||
add wave -noupdate -format Literal -expand /tb_dcache/tlb_flags
|
||||
add wave -noupdate -format Logic /tb_dcache/tlb_hit
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_addr
|
||||
add wave -noupdate -format Literal /tb_dcache/cpu_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/cpu_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/dcache_ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_din
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_dout
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_dout_vld
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_dout_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dcache/bus_cmd
|
||||
add wave -noupdate -format Logic /tb_dcache/bus_cyc_complete
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {743514 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {3533088 ps}
|
||||
@@ -0,0 +1,45 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
|
||||
vcom -explicit -93 "../src/core/mips_util_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_types.vhd"
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/ram_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/ram_wb.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_sim.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
|
||||
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
|
||||
|
||||
# MIPS Cache
|
||||
vcom -explicit -93 "../src/core/mips_icache.vhd"
|
||||
|
||||
# MIPS TLB
|
||||
vcom -explicit -93 "../src/core/mips_cam.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_tlb.vhd"
|
||||
|
||||
# Busmaster
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_sync.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_icache.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_icache
|
||||
do {tb_mips_icache.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -0,0 +1,162 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_icache/clk
|
||||
add wave -noupdate -format Logic /tb_icache/rst
|
||||
add wave -noupdate -format Logic /tb_icache/int_o
|
||||
add wave -noupdate -format Logic /tb_icache/cyc_o
|
||||
add wave -noupdate -format Logic /tb_icache/stb_o
|
||||
add wave -noupdate -format Logic /tb_icache/we_o
|
||||
add wave -noupdate -format Literal /tb_icache/sel_o
|
||||
add wave -noupdate -format Logic /tb_icache/ack_i
|
||||
add wave -noupdate -format Logic /tb_icache/mrdy_o
|
||||
add wave -noupdate -format Logic /tb_icache/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/addr_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/mdat_o
|
||||
add wave -noupdate -divider TLB
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/rst
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/clk
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/ce
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/index_in
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/entry_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/entry_lo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/entry_hi_in
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/index_out
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/entry_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/entry_lo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/entry_hi_out
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/tlb_blk_entry_we
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/tlb_blk_hit
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/tlb_blk_flags
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/tlb_blk_pfn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/tlb_blk_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/tlb_blk_entry_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_tlb/pa
|
||||
add wave -noupdate -format Logic /tb_icache/inst_tlb/hit
|
||||
add wave -noupdate -format Literal /tb_icache/inst_tlb/flags
|
||||
add wave -noupdate -divider I-Cache
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/rst
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/cpu_din_reg
|
||||
add wave -noupdate -format Logic /tb_icache/cpu_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/request_va
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/request_pa
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/cache_req_rd
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/read_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/dout
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/cache_busy_state
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/cache_ctrl_state
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/single_read_reg_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/single_read_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/tag_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/bus_din
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_din_vld
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/bus_cmd_out
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/bus_cyc_complete
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/cache_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/tag_match
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/cache_entry_out_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/data_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/data_ram_data_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/data_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/data_ram_data_wr
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_ram_data_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_ram_data_rd_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/tag_ram_data_wr
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/fill_count
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/flush_count
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/request_count
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/ram_read_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/was_miss
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/invalidate_req
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/req_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_icache/fill_word_index
|
||||
add wave -noupdate -format Logic /tb_icache/inst_icache/tlb_exc
|
||||
add wave -noupdate -format Literal /tb_icache/inst_icache/tlb_exc_type
|
||||
add wave -noupdate -divider Busmaster
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/clk
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/rst
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/cmd_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/din
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/din_rdy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/dout
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/dout_vld
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/dout_re
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/ack_i
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/addr_o
|
||||
add wave -noupdate -format Literal /tb_icache/inst_busmaster_sync/sel_o
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/we_o
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cyc_o
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/stb_o
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/mrdy_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_icache/inst_busmaster_sync/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/read_fifo_re
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/read_fifo_we
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/read_fifo_full
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_en
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_icache/inst_busmaster_sync/read_cnt
|
||||
add wave -noupdate -format Logic /tb_icache/inst_busmaster_sync/write
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1549212 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {1322906 ps} {1804473 ps}
|
||||
@@ -0,0 +1,27 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r1wc_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
|
||||
|
||||
|
||||
# FIFOS
|
||||
|
||||
# MIPS
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_cam.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_tlb.vhd"
|
||||
|
||||
vcom -explicit -93 "../src/tb_mips_tlb.vhd"
|
||||
vsim -t 1ps -lib work tb_tlb
|
||||
do {tb_mips_tlb.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 200us
|
||||
@@ -0,0 +1,74 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_tlb/clk_o
|
||||
add wave -noupdate -format Logic /tb_tlb/rst_o
|
||||
add wave -noupdate -format Logic /tb_tlb/ce
|
||||
add wave -noupdate -format Logic /tb_tlb/tlb_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/tlb_ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_query_out
|
||||
add wave -noupdate -divider TLB
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/hit_idx
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/num_entries
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/clk
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/blk_hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/blk_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/qry_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/stat_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/pa
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/cam_hit_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/vaddr_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_umc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_umuc
|
||||
add wave -noupdate -divider REG:LO
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_reg_entry_lo/dout_b
|
||||
add wave -noupdate -divider CAM
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/clk
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/state
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/state_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/tag_wr
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/tag_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe3
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe0_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe1_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe2_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe3_rd
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/busy
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/cam_ram_re
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/cam_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/cam_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/cam_ram_addr_rd
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/track_ram_re
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/track_ram_we
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/track_ram_addr_wr
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/track_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/track_ram_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/track_ram_dout
|
||||
add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/clear_addr
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/clear_count_en
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/clear_count_rdy
|
||||
add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/over_write
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/inst_track_ram/ram
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3385000 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 111
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {10940666 ps}
|
||||
@@ -2,7 +2,14 @@
|
||||
##
|
||||
vlib work
|
||||
|
||||
# Packages
|
||||
vcom -explicit -93 "../src/core/mips_util_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_types.vhd"
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r1wc_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
|
||||
@@ -34,11 +41,10 @@ vcom -explicit -93 "../../../misc/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs.vhd"
|
||||
|
||||
# ROM
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../src/bootloader_flash.ROM.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
|
||||
|
||||
# MIPS
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_shifter.vhd"
|
||||
@@ -47,6 +53,9 @@ vcom -explicit -93 "../src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_cop.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_cam.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_tlb.vhd"
|
||||
vcom -explicit -93 "../../../JBUS/src/busmaster_async.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
|
||||
|
||||
+334
-103
@@ -1,10 +1,12 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {TOP interface}
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_top/nmi
|
||||
add wave -noupdate -format Logic /tb_mips_top/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/debug
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/debug
|
||||
add wave -noupdate -format Logic /tb_mips_top/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_top/srdy_i
|
||||
@@ -13,7 +15,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/we_o
|
||||
add wave -noupdate -format Literal /tb_mips_top/sel_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/mrdy_o
|
||||
add wave -noupdate -format Literal /tb_mips_top/int
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout
|
||||
@@ -21,56 +22,87 @@ add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run
|
||||
add wave -noupdate -divider BIU
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en
|
||||
add wave -noupdate -divider Busmaster
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/rst
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_we
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/din
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/din_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/din_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/dout_vld
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/dout_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/rst_i
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/clk_i
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/addr_o
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/sel_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/we_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/mrdy_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cycle_busy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/read_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/write
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/jbus_cycle_busy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_busmaster/jbus_state
|
||||
add wave -noupdate -divider {External components}
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0
|
||||
add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
|
||||
add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
|
||||
add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_uart/uart_status_port
|
||||
add wave -noupdate -format Logic /tb_mips_top/rx
|
||||
add wave -noupdate -format Logic /tb_mips_top/tx
|
||||
add wave -noupdate -format Literal -radix ascii /tb_mips_top/inst_uart/reg_uart_tx
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_uart/reg_uart_rx
|
||||
add wave -noupdate -divider SRAM
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
|
||||
add wave -noupdate -format Literal /tb_mips_top/sram_be_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/sram_wr_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
|
||||
add wave -noupdate -divider FLASH
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
|
||||
add wave -noupdate -format Literal /tb_mips_top/flash_be_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_page_mode_en
|
||||
add wave -noupdate -divider {Interrupt Timer}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
|
||||
@@ -82,8 +114,6 @@ add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
|
||||
add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
|
||||
add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
|
||||
add wave -noupdate -format Logic /tb_mips_top/stb_o
|
||||
@@ -115,98 +145,299 @@ add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
|
||||
add wave -noupdate -divider ALU
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu
|
||||
add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu
|
||||
add wave -noupdate -divider PC
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc
|
||||
add wave -noupdate -divider COP0
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/itlb_exc
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/dtlb_exc
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/tlb_sel
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/itlb_entry_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/itlb_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dtlb_entry_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dtlb_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/entry_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/entry_lo
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ex_reg_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/regs
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/random
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/index
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state
|
||||
add wave -noupdate -divider Pipestages
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
|
||||
add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage.exc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.exc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/mem_stage.exc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage.exc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/dtlb_qry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/dtlb_qry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/itlb_qry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/itlb_qry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/icache_qry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/icache_qry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
|
||||
add wave -noupdate -divider I-Cache
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_busy_state
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_ctrl_state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/query_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/debug
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_va
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_pa
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/single_read_reg
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_set
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/read_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_req_rd
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/bus_din
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_vld
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/bus_cmd_out
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_cyc_complete
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_wr
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_rd_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_data_wr
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/ram_read_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/invalidate_req
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_word_index
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/req_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
|
||||
add wave -noupdate -divider I-TLB
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_out
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/pa
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/hit
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/vld_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/vaddr_reg
|
||||
add wave -noupdate -divider I-TLB-CAM
|
||||
add wave -noupdate -divider D-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/query_out
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy_state
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_ctrl_state
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_data_avail
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_through_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_full
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/debug
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_rd
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_va
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_pa
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_set
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/read_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_din
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_din_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout_vld
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_dout_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_cycle_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_cmd_out
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_cyc_complete
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit_inv
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_dout
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/be_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_addr
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_we
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_dout_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/invalidate_req
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_hit
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/ram_write_en
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_word_index
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/req_word_index
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/hit_cache_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_data_avail
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/read_write_buffer
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_through_en
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_sel_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_data_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_addr_out
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_sel_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_data_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/write_fifo_addr_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/inst_tag_ram/ram
|
||||
add wave -noupdate -divider D-TLB
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_d_tlb/query_out
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_d_tlb/blk_hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/blk_entry_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/pa
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_d_tlb/hit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_addr
|
||||
add wave -noupdate -format Literal -label reg_entry_lo_mem -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/inst_reg_entry_lo/reg_mem
|
||||
add wave -noupdate -divider D-TLB-CAM
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/rst
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clk_rd
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/we
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/tag_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/tag_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/hit
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/hit_vld
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/debug
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/state
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/state_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe3
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe0_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe1_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe2_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/pipe3_rd
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/busy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/vld_cam
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_result
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/cam_ram_addr_rd
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_re
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/track_ram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_addr
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_count_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/over_write
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {Cursor {5877623 ps} 0}
|
||||
WaveRestoreCursors {Cursor {24310024 ps} 0}
|
||||
configure wave -namecolwidth 188
|
||||
configure wave -valuecolwidth 154
|
||||
configure wave -justifyvalue left
|
||||
@@ -220,4 +451,4 @@ configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {5846736 ps} {5910641 ps}
|
||||
WaveRestoreZoom {24134231 ps} {24477503 ps}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,513 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
ENTITY dcache IS
|
||||
Generic
|
||||
(
|
||||
cache_size : natural := 2048; -- words
|
||||
line_size : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_we : in STD_LOGIC;
|
||||
cpu_be : in unsigned(3 downto 0);
|
||||
cpu_addr : in word_t;
|
||||
cpu_din : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
cpu_busy : out STD_LOGIC
|
||||
);
|
||||
END dcache;
|
||||
|
||||
ARCHITECTURE behavior OF dcache IS
|
||||
|
||||
|
||||
COMPONENT dpram_2w2r2c_ra is
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(line_size);
|
||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||
constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
|
||||
constant tag_parity_width : natural := 3;
|
||||
constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
|
||||
subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
|
||||
|
||||
type dcache_entry_t is record
|
||||
valid : std_logic;
|
||||
tv_p : unsigned(tag_parity_width-1 downto 0);
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
end record;
|
||||
|
||||
function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is
|
||||
variable result : dcache_entry_t;
|
||||
begin
|
||||
result.valid := x(0);
|
||||
result.tv_p := x(3 downto 1);
|
||||
result.tag := x(tag_width+3 downto 4);
|
||||
|
||||
return result;
|
||||
end to_dcache_entry;
|
||||
|
||||
function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is
|
||||
variable result : tag_ram_data_t;
|
||||
begin
|
||||
result(0) := x.valid;
|
||||
result(3 downto 1) := x.tv_p;
|
||||
result(tag_width+3 downto 4) := x.tag;
|
||||
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
|
||||
type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache);
|
||||
signal s, sn : cache_state_t;
|
||||
|
||||
signal cache_req : std_logic;
|
||||
signal cache_ack : std_logic;
|
||||
signal cache_busy : std_logic;
|
||||
signal cache_hit : std_logic;
|
||||
signal tag_match : std_logic;
|
||||
signal cache_hit_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
|
||||
signal request_addr : unsigned(addr_width-1 downto 0);
|
||||
signal fill_addr : unsigned(addr_width-1 downto 0);
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : dcache_entry_t;
|
||||
signal cache_entry_out : dcache_entry_t;
|
||||
signal cache_entry_out_inv : dcache_entry_t;
|
||||
signal cpu_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal cpu_data_ram_dout : word_t;
|
||||
signal cpu_data_reg : word_t;
|
||||
signal cpu_be_reg : unsigned(3 downto 0);
|
||||
signal cpu_we_reg : std_logic;
|
||||
signal ctrl_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal ctrl_data_ram_we : unsigned(3 downto 0);
|
||||
signal cpu_data_ram_we : unsigned(3 downto 0);
|
||||
signal cpu_we2 : std_logic;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_dout : tag_ram_data_t;
|
||||
signal tag_ram_dout_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_din : tag_ram_data_t;
|
||||
signal tag_ram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
signal cpu_hit_we : std_logic;
|
||||
signal instant_raw : std_logic;
|
||||
signal hit_cache_index : unsigned(cache_index_width-1 downto 0);
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias fill_word_index is fill_addr(word_index_width+1 downto 2);
|
||||
alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias req_word_index is request_addr(word_index_width+1 downto 2);
|
||||
alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
begin
|
||||
|
||||
cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
cpu_hit_we <= cpu_we2 and cache_hit;
|
||||
|
||||
fill_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '1' then
|
||||
if ACK_I = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '1'then
|
||||
if SRDY_I = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_request_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cpu_we_reg <= '0';
|
||||
cache_req <= '0';
|
||||
elsif cpu_en = '1' then
|
||||
if cache_busy = '0' then
|
||||
cpu_we2 <= cpu_we;
|
||||
cache_req <= '1';
|
||||
cpu_data_reg <= cpu_din;
|
||||
cpu_be_reg <= cpu_be;
|
||||
cpu_we_reg <= cpu_we;
|
||||
if cpu_we = '1' then
|
||||
hit_cache_index <= cpu_cache_index;
|
||||
end if;
|
||||
end if;
|
||||
elsif cache_ack = '1' then
|
||||
cache_req <= '0';
|
||||
cpu_we2 <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
instant_raw_logic:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
instant_raw <= '0';
|
||||
if cpu_word_index = fill_word_index and cpu_cache_index = hit_cache_index then
|
||||
instant_raw <= cpu_hit_we and cpu_en and not cpu_we;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_din,
|
||||
din_b => tag_ram_din,
|
||||
dout_a => tag_ram_dout_inv,
|
||||
dout_b => tag_ram_dout
|
||||
);
|
||||
|
||||
gen_data_ram:
|
||||
for i in 0 to 3 generate
|
||||
begin
|
||||
|
||||
inst_data_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => lg2(cache_size),
|
||||
data_width => word_t'length/4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => cpu_data_ram_we(i),
|
||||
we_b => ctrl_data_ram_we(i),
|
||||
addr_a => ctrl_data_ram_addr,
|
||||
addr_b => cpu_data_ram_addr,
|
||||
din_a => cpu_data_reg(8*(i+1)-1 downto 8*i),
|
||||
din_b => DAT_I(8*(i+1)-1 downto 8*i),
|
||||
dout_a => open,
|
||||
dout_b => cpu_data_ram_dout(8*(i+1)-1 downto 8*i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
cache_invalidate_request:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl.inv_all or RST_I;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= init;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= fill_count_en;
|
||||
ADDR_O <= request_addr;
|
||||
|
||||
cpu_busy <= cache_busy;
|
||||
cpu_dout <= cpu_data_ram_dout;
|
||||
|
||||
tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
|
||||
cache_hit <= tag_match and cache_entry_out.valid;
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid;
|
||||
tag_ram_din <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else fill_cache_index;
|
||||
|
||||
cache_entry_out <= to_dcache_entry(tag_ram_dout);
|
||||
cache_entry_out_inv <= to_dcache_entry(tag_ram_dout_inv);
|
||||
|
||||
cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index);
|
||||
ctrl_data_ram_addr <= fill_cache_index & fill_word_index;
|
||||
ctrl_data_ram_we <= (others => fill_count_en and ACK_I);
|
||||
cpu_data_ram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
|
||||
|
||||
cache_state:
|
||||
process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
CYC_O <= '0';
|
||||
STB_O <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
sn <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
else
|
||||
if cache_req = '1' then
|
||||
if cache_hit = '0' and cpu_we_reg = '0' then
|
||||
sn <= mem_request;
|
||||
CYC_O <= '1';
|
||||
else
|
||||
cache_busy <= instant_raw;
|
||||
cache_ack <= not instant_raw;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when invalidate =>
|
||||
sn <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
sn <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_hit_inv = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
when mem_request =>
|
||||
CYC_O <= '1';
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_access;
|
||||
end if;
|
||||
when mem_access =>
|
||||
fill_count_en <= '1';
|
||||
request_count_en <= '1';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
STB_O <= '0';
|
||||
sn <= mem_data;
|
||||
end if;
|
||||
when mem_data =>
|
||||
CYC_O <= '1';
|
||||
fill_count_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
when rd_cache =>
|
||||
was_miss <= '1';
|
||||
sn <= ready;
|
||||
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if ctrl.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if SRDY_I = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if ACK_I = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -1,488 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
ENTITY icache IS
|
||||
Generic
|
||||
(
|
||||
cache_size : natural := 2048; -- words
|
||||
line_size : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_addr : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
cpu_busy : out STD_LOGIC
|
||||
);
|
||||
END icache;
|
||||
|
||||
ARCHITECTURE behavior OF icache IS
|
||||
|
||||
COMPONENT dpram_1w1r2c_ra
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dpram_2w2r2c_ra is
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(line_size);
|
||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||
constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
|
||||
constant tag_parity_width : natural := 3;
|
||||
constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
|
||||
subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
|
||||
|
||||
type icache_entry_t is record
|
||||
valid : std_logic;
|
||||
tv_p : unsigned(tag_parity_width-1 downto 0);
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
end record;
|
||||
|
||||
function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
|
||||
variable result : icache_entry_t;
|
||||
begin
|
||||
result.valid := x(0);
|
||||
result.tv_p := x(3 downto 1);
|
||||
result.tag := x(tag_width+3 downto 4);
|
||||
|
||||
return result;
|
||||
end to_icache_entry;
|
||||
|
||||
function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is
|
||||
variable result : tag_ram_data_t;
|
||||
begin
|
||||
result(0) := x.valid;
|
||||
result(3 downto 1) := x.tv_p;
|
||||
result(tag_width+3 downto 4) := x.tag;
|
||||
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
|
||||
type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache, upd_cache);
|
||||
signal s, sn : cache_state_t;
|
||||
|
||||
signal cache_req : std_logic;
|
||||
signal cache_ack : std_logic;
|
||||
signal cache_busy : std_logic;
|
||||
signal cache_miss : std_logic;
|
||||
signal tag_match : std_logic;
|
||||
signal cache_miss_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
signal request_addr : unsigned(addr_width-1 downto 0);
|
||||
signal fill_addr : unsigned(addr_width-1 downto 0);
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : icache_entry_t;
|
||||
signal cache_entry_out : icache_entry_t;
|
||||
signal cache_entry_out_inv : icache_entry_t;
|
||||
signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal data_ram_data_rd : word_t;
|
||||
signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal data_ram_data_wr : word_t;
|
||||
signal data_ram_we : std_logic;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_rd : tag_ram_data_t;
|
||||
signal tag_ram_data_rd_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_wr : tag_ram_data_t;
|
||||
signal tag_ram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal ram_read_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias fill_word_index is fill_addr(word_index_width+1 downto 2);
|
||||
alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias req_word_index is request_addr(word_index_width+1 downto 2);
|
||||
alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
begin
|
||||
|
||||
ram_read_en <= cpu_en or was_miss;
|
||||
cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
|
||||
fill_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '1' then
|
||||
if ACK_I = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '1'then
|
||||
if SRDY_I = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_request_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cache_req <= '0';
|
||||
elsif cpu_en = '1' then
|
||||
if cache_busy = '0' then
|
||||
cache_req <= '1';
|
||||
end if;
|
||||
elsif cache_ack = '1' then
|
||||
cache_req <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_invalidate_request:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl.inv_all or RST_I;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_data_wr,
|
||||
din_b => tag_ram_data_wr,
|
||||
dout_a => tag_ram_data_rd_inv,
|
||||
dout_b => tag_ram_data_rd
|
||||
);
|
||||
|
||||
inst_data_ram : dpram_1w1r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => lg2(cache_size),
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => data_ram_we,
|
||||
addr_a => data_ram_addr_wr,
|
||||
addr_b => data_ram_addr_rd,
|
||||
din_a => data_ram_data_wr,
|
||||
dout_b => data_ram_data_rd
|
||||
);
|
||||
|
||||
cache_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= init;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= fill_count_en;
|
||||
ADDR_O <= fill_tag & fill_cache_index & req_word_index & "00";
|
||||
|
||||
cpu_busy <= cache_busy;
|
||||
cpu_dout <= data_ram_data_rd;
|
||||
|
||||
cache_entry_out <= to_icache_entry(tag_ram_data_rd);
|
||||
tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
|
||||
cache_miss <= not (tag_match and cache_entry_out.valid);
|
||||
|
||||
cache_entry_out_inv <= to_icache_entry(tag_ram_data_rd_inv);
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_miss_inv <= not (tag_match_inv and cache_entry_out_inv.valid);
|
||||
|
||||
tag_ram_data_wr <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else fill_cache_index;
|
||||
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index);
|
||||
data_ram_addr_wr <= fill_cache_index & fill_word_index;
|
||||
data_ram_data_wr <= DAT_I;
|
||||
data_ram_we <= fill_count_en and ACK_I;
|
||||
|
||||
cache_state:
|
||||
process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
CYC_O <= '0';
|
||||
STB_O <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
sn <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
elsif cache_req = '1' then
|
||||
if cache_miss = '1' then
|
||||
sn <= mem_request;
|
||||
CYC_O <= '1';
|
||||
else
|
||||
cache_busy <= '0';
|
||||
cache_ack <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when invalidate =>
|
||||
sn <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
sn <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_miss_inv = '0' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
when mem_request =>
|
||||
CYC_O <= '1';
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_access;
|
||||
end if;
|
||||
when mem_access =>
|
||||
request_count_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
STB_O <= '0';
|
||||
sn <= mem_data;
|
||||
end if;
|
||||
when mem_data =>
|
||||
CYC_O <= '1';
|
||||
fill_count_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
when rd_cache =>
|
||||
was_miss <= '1';
|
||||
sn <= ready;
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if ctrl.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if SRDY_I = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if ACK_I = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -56,21 +56,24 @@ architecture Behavioral of alu is
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
eq <= '1' when op1_in = op2_in else '0' after 3 ns;
|
||||
eq <= '1' when op1_in = op2_in else '0' after 1 ns;
|
||||
sa <= op1_in(op1_in'left);
|
||||
sb <= op2_in(op2_in'left);
|
||||
sr <= sum_res(sum_res'left);
|
||||
z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
|
||||
z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0';
|
||||
|
||||
flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr));
|
||||
flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr));
|
||||
-- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb))));
|
||||
lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr));
|
||||
|
||||
-- lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr));
|
||||
lts <= '1' when signed(op1_in) < signed(op2_in) else '0';
|
||||
|
||||
-- ltu <= (not eq) and (not c);
|
||||
ltu <= '1' when op1_in < op2_in else '0';
|
||||
|
||||
ltu <= (not eq) and (not c);
|
||||
flags.lts <= lts;
|
||||
flags.ltu <= ltu;
|
||||
flags.c <= c;
|
||||
flags.lts <= lts after 1 ns;
|
||||
flags.ltu <= ltu after 1 ns;
|
||||
flags.c <= c after 1 ns;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_op_and:
|
||||
|
||||
@@ -45,7 +45,7 @@ architecture Behavioral of bcu is
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns;
|
||||
flags.eq <= '1' when ((op1_in xor op2_in) = (data_width-1 downto 0 => '0')) else '0' after 1 ns;
|
||||
flags.ltz <= op1_in(op1_in'left) after 1 ns;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,399 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
entity biu is
|
||||
Generic
|
||||
(
|
||||
ICACHE_SIZE : natural := 2048; -- words
|
||||
ICACHE_LINE : natural := 8; -- words
|
||||
DCACHE_SIZE : natural := 2048; -- words
|
||||
DCACHE_LINE : natural := 8; -- words
|
||||
WRITE_FIFO_SIZE : natural := 4; -- words
|
||||
WITH_TLB : boolean := true;
|
||||
TRANSLATE_KSEG0_1 : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
busy : out STD_LOGIC;
|
||||
|
||||
imem_err : out STD_LOGIC;
|
||||
dmem_err : out STD_LOGIC;
|
||||
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
MDAT_I : in unsigned(31 downto 0);
|
||||
MDAT_O : out unsigned(31 downto 0);
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
|
||||
ctrl_in : in biu_ctrl_in_t;
|
||||
ctrl_out : out biu_ctrl_out_t
|
||||
|
||||
);
|
||||
end biu;
|
||||
|
||||
architecture behavior of biu is
|
||||
|
||||
type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
|
||||
|
||||
signal s, sn : bus_state_t;
|
||||
signal bus_idle : std_logic;
|
||||
|
||||
type timeout_cnt_t is range 0 to 1E5-1;
|
||||
signal bus_timeout_cnt : timeout_cnt_t;
|
||||
signal bus_timeout : std_logic;
|
||||
|
||||
-------------------------------------------------
|
||||
signal RST : std_logic;
|
||||
signal CPU_CLK : std_logic;
|
||||
|
||||
-- busmaster signals
|
||||
signal bus_din : word_t;
|
||||
signal bus_din_rdy : std_logic;
|
||||
signal bus_din_we : std_logic;
|
||||
|
||||
signal bus_dout : word_t;
|
||||
signal bus_dout_vld : std_logic;
|
||||
signal bus_dout_re : std_logic;
|
||||
|
||||
signal bus_cmd_rdy : std_logic;
|
||||
signal bus_cmd_we : std_logic;
|
||||
signal bus_cmd_cycle_en : std_logic;
|
||||
signal bus_cmd : bm_cmd_t;
|
||||
signal bus_cyc_complete : std_logic;
|
||||
|
||||
signal i_bus_din_rdy : std_logic;
|
||||
signal i_bus_cmd_rdy : std_logic;
|
||||
signal i_bus_cmd_we : std_logic;
|
||||
signal i_bus_cmd_cycle_en : std_logic;
|
||||
signal i_bus_cmd : bm_cmd_t;
|
||||
|
||||
signal i_tlb_rdy : std_logic;
|
||||
signal i_cache_rdy : std_logic;
|
||||
|
||||
signal d_bus_din_rdy : std_logic;
|
||||
signal d_bus_cmd_rdy : std_logic;
|
||||
signal d_bus_cmd_we : std_logic;
|
||||
signal d_bus_cmd_cycle_en : std_logic;
|
||||
signal d_bus_cmd : bm_cmd_t;
|
||||
|
||||
signal d_tlb_rdy : std_logic;
|
||||
signal d_cache_rdy : std_logic;
|
||||
|
||||
signal icache_bus_gnt : std_logic;
|
||||
signal dcache_bus_gnt : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
CPU_CLK <= clk;
|
||||
RST <= RST_I;
|
||||
|
||||
biu_busy_state:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if RST_I = '1' then
|
||||
busy <= '1';
|
||||
elsif (i_tlb_rdy and i_cache_rdy and d_cache_rdy and d_tlb_rdy) = '1' then
|
||||
busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_busmaster : entity work.busmaster_async
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 16
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CPU_CLK,
|
||||
|
||||
cmd_cycle_finished => bus_cyc_complete,
|
||||
cmd_cycle_en => bus_cmd_cycle_en,
|
||||
|
||||
cmd_rdy => bus_cmd_rdy,
|
||||
cmd_we => bus_cmd_we,
|
||||
cmd_in => bus_cmd,
|
||||
|
||||
din_rdy => bus_din_rdy,
|
||||
din_we => bus_din_we,
|
||||
din => bus_din,
|
||||
|
||||
dout => bus_dout,
|
||||
dout_vld => bus_dout_vld,
|
||||
dout_re => bus_dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
RST_I => RST_I,
|
||||
CLK_I => CLK_I,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
inst_i_tlb : entity work.tlb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => TLB_NUM_ENTRIES,
|
||||
CACHE_KSEG1 => false,
|
||||
TRANSLATE_KSEG0_1 => TRANSLATE_KSEG0_1,
|
||||
USE_TLB => WITH_TLB
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CPU_CLK,
|
||||
ce => '1',
|
||||
|
||||
rdy => i_tlb_rdy,
|
||||
|
||||
ctrl_in => ctrl_in.itlb_ctrl,
|
||||
ctrl_out => ctrl_out.itlb_ctrl,
|
||||
|
||||
query_in => ctrl_in.itlb_qry,
|
||||
query_out => ctrl_out.itlb_qry
|
||||
|
||||
);
|
||||
|
||||
inst_icache: entity work.icache
|
||||
GENERIC MAP
|
||||
(
|
||||
CACHE_SIZE => ICACHE_SIZE,
|
||||
LINE_SIZE => ICACHE_LINE
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CPU_CLK,
|
||||
rdy => i_cache_rdy,
|
||||
|
||||
-- CPU control/data
|
||||
query_in => ctrl_in.icache_qry,
|
||||
query_out => ctrl_out.icache_qry,
|
||||
|
||||
-- Cache control
|
||||
ctrl_in => ctrl_in.icache,
|
||||
|
||||
-- busmaster data
|
||||
bus_din => bus_dout,
|
||||
bus_din_rdy => i_bus_din_rdy,
|
||||
bus_din_vld => bus_dout_vld,
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy => i_bus_cmd_rdy,
|
||||
bus_cmd_we => i_bus_cmd_we,
|
||||
bus_cmd_cycle_en => i_bus_cmd_cycle_en,
|
||||
bus_cmd_out => i_bus_cmd,
|
||||
bus_cyc_complete => bus_cyc_complete
|
||||
);
|
||||
|
||||
|
||||
inst_d_tlb : entity work.tlb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => TLB_NUM_ENTRIES,
|
||||
CACHE_KSEG1 => false,
|
||||
TRANSLATE_KSEG0_1 => TRANSLATE_KSEG0_1,
|
||||
USE_TLB => WITH_TLB
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CPU_CLK,
|
||||
ce => '1',
|
||||
|
||||
rdy => d_tlb_rdy,
|
||||
|
||||
ctrl_in => ctrl_in.dtlb_ctrl,
|
||||
ctrl_out => ctrl_out.dtlb_ctrl,
|
||||
|
||||
query_in => ctrl_in.dtlb_qry,
|
||||
query_out => ctrl_out.dtlb_qry
|
||||
|
||||
);
|
||||
|
||||
inst_dcache: entity work.dcache
|
||||
GENERIC MAP
|
||||
(
|
||||
CACHE_SIZE => DCACHE_SIZE,
|
||||
LINE_SIZE => DCACHE_LINE,
|
||||
WRITE_FIFO_SIZE => WRITE_FIFO_SIZE
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CPU_CLK,
|
||||
rdy => d_cache_rdy,
|
||||
|
||||
-- CPU control/data
|
||||
query_in => ctrl_in.dcache_qry,
|
||||
query_out => ctrl_out.dcache_qry,
|
||||
|
||||
-- Cache control
|
||||
ctrl_in => ctrl_in.dcache,
|
||||
|
||||
-- busmaster data
|
||||
bus_din => bus_dout,
|
||||
bus_din_rdy => d_bus_din_rdy,
|
||||
bus_din_vld => bus_dout_vld,
|
||||
|
||||
bus_dout => bus_din,
|
||||
bus_dout_vld => bus_din_we,
|
||||
bus_dout_rdy => bus_din_rdy,
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy => d_bus_cmd_rdy,
|
||||
bus_cmd_we => d_bus_cmd_we,
|
||||
bus_cmd_cycle_en => d_bus_cmd_cycle_en,
|
||||
bus_cmd_out => d_bus_cmd,
|
||||
bus_cyc_complete => bus_cyc_complete
|
||||
);
|
||||
|
||||
|
||||
bus_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if RST_I = '1' then
|
||||
s <= init;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_state:
|
||||
process(s, i_bus_cmd_cycle_en, d_bus_cmd_cycle_en, i_bus_cmd_we, i_bus_cmd, d_bus_cmd_we, d_bus_cmd, bus_cyc_complete, i_bus_din_rdy, d_bus_din_rdy, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
icache_bus_gnt <= '0';
|
||||
dcache_bus_gnt <= '0';
|
||||
|
||||
i_bus_cmd_rdy <= '0';
|
||||
d_bus_cmd_rdy <= '0';
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
bus_cmd <= i_bus_cmd;
|
||||
bus_dout_re <= '0';
|
||||
bus_idle <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
when ready =>
|
||||
bus_idle <= '1';
|
||||
if i_bus_cmd_cycle_en = '1' then
|
||||
sn <= icache_bus_access;
|
||||
elsif d_bus_cmd_cycle_en = '1' then
|
||||
sn <= dcache_bus_access;
|
||||
end if;
|
||||
when icache_bus_access =>
|
||||
icache_bus_gnt <= '1';
|
||||
i_bus_cmd_rdy <= bus_cmd_rdy;
|
||||
bus_cmd_cycle_en <= i_bus_cmd_cycle_en;
|
||||
bus_cmd_we <= i_bus_cmd_we;
|
||||
bus_dout_re <= i_bus_din_rdy;
|
||||
if i_bus_cmd_cycle_en = '0' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when dcache_bus_access =>
|
||||
dcache_bus_gnt <= '1';
|
||||
d_bus_cmd_rdy <= bus_cmd_rdy;
|
||||
bus_cmd_cycle_en <= d_bus_cmd_cycle_en;
|
||||
bus_cmd <= d_bus_cmd;
|
||||
bus_cmd_we <= d_bus_cmd_we;
|
||||
bus_dout_re <= d_bus_din_rdy;
|
||||
if d_bus_cmd_cycle_en = '0' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
bus_timeout_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if bus_idle = '0' then
|
||||
if bus_timeout_cnt /= 0 then
|
||||
bus_timeout_cnt <= bus_timeout_cnt - 1;
|
||||
else
|
||||
bus_timeout <= '1';
|
||||
end if;
|
||||
else
|
||||
bus_timeout_cnt <= timeout_cnt_t'high;
|
||||
bus_timeout <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_err:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if RST_I = '1' then
|
||||
imem_err <= '0';
|
||||
dmem_err <= '0';
|
||||
elsif bus_timeout = '1' then
|
||||
imem_err <= icache_bus_gnt;
|
||||
dmem_err <= dcache_bus_gnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
|
||||
end behavior;
|
||||
@@ -1,552 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
entity biu is
|
||||
Generic
|
||||
(
|
||||
icache_size : natural := 2048; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 2048; -- words
|
||||
dcache_line : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
cop0_ctrl_in : in cop0_ctrl_out_t;
|
||||
cpu_clk : in STD_LOGIC;
|
||||
cpu_imem_err : out STD_LOGIC;
|
||||
cpu_imem_rdy : out STD_LOGIC;
|
||||
cpu_imem_en : in STD_LOGIC;
|
||||
cpu_imem_addr : in word_t;
|
||||
cpu_imem_din : out word_t;
|
||||
cpu_dmem_err : out STD_LOGIC;
|
||||
cpu_dmem_rdy : out STD_LOGIC;
|
||||
cpu_dmem_en : in STD_LOGIC;
|
||||
cpu_dmem_we : in STD_LOGIC;
|
||||
cpu_dmem_be : in unsigned(3 downto 0);
|
||||
cpu_dmem_dout : in word_t;
|
||||
cpu_dmem_din : out word_t;
|
||||
cpu_dmem_addr : in word_t
|
||||
);
|
||||
end biu;
|
||||
|
||||
architecture behavior of biu is
|
||||
|
||||
COMPONENT icache
|
||||
GENERIC
|
||||
(
|
||||
cache_size : natural; -- words
|
||||
line_size : natural -- words
|
||||
);
|
||||
PORT
|
||||
(
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_addr : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
cpu_busy : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dcache
|
||||
GENERIC
|
||||
(
|
||||
cache_size : natural; -- words
|
||||
line_size : natural -- words
|
||||
);
|
||||
PORT
|
||||
(
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_we : in STD_LOGIC;
|
||||
cpu_be : in unsigned(3 downto 0);
|
||||
cpu_addr : in word_t;
|
||||
cpu_din : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
cpu_busy : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
|
||||
|
||||
signal s, sn : bus_state_t;
|
||||
signal bus_idle : std_logic;
|
||||
signal busy : std_logic;
|
||||
signal dmem_be : unsigned(3 downto 0);
|
||||
signal dcache_dout : word_t;
|
||||
signal dcache_mem_gnt : std_logic;
|
||||
signal icache_mem_gnt : std_logic;
|
||||
signal dmem_mem_wr_gnt : std_logic;
|
||||
signal dmem_mem_rd_gnt : std_logic;
|
||||
signal dcache_busy : std_logic;
|
||||
signal icache_busy : std_logic;
|
||||
signal CYC_O_icache : std_logic;
|
||||
signal CYC_O_dcache : std_logic;
|
||||
signal CYC_O_dmem_rd : std_logic;
|
||||
signal CYC_O_dmem_wr : std_logic;
|
||||
signal SRDY_I_icache : std_logic;
|
||||
signal SRDY_I_dcache : std_logic;
|
||||
signal MRDY_O_icache : std_logic;
|
||||
signal MRDY_O_dcache : std_logic;
|
||||
signal ADDR_O_icache : word_t;
|
||||
signal ADDR_O_dcache : word_t;
|
||||
signal ADDR_O_dmem_rd : word_t;
|
||||
signal ADDR_O_dmem_wr : word_t;
|
||||
signal STB_O_icache : std_logic;
|
||||
signal STB_O_dcache : std_logic;
|
||||
signal STB_O_dmem_rd : std_logic;
|
||||
signal STB_O_dmem_wr : std_logic;
|
||||
signal DAT_I_dmem_rd : word_t;
|
||||
signal DAT_O_dmem_wr : word_t;
|
||||
signal SEL_O_dmem_wr : unsigned(3 downto 0);
|
||||
signal SEL_O_dmem_rd : unsigned(3 downto 0);
|
||||
signal dcached : std_logic;
|
||||
signal dcache_en2 : std_logic;
|
||||
signal dcache_en : std_logic;
|
||||
signal uncached_access : std_logic;
|
||||
signal ACK : std_logic;
|
||||
signal DAT : unsigned(31 downto 0);
|
||||
|
||||
type timeout_cnt_t is range 0 to 1E5-1;
|
||||
signal bus_timeout_cnt : timeout_cnt_t;
|
||||
signal bus_timeout : std_logic;
|
||||
|
||||
signal bout_fifo_din : unsigned(68 downto 0);
|
||||
signal bout_fifo_dout : unsigned(68 downto 0);
|
||||
signal bout_fifo_re : std_logic;
|
||||
signal bout_fifo_we : std_logic;
|
||||
signal bout_fifo_full : std_logic;
|
||||
signal bout_fifo_empty : std_logic;
|
||||
signal bout_rdy : std_logic;
|
||||
|
||||
signal bin_fifo_din : unsigned(31 downto 0);
|
||||
signal bin_fifo_dout : unsigned(31 downto 0);
|
||||
signal bin_fifo_re : std_logic;
|
||||
signal bin_fifo_we : std_logic;
|
||||
signal bin_fifo_full : std_logic;
|
||||
signal bin_fifo_empty : std_logic;
|
||||
|
||||
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
|
||||
alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
|
||||
alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
|
||||
alias bout_fifo_we_in is bout_fifo_din(68);
|
||||
alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
|
||||
alias bout_fifo_data_out is bout_fifo_dout(63 downto 32);
|
||||
alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64);
|
||||
alias bout_fifo_we_out is bout_fifo_dout(68);
|
||||
|
||||
signal write_fifo_din : unsigned(67 downto 0);
|
||||
signal write_fifo_dout : unsigned(67 downto 0);
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
|
||||
alias write_fifo_addr_in is write_fifo_din(31 downto 0);
|
||||
alias write_fifo_data_in is write_fifo_din(63 downto 32);
|
||||
alias write_fifo_sel_in is write_fifo_din(67 downto 64);
|
||||
alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
|
||||
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
|
||||
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
|
||||
|
||||
signal read_cycle : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
read_cyc_register:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if RST_I = '1' then
|
||||
read_cycle <= '0';
|
||||
else
|
||||
read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd)
|
||||
or (dcache_mem_gnt and CYC_O_dcache)
|
||||
or (icache_mem_gnt and CYC_O_icache);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= not bin_fifo_full;
|
||||
CYC_O <= not bout_fifo_empty or read_cycle;
|
||||
STB_O <= not bout_fifo_empty;
|
||||
ADDR_O <= bout_fifo_addr_out;
|
||||
DAT_O <= bout_fifo_data_out;
|
||||
SEL_O <= bout_fifo_sel_out;
|
||||
WE_O <= bout_fifo_we_out;
|
||||
|
||||
cpu_imem_rdy <= not icache_busy after 4.5 ns;
|
||||
busy <= CYC_O_dmem_rd or dcache_busy or (write_fifo_full);
|
||||
cpu_dmem_rdy <= not busy after 4.5 ns;
|
||||
|
||||
inst_icache : icache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => icache_size, -- words
|
||||
line_size => icache_line -- words
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => cpu_clk,
|
||||
RST_I => RST_I,
|
||||
STB_O => STB_O_icache,
|
||||
CYC_O => CYC_O_icache,
|
||||
ADDR_O => ADDR_O_icache,
|
||||
MRDY_O => MRDY_O_icache,
|
||||
DAT_I => DAT,
|
||||
ACK_I => ACK,
|
||||
SRDY_I => SRDY_I_icache,
|
||||
ctrl => cop0_ctrl_in.icache,
|
||||
cpu_en => cpu_imem_en,
|
||||
cpu_addr => cpu_imem_addr,
|
||||
cpu_dout => cpu_imem_din,
|
||||
cpu_busy => icache_busy
|
||||
);
|
||||
|
||||
SRDY_I_icache <= bout_rdy and icache_mem_gnt;
|
||||
|
||||
inst_dcache : dcache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => dcache_size, -- words
|
||||
line_size => dcache_line -- words
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => cpu_clk,
|
||||
RST_I => RST_I,
|
||||
CYC_O => CYC_O_dcache,
|
||||
STB_O => STB_O_dcache,
|
||||
ADDR_O => ADDR_O_dcache,
|
||||
MRDY_O => MRDY_O_dcache,
|
||||
DAT_I => DAT,
|
||||
ACK_I => ACK,
|
||||
SRDY_I => SRDY_I_dcache,
|
||||
ctrl => cop0_ctrl_in.dcache,
|
||||
cpu_en => dcache_en,
|
||||
cpu_we => cpu_dmem_we,
|
||||
cpu_be => cpu_dmem_be,
|
||||
cpu_addr => cpu_dmem_addr,
|
||||
cpu_din => cpu_dmem_dout,
|
||||
cpu_dout => dcache_dout,
|
||||
cpu_busy => dcache_busy
|
||||
);
|
||||
|
||||
SRDY_I_dcache <= bout_rdy and dcache_mem_gnt;
|
||||
|
||||
dcached <= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0';
|
||||
cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
|
||||
dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_fifo_full);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_bin_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 32,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk_w => CLK_I,
|
||||
clk_r => cpu_clk,
|
||||
we => bin_fifo_we,
|
||||
re => bin_fifo_re,
|
||||
fifo_full => bin_fifo_full,
|
||||
fifo_empty => bin_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => bin_fifo_din,
|
||||
data_r => bin_fifo_dout
|
||||
);
|
||||
|
||||
bin_fifo_din <= DAT_I;
|
||||
DAT <= bin_fifo_dout;
|
||||
ACK <= not bin_fifo_empty;
|
||||
bin_fifo_we <= ACK_I;
|
||||
bin_fifo_re <= dmem_mem_rd_gnt or MRDY_O_icache or MRDY_O_dcache;
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_bout_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 69,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk_w => cpu_clk,
|
||||
clk_r => CLK_I,
|
||||
we => bout_fifo_we,
|
||||
re => bout_fifo_re,
|
||||
fifo_full => bout_fifo_full,
|
||||
fifo_empty => bout_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => bout_fifo_din,
|
||||
data_r => bout_fifo_dout
|
||||
);
|
||||
bout_rdy <= not bout_fifo_full;
|
||||
bout_fifo_re <= SRDY_I and not bin_fifo_full;
|
||||
|
||||
bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
|
||||
|
||||
bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
|
||||
|
||||
bout_fifo_addr_in <= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
||||
ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else
|
||||
ADDR_O_dcache when dcache_mem_gnt = '1' else
|
||||
ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
|
||||
|
||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
||||
SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
|
||||
|
||||
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_write_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 68,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk => cpu_clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => write_fifo_din,
|
||||
data_r => write_fifo_dout
|
||||
);
|
||||
|
||||
CYC_O_dmem_wr <= not write_fifo_empty;
|
||||
DAT_O_dmem_wr <= write_fifo_data_out;
|
||||
ADDR_O_dmem_wr <= write_fifo_addr_out;
|
||||
SEL_O_dmem_wr <= write_fifo_sel_out;
|
||||
|
||||
write_fifo_data_in <= cpu_dmem_dout;
|
||||
write_fifo_addr_in <= cpu_dmem_addr;
|
||||
write_fifo_sel_in <= cpu_dmem_be;
|
||||
write_fifo_re <= STB_O_dmem_wr;
|
||||
write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we;
|
||||
|
||||
dmem_rd_flags:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
uncached_access <= '0';
|
||||
if RST_I = '1' then
|
||||
CYC_O_dmem_rd <= '0';
|
||||
dcache_en2 <= '1';
|
||||
else
|
||||
if ACK = '1' and dmem_mem_rd_gnt = '1' then
|
||||
uncached_access <= '1';
|
||||
CYC_O_dmem_rd <= '0';
|
||||
dcache_en2 <= '1';
|
||||
end if;
|
||||
if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
|
||||
if dcached = '0' then
|
||||
CYC_O_dmem_rd <= '1';
|
||||
dcache_en2 <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dmem_rd_data:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if RST_I = '1' then
|
||||
DAT_I_dmem_rd <= (others => '0');
|
||||
elsif ACK = '1' and CYC_O_dmem_rd = '1' then
|
||||
DAT_I_dmem_rd <= DAT;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dmem_rd_regs:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if cpu_dmem_en = '1' and busy = '0' then
|
||||
ADDR_O_dmem_rd <= cpu_dmem_addr;
|
||||
SEL_O_dmem_rd <= cpu_dmem_be;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_state_next:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if RST_I = '1' then
|
||||
s <= init;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_state:
|
||||
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK)
|
||||
begin
|
||||
|
||||
icache_mem_gnt <= '0';
|
||||
dcache_mem_gnt <= '0';
|
||||
dmem_mem_rd_gnt <= '0';
|
||||
dmem_mem_wr_gnt <= '0';
|
||||
STB_O_dmem_rd <= '0';
|
||||
STB_O_dmem_wr <= '0';
|
||||
bus_idle <= '0';
|
||||
sn <= s;
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
when ready =>
|
||||
bus_idle <= '1';
|
||||
if CYC_O_dmem_wr = '1' then
|
||||
sn <= write_bus;
|
||||
elsif CYC_O_dmem_rd = '1' then
|
||||
sn <= read_bus;
|
||||
elsif CYC_O_icache = '1' then
|
||||
sn <= icache_bus_access;
|
||||
elsif CYC_O_dcache = '1' then
|
||||
sn <= dcache_bus_access;
|
||||
end if;
|
||||
when icache_bus_access =>
|
||||
icache_mem_gnt <= '1';
|
||||
if CYC_O_icache = '0' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when dcache_bus_access =>
|
||||
dcache_mem_gnt <= '1';
|
||||
if CYC_O_dcache = '0' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when write_bus =>
|
||||
dmem_mem_wr_gnt <= '1';
|
||||
if CYC_O_dmem_wr = '1' then
|
||||
if bout_rdy = '1' then
|
||||
STB_O_dmem_wr <= '1';
|
||||
end if;
|
||||
else
|
||||
sn <= ready;
|
||||
end if;
|
||||
when read_bus =>
|
||||
dmem_mem_rd_gnt <= '1';
|
||||
if bout_rdy = '1' then
|
||||
STB_O_dmem_rd <= '1';
|
||||
sn <= read_finish;
|
||||
end if;
|
||||
when read_finish =>
|
||||
dmem_mem_rd_gnt <= '1';
|
||||
if ACK = '1' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
bus_timeout_counter:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if bus_idle = '0' then
|
||||
if bus_timeout_cnt /= 0 then
|
||||
bus_timeout_cnt <= bus_timeout_cnt - 1;
|
||||
else
|
||||
bus_timeout <= '1';
|
||||
end if;
|
||||
else
|
||||
bus_timeout_cnt <= timeout_cnt_t'high;
|
||||
bus_timeout <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_err:
|
||||
process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if RST_I = '1' then
|
||||
cpu_imem_err <= '0';
|
||||
cpu_dmem_err <= '0';
|
||||
elsif bus_timeout = '1' then
|
||||
cpu_imem_err <= icache_mem_gnt;
|
||||
cpu_dmem_err <= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
|
||||
end behavior;
|
||||
@@ -1,3 +1,26 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
+594
-277
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,777 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.mips_types.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY dcache IS
|
||||
Generic
|
||||
(
|
||||
CACHE_SIZE : natural := 1024; -- words
|
||||
LINE_SIZE : natural := 8; -- words
|
||||
WRITE_FIFO_SIZE : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
rdy : out STD_LOGIC;
|
||||
|
||||
-- CPU control/data
|
||||
query_in : in dcache_query_in_t;
|
||||
query_out : out dcache_query_out_t;
|
||||
|
||||
-- Cache control
|
||||
ctrl_in : in cache_ctrl_t;
|
||||
|
||||
-- busmaster data
|
||||
bus_din : in word_t;
|
||||
bus_din_rdy : out std_logic;
|
||||
bus_din_vld : in std_logic;
|
||||
|
||||
bus_dout : out word_t;
|
||||
bus_dout_vld : out std_logic;
|
||||
bus_dout_rdy : in std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
bus_cmd_out : out bm_cmd_t;
|
||||
bus_cyc_complete : in std_logic
|
||||
|
||||
);
|
||||
END dcache;
|
||||
|
||||
ARCHITECTURE behavior OF dcache IS
|
||||
|
||||
|
||||
COMPONENT dpram_2w2r2c_ra is
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(LINE_SIZE);
|
||||
constant cache_index_width : natural := lg2(CACHE_SIZE) - word_index_width;
|
||||
constant tag_width : natural := addr_width - lg2(CACHE_SIZE) - 2;
|
||||
constant tag_ram_data_width : natural := 1 + tag_width + lg2(TLB_NUM_ENTRIES)+1;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
|
||||
subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
|
||||
|
||||
type dcache_entry_t is record
|
||||
valid : std_logic;
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
idx : unsigned(lg2(TLB_NUM_ENTRIES) downto 0);
|
||||
end record;
|
||||
|
||||
function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is
|
||||
variable result : dcache_entry_t;
|
||||
begin
|
||||
result.valid := x(0);
|
||||
result.tag := x(tag_width downto 1);
|
||||
result.idx := x(lg2(TLB_NUM_ENTRIES)+tag_width+1 downto tag_width+1);
|
||||
|
||||
return result;
|
||||
end to_dcache_entry;
|
||||
|
||||
function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is
|
||||
variable result : tag_ram_data_t;
|
||||
begin
|
||||
result(0) := x.valid;
|
||||
result(tag_width downto 1) := x.tag;
|
||||
result(lg2(TLB_NUM_ENTRIES)+tag_width+1 downto tag_width+1) := x.idx;
|
||||
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
|
||||
function to_word_index(x : word_t) return unsigned is
|
||||
variable result : unsigned(word_index_width-1 downto 0);
|
||||
begin
|
||||
result := x(word_index_width+1 downto 2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_word_index;
|
||||
|
||||
|
||||
function to_cache_index(x : word_t) return unsigned is
|
||||
variable result : unsigned(cache_index_width-1 downto 0);
|
||||
begin
|
||||
result := x(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_cache_index;
|
||||
|
||||
function to_tag(x : word_t) return unsigned is
|
||||
variable result : unsigned(tag_width-1 downto 0);
|
||||
begin
|
||||
result := x(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_tag;
|
||||
|
||||
|
||||
type cache_busy_state_t is (init, ready, busy);
|
||||
signal cache_busy_state, cache_busy_state_next : cache_busy_state_t;
|
||||
|
||||
type cache_ctrl_state_t is (init, ready, invalidate, invalidate_post, flush, bus_request, mem_read, mem_read_single, mem_read_data, mem_read_data_single, rd_cache, upd_cache, wait_write_thru);
|
||||
signal cache_ctrl_state, cache_ctrl_state_next : cache_ctrl_state_t;
|
||||
|
||||
type debug_t is record
|
||||
ready : std_logic;
|
||||
req_strobe : std_logic;
|
||||
req_read : std_logic;
|
||||
req_write : std_logic;
|
||||
req_va : word_t;
|
||||
req_pa : word_t;
|
||||
dout_reg : word_t;
|
||||
din_reg : word_t;
|
||||
end record;
|
||||
|
||||
signal debug : debug_t;
|
||||
|
||||
signal req_strobe : std_logic;
|
||||
signal cache_req : std_logic;
|
||||
signal cache_req_rd : std_logic;
|
||||
signal cache_req_wr : std_logic;
|
||||
signal cache_rdy : std_logic;
|
||||
signal cache_hit : std_logic;
|
||||
signal read_rdy : std_logic;
|
||||
signal write_rdy : std_logic;
|
||||
signal request_va : word_t;
|
||||
signal request_pa : word_t;
|
||||
signal request_nc : std_logic;
|
||||
|
||||
signal tag_match : std_logic;
|
||||
signal cache_hit_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
|
||||
signal mem_fetch_req : std_logic;
|
||||
signal mem_fetch_ack : std_logic;
|
||||
signal single_read_en : std_logic;
|
||||
signal single_read_set : std_logic;
|
||||
signal single_read_reg_vld : std_logic;
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : dcache_entry_t;
|
||||
signal cache_entry_out : dcache_entry_t;
|
||||
signal cache_entry_out_inv : dcache_entry_t;
|
||||
signal data_ram_addr : unsigned(lg2(CACHE_SIZE)-1 downto 0);
|
||||
signal data_ram_dout : word_t;
|
||||
signal din_reg : word_t;
|
||||
signal be_reg : unsigned(3 downto 0);
|
||||
signal ctrl_data_ram_addr : unsigned(lg2(CACHE_SIZE)-1 downto 0);
|
||||
signal ctrl_data_ram_we : unsigned(3 downto 0);
|
||||
signal data_ram_we : unsigned(3 downto 0);
|
||||
signal single_read_reg : word_t;
|
||||
signal cache_dout : word_t;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_dout : tag_ram_data_t;
|
||||
signal tag_ram_dout_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_din : tag_ram_data_t;
|
||||
signal tag_ram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal ram_read_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
signal write_hit : std_logic;
|
||||
signal instant_raw : std_logic;
|
||||
signal ram_write_en : std_logic;
|
||||
signal fill_word_index : unsigned(word_index_width-1 downto 0);
|
||||
signal req_word_index : unsigned(word_index_width-1 downto 0);
|
||||
signal hit_cache_index : unsigned(cache_index_width-1 downto 0);
|
||||
|
||||
signal write_fifo_din : unsigned(67 downto 0);
|
||||
signal write_fifo_dout : unsigned(67 downto 0);
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal write_data_avail : std_logic;
|
||||
signal read_write_buffer : std_logic;
|
||||
|
||||
alias write_fifo_addr_in is write_fifo_din(31 downto 0);
|
||||
alias write_fifo_data_in is write_fifo_din(63 downto 32);
|
||||
alias write_fifo_sel_in is write_fifo_din(67 downto 64);
|
||||
alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
|
||||
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
|
||||
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
|
||||
|
||||
signal write_through_en : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Print info
|
||||
assert false report "addr_width = " & natural'image(addr_width) & "." severity note;
|
||||
assert false report "tag_width = " & natural'image(tag_width) & "." severity note;
|
||||
assert false report "word_index_width = " & natural'image(word_index_width) & "." severity note;
|
||||
assert false report "cache_index_width = " & natural'image(cache_index_width) & "." severity note;
|
||||
|
||||
cache_index_inv <= ctrl_in.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl_in.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
bus_din_rdy <= fill_count_en or single_read_en;
|
||||
bus_cmd_out.addr <= write_fifo_addr_out when read_write_buffer = '1' else to_tag(request_pa) & to_cache_index(request_pa) & req_word_index & "00";
|
||||
bus_cmd_out.rw <= read_write_buffer;
|
||||
bus_cmd_out.sel <= write_fifo_sel_out when read_write_buffer = '1' else (others => '1');
|
||||
bus_dout <= write_fifo_data_out;
|
||||
bus_dout_vld <= read_write_buffer and write_data_avail;
|
||||
|
||||
-- tlb_query_out.vld <= cache_req;
|
||||
-- tlb_query_out.vaddr <= request_va;
|
||||
-- tlb_query_out.write <= cache_req_wr;
|
||||
-- tlb_query_out.vld <= req_strobe;
|
||||
-- tlb_query_out.vaddr <= query_in.addr;
|
||||
-- tlb_query_out.idx <= cache_entry_out.idx;
|
||||
-- tlb_query_out.write <= query_in.we;
|
||||
|
||||
request_pa <= request_va;
|
||||
|
||||
write_hit <= cache_req_wr and cache_hit; -- and not tlb_query_in.exc;
|
||||
|
||||
debug.req_strobe <= req_strobe;
|
||||
debug.req_read <= cache_req_rd;
|
||||
debug.req_write <= cache_req_wr;
|
||||
debug.req_va <= request_va;
|
||||
debug.req_pa <= request_pa;
|
||||
debug.din_reg <= din_reg;
|
||||
debug.dout_reg <= cache_dout;
|
||||
debug.ready <= cache_rdy;
|
||||
|
||||
-------------------------------------------------
|
||||
-- ctrl
|
||||
-------------------------------------------------
|
||||
req_strobe <= cache_rdy and query_in.en;
|
||||
|
||||
request_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cache_req_rd <= '0';
|
||||
cache_req_wr <= '0';
|
||||
elsif cache_rdy = '1' then
|
||||
cache_req_rd <= query_in.en and not query_in.we;
|
||||
cache_req_wr <= query_in.en and query_in.we;
|
||||
cache_req <= query_in.en;
|
||||
if query_in.we = '1' then
|
||||
hit_cache_index <= to_cache_index(query_in.addr);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_address_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
request_va <= (others => '0');
|
||||
request_nc <= '0';
|
||||
elsif req_strobe = '1' then
|
||||
din_reg <= query_in.data;
|
||||
be_reg <= query_in.be;
|
||||
request_va <= query_in.addr;
|
||||
request_nc <= query_in.nc;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
instant_raw_logic:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
instant_raw <= '0';
|
||||
if to_word_index(query_in.addr) = fill_word_index and to_cache_index(query_in.addr) = hit_cache_index then
|
||||
instant_raw <= write_hit and query_in.en and not query_in.we;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_write_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => lg2(WRITE_FIFO_SIZE),
|
||||
data_width => 68,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => write_fifo_din,
|
||||
data_r => write_fifo_dout
|
||||
);
|
||||
|
||||
write_fifo_data_in <= din_reg;
|
||||
write_fifo_addr_in <= request_pa;
|
||||
write_fifo_sel_in <= be_reg;
|
||||
write_fifo_re <= read_write_buffer and bus_dout_rdy and bus_cmd_rdy;
|
||||
write_fifo_we <= write_through_en;
|
||||
write_data_avail <= not write_fifo_empty;
|
||||
|
||||
fill_address_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if req_strobe = '1' then
|
||||
fill_word_index <= to_word_index(query_in.addr);
|
||||
elsif bus_din_vld = '1' and fill_count_en = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_request_address_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if req_strobe = '1' then
|
||||
req_word_index <= to_word_index(query_in.addr);
|
||||
elsif request_count_en = '1' and bus_cmd_rdy = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
single_read_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
single_read_en <= '0';
|
||||
single_read_reg_vld <= '0';
|
||||
elsif single_read_en = '0' then
|
||||
if single_read_set = '1' then
|
||||
single_read_en <= '1';
|
||||
end if;
|
||||
elsif single_read_reg_vld = '1' then
|
||||
if query_in.en = '1' then
|
||||
single_read_en <= '0';
|
||||
single_read_reg_vld <= '0';
|
||||
end if;
|
||||
elsif bus_din_vld = '1' and single_read_en = '1' then
|
||||
single_read_reg <= bus_din;
|
||||
single_read_reg_vld <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_din,
|
||||
din_b => tag_ram_din,
|
||||
dout_a => tag_ram_dout_inv,
|
||||
dout_b => tag_ram_dout
|
||||
);
|
||||
|
||||
gen_data_ram:
|
||||
for i in 0 to 3 generate
|
||||
begin
|
||||
|
||||
inst_data_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => lg2(CACHE_SIZE),
|
||||
data_width => word_t'length/4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => data_ram_we(i),
|
||||
we_b => ctrl_data_ram_we(i),
|
||||
addr_a => ctrl_data_ram_addr,
|
||||
addr_b => data_ram_addr,
|
||||
din_a => din_reg(8*(i+1)-1 downto 8*i),
|
||||
din_b => bus_din(8*(i+1)-1 downto 8*i),
|
||||
dout_a => open,
|
||||
dout_b => data_ram_dout(8*(i+1)-1 downto 8*i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
cache_invalidate_request:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or ctrl_in.inv_all = '1' or ctrl_in.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl_in.inv_all or rst;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cache_ctrl_state <= init;
|
||||
cache_busy_state <= init;
|
||||
else
|
||||
cache_ctrl_state <= cache_ctrl_state_next;
|
||||
cache_busy_state <= cache_busy_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_rdy <= read_rdy and not instant_raw and write_rdy;
|
||||
write_rdy <= not (write_fifo_full and cache_req_wr);
|
||||
query_out.rdy <= cache_rdy;
|
||||
rdy <= cache_rdy;
|
||||
|
||||
cache_dout <= single_read_reg when single_read_en = '1' else to_mips_01(data_ram_dout);
|
||||
query_out.data <= cache_dout;
|
||||
|
||||
-- tag_match <= '1' when to_tag(request_pa) = cache_entry_out.tag else '0';
|
||||
tag_match <= '1' when ((to_tag(request_pa) xor cache_entry_out.tag) = (tag_width-1 downto 0 => '0')) else '0';
|
||||
cache_hit <= tag_match and cache_entry_out.valid;
|
||||
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid;
|
||||
|
||||
tag_ram_din <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else to_cache_index(request_va);
|
||||
tag_ram_addr_rd <= to_cache_index(query_in.addr) when (was_miss = '0' and instant_raw = '0') else to_cache_index(request_va);
|
||||
|
||||
cache_entry_out <= to_dcache_entry(to_mips_01(tag_ram_dout));
|
||||
cache_entry_out_inv <= to_dcache_entry(to_mips_01(tag_ram_dout_inv));
|
||||
|
||||
ram_read_en <= query_in.en or was_miss or fill_count_en;
|
||||
data_ram_addr <= (to_cache_index(query_in.addr) & to_word_index(query_in.addr)) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (to_cache_index(request_va) & fill_word_index);
|
||||
ctrl_data_ram_addr <= to_cache_index(request_va) & fill_word_index;
|
||||
ctrl_data_ram_we <= (others => ram_write_en and bus_din_vld);
|
||||
data_ram_we <= be_reg when (write_hit = '1') else (others => '0');
|
||||
|
||||
write_through_en <= cache_rdy and cache_req_wr; -- and tlb_query_in.hit and not tlb_query_in.flags.D;
|
||||
|
||||
cache_busy_state_fsm:
|
||||
process(cache_busy_state, request_nc, cache_req_rd, cache_hit, mem_fetch_ack, single_read_en, single_read_reg_vld)
|
||||
begin
|
||||
|
||||
read_rdy <= '0';
|
||||
mem_fetch_req <= '0';
|
||||
single_read_set <= '0';
|
||||
cache_busy_state_next <= cache_busy_state;
|
||||
|
||||
case cache_busy_state is
|
||||
|
||||
when init =>
|
||||
cache_busy_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if single_read_en = '1' then
|
||||
read_rdy <= single_read_reg_vld;
|
||||
else
|
||||
read_rdy <= '1';
|
||||
if cache_req_rd = '1' then
|
||||
-- if tlb_query_in.exc = '0' then
|
||||
if request_nc = '1' or cache_hit = '0' then
|
||||
-- mem_fetch_req <= '1';
|
||||
read_rdy <= '0';
|
||||
cache_busy_state_next <= busy;
|
||||
end if;
|
||||
-- end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when busy =>
|
||||
mem_fetch_req <= '1';
|
||||
if mem_fetch_ack = '1' then
|
||||
single_read_set <= request_nc;
|
||||
cache_busy_state_next <= ready;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
cache_busy_state_next <= ready;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
cache_ctrl_state_fsm:
|
||||
process(cache_ctrl_state, mem_fetch_req, request_nc, flush_count_rdy, fill_count_rdy, request_count_rdy, request_pa, bus_cmd_rdy, bus_din_vld, invalidate_req, invalidate_all, write_through_en, write_data_avail)
|
||||
begin
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
ram_write_en <= '0';
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
mem_fetch_ack <= '0';
|
||||
read_write_buffer <= '0';
|
||||
|
||||
cache_entry_in.tag <= to_tag(request_pa);
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_ctrl_state_next <= cache_ctrl_state;
|
||||
|
||||
case cache_ctrl_state is
|
||||
|
||||
when init =>
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
cache_ctrl_state_next <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
elsif mem_fetch_req = '1' or write_data_avail = '1' then
|
||||
cache_ctrl_state_next <= bus_request;
|
||||
-- bus_cmd_cycle_en <= '1';
|
||||
elsif write_through_en = '1' then
|
||||
cache_ctrl_state_next <= wait_write_thru;
|
||||
-- bus_cmd_cycle_en <= '1';
|
||||
end if;
|
||||
|
||||
when invalidate =>
|
||||
cache_ctrl_state_next <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
cache_ctrl_state_next <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_hit_inv = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
cache_ctrl_state_next <= invalidate_post;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
cache_ctrl_state_next <= invalidate_post;
|
||||
end if;
|
||||
|
||||
when invalidate_post =>
|
||||
was_miss <= '1';
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when wait_write_thru =>
|
||||
cache_ctrl_state_next <= bus_request;
|
||||
bus_cmd_cycle_en <= '1';
|
||||
|
||||
when bus_request =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
if bus_cmd_rdy = '1' then
|
||||
if write_data_avail = '1' then
|
||||
read_write_buffer <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
elsif mem_fetch_req = '1' then
|
||||
if request_nc = '1' then
|
||||
cache_ctrl_state_next <= mem_read_single;
|
||||
else
|
||||
cache_ctrl_state_next <= mem_read;
|
||||
end if;
|
||||
else
|
||||
cache_ctrl_state_next <= ready;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when mem_read =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
request_count_en <= '1';
|
||||
ram_write_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
bus_cmd_we <= '0';
|
||||
cache_ctrl_state_next <= mem_read_data;
|
||||
end if;
|
||||
|
||||
when mem_read_single =>
|
||||
mem_fetch_ack <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
cache_ctrl_state_next <= mem_read_data_single;
|
||||
|
||||
when mem_read_data =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
ram_write_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
cache_ctrl_state_next <= rd_cache;
|
||||
end if;
|
||||
|
||||
when mem_read_data_single =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
if bus_din_vld = '1' then
|
||||
cache_ctrl_state_next <= ready;
|
||||
end if;
|
||||
|
||||
when rd_cache =>
|
||||
mem_fetch_ack <= '1';
|
||||
was_miss <= '1';
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when others =>
|
||||
cache_ctrl_state_next <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if ctrl_in.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if bus_cmd_rdy = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if bus_din_vld = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -0,0 +1,663 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.mips_types.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY icache IS
|
||||
Generic
|
||||
(
|
||||
CACHE_SIZE : natural := 1024; -- words
|
||||
LINE_SIZE : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
rdy : out STD_LOGIC;
|
||||
|
||||
-- CPU control/data
|
||||
query_in : in icache_query_in_t;
|
||||
query_out : out icache_query_out_t;
|
||||
|
||||
-- Cache control
|
||||
ctrl_in : in cache_ctrl_t;
|
||||
|
||||
-- busmaster data
|
||||
bus_din : in word_t;
|
||||
bus_din_rdy : out std_logic;
|
||||
bus_din_vld : in std_logic;
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
bus_cmd_cycle_en : out std_logic;
|
||||
bus_cmd_out : out bm_cmd_t;
|
||||
bus_cyc_complete : in std_logic
|
||||
);
|
||||
END icache;
|
||||
|
||||
ARCHITECTURE behavior OF icache IS
|
||||
|
||||
COMPONENT dpram_1w1r2c_ra
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT (
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dpram_2w2r2c_ra is
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(LINE_SIZE);
|
||||
constant cache_index_width : natural := lg2(CACHE_SIZE) - word_index_width;
|
||||
constant tag_width : natural := addr_width - lg2(CACHE_SIZE) - 2;
|
||||
constant tag_ram_data_width : natural := 1 + tag_width + lg2(TLB_NUM_ENTRIES);
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
|
||||
subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
|
||||
|
||||
type icache_entry_t is record
|
||||
valid : std_logic;
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
tlb_idx : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
end record;
|
||||
|
||||
function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
|
||||
variable result : icache_entry_t;
|
||||
begin
|
||||
result.valid := x(0);
|
||||
result.tag := x(tag_width downto 1);
|
||||
result.tlb_idx := x(lg2(TLB_NUM_ENTRIES)+tag_width downto tag_width+1);
|
||||
|
||||
return result;
|
||||
end to_icache_entry;
|
||||
|
||||
function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is
|
||||
variable result : tag_ram_data_t;
|
||||
begin
|
||||
result(0) := x.valid;
|
||||
result(tag_width downto 1) := x.tag;
|
||||
result(lg2(TLB_NUM_ENTRIES)+tag_width downto tag_width+1) := x.tlb_idx;
|
||||
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
|
||||
function to_word_index(x : word_t) return unsigned is
|
||||
variable result : unsigned(word_index_width-1 downto 0);
|
||||
begin
|
||||
result := x(word_index_width+1 downto 2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_word_index;
|
||||
|
||||
|
||||
function to_cache_index(x : word_t) return unsigned is
|
||||
variable result : unsigned(cache_index_width-1 downto 0);
|
||||
begin
|
||||
result := x(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_cache_index;
|
||||
|
||||
function to_tag(x : word_t) return unsigned is
|
||||
variable result : unsigned(tag_width-1 downto 0);
|
||||
begin
|
||||
result := x(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
return result;
|
||||
|
||||
end to_tag;
|
||||
|
||||
type cache_busy_state_t is (init, ready, busy);
|
||||
signal cache_busy_state, cache_busy_state_next : cache_busy_state_t;
|
||||
|
||||
type cache_ctrl_state_t is (init, ready, invalidate, invalidate_post, flush, bus_request, mem_read, mem_read_single, mem_read_data, mem_read_data_single, rd_cache, upd_cache);
|
||||
signal cache_ctrl_state, cache_ctrl_state_next : cache_ctrl_state_t;
|
||||
|
||||
type debug_t is record
|
||||
ready : std_logic;
|
||||
req_strobe : std_logic;
|
||||
req_read : std_logic;
|
||||
req_va : word_t;
|
||||
req_pa : word_t;
|
||||
dout_reg : word_t;
|
||||
end record;
|
||||
|
||||
signal debug : debug_t;
|
||||
|
||||
signal req_strobe : std_logic;
|
||||
signal cache_req_rd : std_logic;
|
||||
signal read_rdy : std_logic;
|
||||
signal cache_rdy : std_logic;
|
||||
signal cache_hit : std_logic;
|
||||
signal request_va : word_t;
|
||||
signal request_pa : word_t;
|
||||
signal request_nc : std_logic;
|
||||
|
||||
signal tag_match : std_logic;
|
||||
signal cache_hit_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
|
||||
signal mem_fetch_req : std_logic;
|
||||
signal mem_fetch_ack : std_logic;
|
||||
signal single_read_en : std_logic;
|
||||
signal single_read_set : std_logic;
|
||||
signal single_read_reg_vld : std_logic;
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : icache_entry_t;
|
||||
signal cache_entry_out : icache_entry_t;
|
||||
signal cache_entry_out_inv : icache_entry_t;
|
||||
signal data_ram_addr_rd : unsigned(lg2(CACHE_SIZE)-1 downto 0);
|
||||
signal data_ram_data_rd : word_t;
|
||||
signal data_ram_addr_wr : unsigned(lg2(CACHE_SIZE)-1 downto 0);
|
||||
signal data_ram_data_wr : word_t;
|
||||
signal data_ram_we : std_logic;
|
||||
signal single_read_reg : word_t;
|
||||
signal cache_dout : word_t;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_rd : tag_ram_data_t;
|
||||
signal tag_ram_data_rd_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_wr : tag_ram_data_t;
|
||||
signal tag_ram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal ram_read_en : std_logic;
|
||||
signal ram_write_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
|
||||
signal fill_word_index : unsigned(word_index_width-1 downto 0);
|
||||
signal req_word_index : unsigned(word_index_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Print info
|
||||
assert false report "addr_width = " & natural'image(addr_width) & "." severity note;
|
||||
assert false report "tag_width = " & natural'image(tag_width) & "." severity note;
|
||||
assert false report "word_index_width = " & natural'image(word_index_width) & "." severity note;
|
||||
assert false report "cache_index_width = " & natural'image(cache_index_width) & "." severity note;
|
||||
|
||||
-- tlb_query_out.vld <= cache_req_rd;
|
||||
-- tlb_query_out.vaddr <= request_va;
|
||||
-- tlb_query_out.write <= '0';
|
||||
-- tlb_query_out.vld <= req_strobe;
|
||||
-- tlb_query_out.vaddr <= query_in.addr;
|
||||
-- tlb_query_out.write <= '0';
|
||||
|
||||
cache_index_inv <= ctrl_in.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl_in.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
request_pa <= request_va;
|
||||
|
||||
debug.req_strobe <= req_strobe;
|
||||
debug.req_read <= cache_req_rd;
|
||||
debug.req_va <= request_va;
|
||||
debug.req_pa <= request_pa;
|
||||
debug.dout_reg <= cache_dout;
|
||||
debug.ready <= cache_rdy;
|
||||
|
||||
-------------------------------------------------
|
||||
-- ctrl
|
||||
-------------------------------------------------
|
||||
req_strobe <= cache_rdy and query_in.en;
|
||||
|
||||
ctrl_request_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if cache_rdy = '1' then
|
||||
cache_req_rd <= query_in.en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------------
|
||||
fill_address_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
request_va <= (others => '0');
|
||||
request_nc <= '0';
|
||||
elsif req_strobe = '1' then
|
||||
request_va <= query_in.addr;
|
||||
request_nc <= query_in.nc;
|
||||
fill_word_index <= to_word_index(query_in.addr);
|
||||
elsif bus_din_vld = '1' and fill_count_en = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_request_address_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if req_strobe = '1' then
|
||||
req_word_index <= to_word_index(query_in.addr);
|
||||
elsif request_count_en = '1' and bus_cmd_rdy = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
single_read_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
single_read_en <= '0';
|
||||
single_read_reg_vld <= '0';
|
||||
elsif single_read_en = '0' then
|
||||
if single_read_set = '1' then
|
||||
single_read_en <= '1';
|
||||
end if;
|
||||
elsif single_read_reg_vld = '1' then
|
||||
if query_in.en = '1' then
|
||||
single_read_en <= '0';
|
||||
single_read_reg_vld <= '0';
|
||||
end if;
|
||||
elsif bus_din_vld = '1' and single_read_en = '1' then
|
||||
single_read_reg <= bus_din;
|
||||
single_read_reg_vld <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_invalidate_request:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or ctrl_in.inv_all = '1' or ctrl_in.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl_in.inv_all or rst;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_data_wr,
|
||||
din_b => tag_ram_data_wr,
|
||||
dout_a => tag_ram_data_rd_inv,
|
||||
dout_b => tag_ram_data_rd
|
||||
);
|
||||
|
||||
inst_data_ram : dpram_1w1r2c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => lg2(CACHE_SIZE),
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => clk,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
we_a => data_ram_we,
|
||||
addr_a => data_ram_addr_wr,
|
||||
addr_b => data_ram_addr_rd,
|
||||
din_a => data_ram_data_wr,
|
||||
dout_b => data_ram_data_rd
|
||||
);
|
||||
|
||||
cache_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cache_ctrl_state <= init;
|
||||
cache_busy_state <= init;
|
||||
else
|
||||
cache_ctrl_state <= cache_ctrl_state_next;
|
||||
cache_busy_state <= cache_busy_state_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_din_rdy <= fill_count_en or single_read_en;
|
||||
bus_cmd_out.addr <= to_tag(request_pa) & to_cache_index(request_pa) & req_word_index & "00";
|
||||
bus_cmd_out.rw <= '0';
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
|
||||
cache_rdy <= read_rdy;
|
||||
query_out.rdy <= cache_rdy;
|
||||
rdy <= cache_rdy;
|
||||
|
||||
cache_dout <= single_read_reg when single_read_en = '1' else data_ram_data_rd;
|
||||
query_out.data <= cache_dout;
|
||||
|
||||
cache_entry_out <= to_icache_entry(to_mips_01(tag_ram_data_rd));
|
||||
tag_match <= '1' when ((to_tag(request_pa) xor cache_entry_out.tag) = (tag_width-1 downto 0 => '0')) else '0';
|
||||
cache_hit <= tag_match and cache_entry_out.valid;
|
||||
|
||||
cache_entry_out_inv <= to_icache_entry(to_mips_01(tag_ram_data_rd_inv));
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid;
|
||||
|
||||
ram_read_en <= query_in.en or was_miss;
|
||||
tag_ram_data_wr <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else to_cache_index(request_va);
|
||||
tag_ram_addr_rd <= to_cache_index(query_in.addr) when was_miss = '0' else to_cache_index(request_va);
|
||||
data_ram_addr_rd <= (to_cache_index(query_in.addr) & to_word_index(query_in.addr)) when was_miss = '0' else (to_cache_index(request_va) & fill_word_index);
|
||||
data_ram_addr_wr <= to_cache_index(request_va) & fill_word_index;
|
||||
data_ram_data_wr <= bus_din;
|
||||
data_ram_we <= ram_write_en and bus_din_vld;
|
||||
|
||||
cache_busy_state_fsm:
|
||||
process(cache_busy_state, request_nc, cache_req_rd, cache_hit, mem_fetch_ack, single_read_en, single_read_reg_vld)
|
||||
begin
|
||||
|
||||
read_rdy <= '0';
|
||||
mem_fetch_req <= '0';
|
||||
single_read_set <= '0';
|
||||
cache_busy_state_next <= cache_busy_state;
|
||||
|
||||
case cache_busy_state is
|
||||
|
||||
when init =>
|
||||
cache_busy_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if single_read_en = '1' then
|
||||
read_rdy <= single_read_reg_vld;
|
||||
else
|
||||
read_rdy <= '1';
|
||||
if cache_req_rd = '1' then
|
||||
-- if tlb_query_in.exc = '0' then
|
||||
if request_nc = '1' or cache_hit = '0' then
|
||||
-- mem_fetch_req <= '1';
|
||||
read_rdy <= '0';
|
||||
single_read_set <= request_nc;
|
||||
cache_busy_state_next <= busy;
|
||||
end if;
|
||||
-- end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when busy =>
|
||||
mem_fetch_req <= '1';
|
||||
if mem_fetch_ack = '1' then
|
||||
cache_busy_state_next <= ready;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
cache_busy_state_next <= ready;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
cache_ctrl_state_fsm:
|
||||
process(cache_ctrl_state, mem_fetch_req, request_nc, bus_din_vld, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, request_pa, bus_cmd_rdy, invalidate_req, invalidate_all)
|
||||
begin
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
ram_write_en <= '0';
|
||||
bus_cmd_cycle_en <= '0';
|
||||
bus_cmd_we <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
mem_fetch_ack <= '0';
|
||||
|
||||
cache_entry_in.tag <= to_tag(request_pa);
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_ctrl_state_next <= cache_ctrl_state;
|
||||
|
||||
case cache_ctrl_state is
|
||||
|
||||
when init =>
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
cache_ctrl_state_next <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
elsif mem_fetch_req = '1' then
|
||||
cache_ctrl_state_next <= bus_request;
|
||||
bus_cmd_cycle_en <= '1';
|
||||
end if;
|
||||
|
||||
when invalidate =>
|
||||
cache_ctrl_state_next <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
cache_ctrl_state_next <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_hit_inv = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
cache_ctrl_state_next <= invalidate_post;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
cache_ctrl_state_next <= invalidate_post;
|
||||
end if;
|
||||
|
||||
when invalidate_post =>
|
||||
was_miss <= '1';
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when bus_request =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
if bus_cmd_rdy = '1' then
|
||||
cache_ctrl_state_next <= mem_read;
|
||||
if request_nc = '1' then
|
||||
cache_ctrl_state_next <= mem_read_single;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when mem_read =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
request_count_en <= '1';
|
||||
ram_write_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
bus_cmd_we <= '0';
|
||||
cache_ctrl_state_next <= mem_read_data;
|
||||
end if;
|
||||
|
||||
when mem_read_single =>
|
||||
mem_fetch_ack <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
cache_ctrl_state_next <= mem_read_data_single;
|
||||
|
||||
when mem_read_data =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
ram_write_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
cache_ctrl_state_next <= rd_cache;
|
||||
end if;
|
||||
|
||||
when mem_read_data_single =>
|
||||
bus_cmd_cycle_en <= '1';
|
||||
if bus_din_vld = '1' then
|
||||
cache_ctrl_state_next <= ready;
|
||||
end if;
|
||||
|
||||
when rd_cache =>
|
||||
mem_fetch_ack <= '1';
|
||||
was_miss <= '1';
|
||||
cache_ctrl_state_next <= ready;
|
||||
|
||||
when others =>
|
||||
cache_ctrl_state_next <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if ctrl_in.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if bus_cmd_rdy = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if bus_din_vld = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -27,32 +27,30 @@ use IEEE.numeric_std.ALL;
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_instr.all;
|
||||
use work.mips_util_pkg.all;
|
||||
|
||||
entity pipeline is
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
imem_en : out STD_LOGIC;
|
||||
imem_addr : out word_t;
|
||||
imem_data : in word_t;
|
||||
dmem_err : in STD_LOGIC;
|
||||
dmem_rdy : in STD_LOGIC;
|
||||
dmem_en : out STD_LOGIC;
|
||||
dmem_we : out STD_LOGIC;
|
||||
dmem_be : out unsigned(3 downto 0);
|
||||
dmem_addr : out word_t;
|
||||
dmem_din : in word_t;
|
||||
dmem_dout : out word_t;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
c0_ctrl_out : out cop0_ctrl_in_t;
|
||||
c0_ctrl_in : in cop0_ctrl_out_t
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
imem_err : in STD_LOGIC;
|
||||
dmem_err : in STD_LOGIC;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
ctrl_out : out pipe_ctrl_out_t;
|
||||
ctrl_in : in pipe_ctrl_in_t;
|
||||
dtlb_qry_out : out tlb_query_in_t;
|
||||
dtlb_qry_in : in tlb_query_out_t;
|
||||
dcache_qry_out : out dcache_query_in_t;
|
||||
dcache_qry_in : in dcache_query_out_t;
|
||||
itlb_qry_out : out tlb_query_in_t;
|
||||
itlb_qry_in : in tlb_query_out_t;
|
||||
icache_qry_out : out icache_query_in_t;
|
||||
icache_qry_in : in icache_query_out_t
|
||||
|
||||
);
|
||||
end pipeline;
|
||||
@@ -161,18 +159,14 @@ architecture Behavioral of pipeline is
|
||||
signal EX_events_instr : event_t;
|
||||
signal EX_events_alu : event_t;
|
||||
signal EX_events_mem : event_t;
|
||||
signal EX_events_DTLB : event_t;
|
||||
signal EX_events : event_t;
|
||||
signal MEM_events : event_t;
|
||||
signal bcu_op_a : word_t;
|
||||
signal bcu_op_b : word_t;
|
||||
signal bcu_flags : bcu_flags_t;
|
||||
signal vaddr : word_t;
|
||||
signal dmem_src : word_t;
|
||||
signal stage_rst : unsigned(3 downto 0);
|
||||
signal pipe_rst : STD_LOGIC;
|
||||
|
||||
signal pc : pc_t;
|
||||
|
||||
signal pc : pc_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
@@ -181,38 +175,49 @@ begin
|
||||
cpu_run <= ce;
|
||||
|
||||
-- Stall Detection Unit ---------------------------------------------------
|
||||
sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc;
|
||||
sdu.ID_nop <= sdu.imem_dep or ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc; -- or pc.branch_not_taken;
|
||||
sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc;
|
||||
sdu.MEM_nop <= EX_stage.nop or EX_stage.exc;
|
||||
sdu.WB_nop <= sdu.dmem_dep or MEM_stage.nop;
|
||||
sdu.WB_nop <= sdu.dmem_dep or MEM_stage.exc or WB_stage.exc or ctrl_in.exc_pending;
|
||||
|
||||
sdu.stall_all <= sdu.dmem_dep;
|
||||
sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit;
|
||||
sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or ctrl_in.exc_exit;
|
||||
sdu.EX_stall <= sdu.stall_all;
|
||||
sdu.MEM_stall <= sdu.stall_all;
|
||||
sdu.WB_stall <= '0';
|
||||
|
||||
sdu.mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
|
||||
sdu.imem_dep <= not imem_rdy;
|
||||
sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
|
||||
sdu.imem_dep <= not icache_qry_in.rdy;
|
||||
sdu.dmem_dep <= not dcache_qry_in.rdy and MEM_stage.ctrl.dmem_en;
|
||||
---------------------------------------------------------------------------
|
||||
imem_en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
|
||||
itlb_qry_out.vld <= (not sdu.ID_stall or ctrl_in.exc_inject);
|
||||
itlb_qry_out.write <= '0';
|
||||
itlb_qry_out.vaddr <= pc.nxt;
|
||||
|
||||
icache_qry_out.addr <= itlb_qry_in.paddr;
|
||||
icache_qry_out.en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or ctrl_in.exc_commit);
|
||||
icache_qry_out.nc <= itlb_qry_in.flags.N;
|
||||
|
||||
dtlb_qry_out.vld <= ID_stage.ctrl.dmem_en and not sdu.dmem_dep;
|
||||
dtlb_qry_out.write <= ID_stage.ctrl.dmem_we;
|
||||
dtlb_qry_out.vaddr <= ID_stage.va;
|
||||
|
||||
dcache_qry_out.be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
|
||||
dcache_qry_out.en <= EX_stage.dmem_en;
|
||||
dcache_qry_out.we <= EX_stage.ctrl.dmem_we;
|
||||
dcache_qry_out.data <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||
dcache_qry_out.addr <= dtlb_qry_in.paddr;
|
||||
dcache_qry_out.nc <= dtlb_qry_in.flags.N;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Coprocessor assignments
|
||||
--------------------------------------------------------------------------
|
||||
c0_ctrl_out.bd_wb <= WB_stage.bd;
|
||||
c0_ctrl_out.epc_mem <= MEM_stage.pcn;
|
||||
c0_ctrl_out.epc_wb <= MEM_stage.epc;
|
||||
c0_ctrl_out.imem_addr <= EX_stage.epc;
|
||||
c0_ctrl_out.dmem_addr <= MEM_stage.va;
|
||||
c0_ctrl_out.sdu <= sdu;
|
||||
c0_ctrl_out.events <= WB_stage.events;
|
||||
c0_ctrl_out.exc_req <= MEM_stage.exc;
|
||||
c0_ctrl_out.exc_ack <= WB_stage.exc;
|
||||
ctrl_out.sdu <= sdu;
|
||||
ctrl_out.exc_req <= WB_stage.exc and not WB_stage.exc_last;
|
||||
ctrl_out.exc_ack <= '1';
|
||||
cop_ir <= ID_stage.IR;
|
||||
cop_ir_en <= ID_stage.ctrl.cop_instr_en;
|
||||
cop_dout <= dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result;
|
||||
cop_dout <= EX_stage.reg_b;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Muldiv
|
||||
@@ -236,7 +241,6 @@ inst_muldiv: muldiv
|
||||
--------------------------------------------------------------------------
|
||||
-- IF stage
|
||||
--------------------------------------------------------------------------
|
||||
imem_addr <= pc.curr;
|
||||
|
||||
pipe_rst <= stage_rst(0);
|
||||
|
||||
@@ -252,80 +256,168 @@ proc_stage_reset:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc:
|
||||
process(pc)
|
||||
--------------------------------------------------------------------------
|
||||
-- pc
|
||||
--------------------------------------------------------------------------
|
||||
inst_bcu_alt_ID: bcu
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
op1_in => ID_stage.reg_a,
|
||||
op2_in => ID_stage.reg_b,
|
||||
flags => ID_stage.bcu_flags
|
||||
);
|
||||
|
||||
inst_bcu_alt_EX: bcu
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
op1_in => EX_stage.reg_a,
|
||||
op2_in => EX_stage.reg_b,
|
||||
flags => EX_stage.bcu_flags
|
||||
);
|
||||
|
||||
|
||||
proc_stage_branch_alt:
|
||||
process(ID_stage)
|
||||
begin
|
||||
if pc.branch_take = '1' then
|
||||
pc.curr <= pc.pc_branch after 2 ns;
|
||||
else
|
||||
pc.curr <= pc.nxt after 2 ns;
|
||||
pc.branch_take <= '0';
|
||||
if ID_stage.ctrl.branch = '1' then
|
||||
|
||||
case ID_stage.ctrl.bc_src is
|
||||
|
||||
when bc_eq_ne =>
|
||||
pc.branch_take <= ID_stage.ctrl.bc_not xor ID_stage.bcu_flags.eq;
|
||||
|
||||
when bc_lez_gtz =>
|
||||
pc.branch_take <= ID_stage.ctrl.bc_not xor (ID_stage.bcu_flags.eq or ID_stage.bcu_flags.ltz);
|
||||
|
||||
when bc_ltz_gez =>
|
||||
pc.branch_take <= ID_stage.ctrl.bc_not xor ID_stage.bcu_flags.ltz;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc_branch:
|
||||
process(clk_1)
|
||||
proc_stage_branch_not:
|
||||
process(EX_stage)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if sdu.ID_stall = '0' then
|
||||
EX_stage.branch_not_taken <= '0';
|
||||
|
||||
case EX_stage.ctrl.bc_src is
|
||||
|
||||
when bc_eq_ne =>
|
||||
EX_stage.branch_not_taken <= EX_stage.ctrl.branch and not(EX_stage.ctrl.bc_not xor EX_stage.bcu_flags.eq);
|
||||
|
||||
when bc_lez_gtz =>
|
||||
EX_stage.branch_not_taken <= EX_stage.ctrl.branch and not(EX_stage.ctrl.bc_not xor (EX_stage.bcu_flags.eq or EX_stage.bcu_flags.ltz));
|
||||
|
||||
when bc_ltz_gez =>
|
||||
EX_stage.branch_not_taken <= EX_stage.ctrl.branch and not(EX_stage.ctrl.bc_not xor EX_stage.bcu_flags.ltz);
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- proc_stage_pc_next_alt:
|
||||
process(ctrl_in, sdu, pc, ID_stage, EX_stage)
|
||||
begin
|
||||
-- pc.nxt <= ctrl_in.exc_vec;
|
||||
-- if ctrl_in.exc_inject = '0' then
|
||||
pc.nxt <= pc.plus4;
|
||||
if ID_stage.ctrl.jump = '1' then
|
||||
pc.nxt <= ID_stage.jimm32;
|
||||
elsif ID_stage.ctrl.jump_long = '1' then
|
||||
pc.nxt <= ID_stage.reg_a;
|
||||
elsif pc.branch_take = '1' then
|
||||
pc.nxt <= pc.pc_branch;
|
||||
end if;
|
||||
-- end if;
|
||||
end process;
|
||||
|
||||
-- always branch in ID and revert in EX
|
||||
-- proc_stage_pc_next_alt:
|
||||
-- process(ctrl_in, sdu, ID_stage, EX_stage, pc)
|
||||
-- begin
|
||||
-- if EX_stage.branch_not_taken = '1' then
|
||||
-- pc.nxt <= pc.pc_branch_revert;
|
||||
-- else
|
||||
-- pc.nxt <= pc.plus4;
|
||||
-- if ID_stage.ctrl.jump = '1' then
|
||||
-- pc.nxt <= ID_stage.jimm32;
|
||||
-- elsif ID_stage.ctrl.jump_long = '1' then
|
||||
-- pc.nxt <= ID_stage.reg_a;
|
||||
-- elsif ID_stage.ctrl.branch = '1' then -- always take branch
|
||||
-- pc.nxt <= pc.pc_branch;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
proc_stage_pc_plus_4_alt:
|
||||
process(clk_2)
|
||||
begin
|
||||
if rising_edge(clk_2) then
|
||||
if rst = '1' then
|
||||
pc.plus4 <= ctrl_in.exc_vec;
|
||||
elsif cpu_run = '1' then
|
||||
if ctrl_in.exc_inject = '1' then
|
||||
pc.plus4 <= ctrl_in.exc_vec;
|
||||
else
|
||||
pc.plus4 <= pc.curr + 4;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc_branch_alt:
|
||||
process(clk_2)
|
||||
begin
|
||||
if rising_edge(clk_2) then
|
||||
if cpu_run = '1' then
|
||||
pc.pc_branch <= pc.curr + ID_stage.bimm18;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_branch_ce:
|
||||
proc_stage_pc_curr_alt:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if pipe_rst = '1' then
|
||||
branch_ce <= '1';
|
||||
else
|
||||
branch_ce <= c0_ctrl_in.exc_pending;
|
||||
if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
|
||||
branch_ce <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if rst = '1' then
|
||||
pc.curr <= ctrl_in.exc_vec;
|
||||
pc.last <= ctrl_in.exc_vec;
|
||||
elsif cpu_run = '1' and (sdu.ID_stall = '0' or ctrl_in.exc_inject = '1') then
|
||||
pc.last <= pc.curr;
|
||||
pc.curr <= pc.nxt;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc_next:
|
||||
proc_stage_pc_revert_alt:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if c0_ctrl_in.exc_inject = '1' then
|
||||
pc.nxt <= c0_ctrl_in.exc_vec;
|
||||
elsif sdu.ID_stall = '0' then
|
||||
pc.last <= pc.curr;
|
||||
if ID_stage.ctrl.jump = '1' then
|
||||
pc.nxt <= ID_stage.jimm32;
|
||||
elsif ID_stage.ctrl.jump_long = '1' then
|
||||
pc.nxt <= ID_stage.reg_a;
|
||||
else
|
||||
pc.nxt <= pc.curr + 4;
|
||||
if cpu_run = '1' and (sdu.ID_stall = '0' or ctrl_in.exc_inject = '1') then
|
||||
if ID_stage.ctrl.branch = '1' then
|
||||
pc.pc_branch_revert <= pc.plus4;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_branch:
|
||||
process(clk_2)
|
||||
proc_stage_branch_not_taken_alt:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_2) and branch_ce = '1' then
|
||||
pc.branch_take <= '0';
|
||||
if EX_stage.ctrl.branch = '1' then
|
||||
|
||||
case EX_stage.ctrl.bc_src is
|
||||
|
||||
when bc_eq_ne =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
|
||||
|
||||
when bc_lez_gtz =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
|
||||
|
||||
when bc_ltz_gez =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
if rising_edge(clk_1) then
|
||||
if cpu_run = '1' and (sdu.ID_stall = '0' or ctrl_in.exc_inject = '1') then
|
||||
pc.branch_not_taken <= EX_stage.branch_not_taken;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
@@ -333,7 +425,7 @@ proc_stage_branch:
|
||||
--------------------------------------------------------------------------
|
||||
-- ID stage
|
||||
--------------------------------------------------------------------------
|
||||
ID_stage.IR <= to_01(imem_data);
|
||||
ID_stage.IR <= to_01(icache_qry_in.data);
|
||||
ID_stage.pcn <= pc.curr;
|
||||
ID_stage.op <= decode_op(ID_stage.IR);
|
||||
ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn);
|
||||
@@ -346,13 +438,25 @@ proc_stage_branch:
|
||||
ID_stage.epc <= pc.last;
|
||||
ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works
|
||||
ID_stage.nop <= sdu.ID_nop;
|
||||
ID_stage.va <= ID_stage.reg_a + extract_simm32(ID_stage.IR);
|
||||
|
||||
ID_stage_tlb_query_results:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
ID_stage.itlb_qry <= itlb_qry_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ID_except:
|
||||
process(ID_stage, c0_ctrl_in, pc)
|
||||
process(ID_stage, ctrl_in, pc)
|
||||
begin
|
||||
ID_stage.events <= events_clr;
|
||||
ID_stage.events.inst_load_err <= not c0_ctrl_in.exc_pending and (pc.nxt(1) or pc.nxt(0));
|
||||
ID_stage.events.inst_priv_addr <= not c0_ctrl_in.exc_pending and (pc.nxt(word_t'left) and c0_ctrl_in.user_mode);
|
||||
ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0));
|
||||
ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode);
|
||||
ID_stage.events.ITLB_LOAD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write;
|
||||
ID_stage.events.ITLB_STORE <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write;
|
||||
ID_stage.events.ITLB_MOD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty;
|
||||
end process;
|
||||
|
||||
proc_stage_hdu:
|
||||
@@ -366,12 +470,12 @@ proc_stage_hdu:
|
||||
|
||||
reg_ptr_a := ID_stage.reg_a_rptr;
|
||||
reg_ptr_b := ID_stage.reg_b_rptr;
|
||||
raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
|
||||
raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
|
||||
raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
|
||||
raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
|
||||
raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
|
||||
raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
|
||||
raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.reg_we = '1';
|
||||
raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.reg_we = '1';
|
||||
raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.reg_we = '1';
|
||||
raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.reg_we = '1';
|
||||
raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.reg_we = '1';
|
||||
raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.reg_we = '1';
|
||||
|
||||
hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns;
|
||||
hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns;
|
||||
@@ -390,18 +494,12 @@ proc_stage_fwd_a:
|
||||
if hdu.alu_fwd_a_ex then
|
||||
data := EX_stage.result;
|
||||
elsif hdu.alu_fwd_a_mem then
|
||||
data := MEM_stage.data;
|
||||
data := MEM_stage.result;
|
||||
elsif hdu.alu_fwd_a_wb then
|
||||
data := WB_stage.data;
|
||||
data := WB_stage.result;
|
||||
end if;
|
||||
|
||||
for i in 0 to 31 loop
|
||||
if data(i) = '1' then
|
||||
ID_stage.reg_a(i) <= '1' after 2 ns;
|
||||
else
|
||||
ID_stage.reg_a(i) <= '0' after 2 ns;
|
||||
end if;
|
||||
end loop;
|
||||
ID_stage.reg_a <= to_mips_01(data) after 1 ns;
|
||||
|
||||
end process;
|
||||
|
||||
@@ -413,18 +511,12 @@ proc_stage_fwd_b:
|
||||
if hdu.alu_fwd_b_ex then
|
||||
data := EX_stage.result;
|
||||
elsif hdu.alu_fwd_b_mem then
|
||||
data := MEM_stage.data;
|
||||
data := MEM_stage.result;
|
||||
elsif hdu.alu_fwd_b_wb then
|
||||
data := WB_stage.data;
|
||||
data := WB_stage.result;
|
||||
end if;
|
||||
|
||||
for i in 0 to 31 loop
|
||||
if data(i) = '1' then
|
||||
ID_stage.reg_b(i) <= '1' after 2 ns;
|
||||
else
|
||||
ID_stage.reg_b(i) <= '0' after 2 ns;
|
||||
end if;
|
||||
end loop;
|
||||
ID_stage.reg_b <= to_mips_01(data) after 1 ns;
|
||||
|
||||
end process;
|
||||
|
||||
@@ -449,7 +541,7 @@ proc_imm_mux:
|
||||
|
||||
end case;
|
||||
|
||||
ID_stage.imm <= data after 2 ns;
|
||||
ID_stage.imm <= data after 1 ns;
|
||||
|
||||
end process;
|
||||
|
||||
@@ -463,10 +555,10 @@ inst_reg_dual: reg_dual
|
||||
PORT MAP
|
||||
(
|
||||
clk_w => clk_1,
|
||||
we => WB_stage.wreg_we,
|
||||
we => WB_stage.reg_we,
|
||||
en => '1',
|
||||
wptr => WB_stage.reg_wptr,
|
||||
din => WB_stage.data,
|
||||
din => WB_stage.result,
|
||||
rptr_a => ID_stage.reg_a_rptr,
|
||||
rptr_b => ID_stage.reg_b_rptr,
|
||||
dout_a => reg_a,
|
||||
@@ -479,6 +571,7 @@ inst_reg_dual: reg_dual
|
||||
EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR);
|
||||
EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR);
|
||||
EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
|
||||
EX_stage.dtlb_qry <= dtlb_qry_in;
|
||||
|
||||
proc_stage_ID_EX_1:
|
||||
process(clk_1)
|
||||
@@ -493,18 +586,19 @@ proc_stage_ID_EX_1:
|
||||
EX_stage.pcn <= (others => '0');
|
||||
EX_stage.events_in <= events_clr;
|
||||
elsif sdu.EX_stall = '0' then
|
||||
EX_stage.nop <= sdu.EX_nop;
|
||||
EX_stage.op <= ID_stage.op;
|
||||
EX_stage.IR <= ID_stage.IR;
|
||||
EX_stage.va <= ID_stage.va;
|
||||
|
||||
EX_stage.reg_a <= ID_stage.reg_a;
|
||||
EX_stage.reg_b <= ID_stage.reg_b;
|
||||
EX_stage.events_in <= ID_stage.events;
|
||||
EX_stage.op <= ID_stage.op;
|
||||
EX_stage.ctrl <= ID_stage.ctrl;
|
||||
EX_stage.reg_write <= ID_stage.reg_write;
|
||||
EX_stage.nop <= sdu.EX_nop;
|
||||
EX_stage.IR <= ID_stage.IR;
|
||||
EX_stage.pcn <= ID_stage.pcn;
|
||||
EX_stage.epc <= ID_stage.epc;
|
||||
if sdu.EX_nop = '1' then
|
||||
EX_stage.op <= op_nop;
|
||||
EX_stage.IR <= (others => '0');
|
||||
EX_stage.ctrl <= ctrl_lines_default;
|
||||
EX_stage.reg_write <= '0';
|
||||
@@ -522,6 +616,15 @@ proc_stage_EX_instr_except:
|
||||
EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall;
|
||||
end process;
|
||||
|
||||
proc_stage_EX_DTLB_except:
|
||||
process(EX_stage)
|
||||
begin
|
||||
EX_events_DTLB <= events_clr;
|
||||
EX_events_DTLB.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write;
|
||||
EX_events_DTLB.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write;
|
||||
EX_events_DTLB.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty;
|
||||
end process;
|
||||
|
||||
proc_stage_EX_alu_except:
|
||||
process(EX_stage)
|
||||
begin
|
||||
@@ -536,30 +639,28 @@ proc_stage_EX_alu_except:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR);
|
||||
|
||||
proc_stage_EX_mem_except:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if pipe_rst = '1' then
|
||||
dmem_en <= '0';
|
||||
EX_stage.dmem_en <= '0';
|
||||
elsif sdu.EX_stall = '0' then
|
||||
EX_events_mem <= events_clr;
|
||||
dmem_en <= '0';
|
||||
EX_stage.dmem_en <= '0';
|
||||
if ID_stage.ctrl.dmem_en = '1' then
|
||||
dmem_en <= '1';
|
||||
EX_stage.dmem_en <= '1';
|
||||
if ID_stage.ctrl.except_en = '1' then
|
||||
if ID_stage.ctrl.word2_en = '1' then
|
||||
if vaddr(0) = '1' then
|
||||
if ID_stage.va(0) = '1' then
|
||||
EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we;
|
||||
EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we;
|
||||
dmem_en <= '0';
|
||||
EX_stage.dmem_en <= '0';
|
||||
end if;
|
||||
elsif vaddr(1 downto 0) /= "00" then
|
||||
elsif ID_stage.va(1 downto 0) /= "00" then
|
||||
EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we;
|
||||
EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we;
|
||||
dmem_en <= '0';
|
||||
EX_stage.dmem_en <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@@ -572,25 +673,19 @@ proc_stage_DMEM_ADDR:
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if sdu.EX_stall = '0' then
|
||||
EX_stage.va <= vaddr;
|
||||
if c0_ctrl_in.EB = '1' then
|
||||
if ctrl_in.EB = '1' then
|
||||
if ID_stage.ctrl.word2_en = '0' then
|
||||
EX_stage.pa_off <= not vaddr(1 downto 0);
|
||||
EX_stage.pa_off <= not ID_stage.va(1 downto 0);
|
||||
else
|
||||
EX_stage.pa_off <= not vaddr(1) & vaddr(0);
|
||||
EX_stage.pa_off <= not ID_stage.va(1) & ID_stage.va(0);
|
||||
end if;
|
||||
else
|
||||
EX_stage.pa_off <= vaddr(1 downto 0);
|
||||
EX_stage.pa_off <= ID_stage.va(1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b;
|
||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
|
||||
dmem_we <= EX_stage.ctrl.dmem_we;
|
||||
dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||
dmem_addr <= EX_stage.va;
|
||||
EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
|
||||
EX_stage.events <= EX_events_DTLB or EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
|
||||
EX_stage.exc <= event_is_active(EX_stage.events);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
@@ -608,9 +703,9 @@ proc_wptr_mux:
|
||||
reg_wptr := extract_rt(EX_stage.IR);
|
||||
end case;
|
||||
|
||||
EX_stage.wreg_we <= EX_stage.reg_write after 1 ns;
|
||||
EX_stage.reg_we <= EX_stage.reg_write after 1 ns;
|
||||
if reg_wptr = "00000" then
|
||||
EX_stage.wreg_we <= '0' after 1 ns;
|
||||
EX_stage.reg_we <= '0' after 1 ns;
|
||||
end if;
|
||||
|
||||
EX_stage.reg_wptr <= reg_wptr after 1 ns;
|
||||
@@ -620,7 +715,7 @@ proc_wptr_mux:
|
||||
|
||||
when wptr_src_const =>
|
||||
EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns;
|
||||
EX_stage.wreg_we <= '1' after 1 ns;
|
||||
EX_stage.reg_we <= '1' after 1 ns;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
@@ -628,14 +723,6 @@ proc_wptr_mux:
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_stage_bcu_op:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) and sdu.EX_stall = '0' then
|
||||
bcu_op_a <= ID_stage.reg_a;
|
||||
bcu_op_b <= ID_stage.reg_b;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
EX_stage.alu_op1 <= EX_stage.reg_a;
|
||||
|
||||
@@ -685,9 +772,9 @@ shifter_sa_mux:
|
||||
end case;
|
||||
data_inv := not data + 1;
|
||||
if ID_stage.ctrl.alu.shift_right = '0' then
|
||||
EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns;
|
||||
EX_stage.shift_ctrl.shamt_rnd <= data_inv after 1 ns;
|
||||
else
|
||||
EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns;
|
||||
EX_stage.shift_ctrl.shamt_rnd <= data after 1 ns;
|
||||
end if;
|
||||
EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns;
|
||||
EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right;
|
||||
@@ -724,18 +811,6 @@ inst_alu: alu
|
||||
flags => EX_stage.alu_flags
|
||||
);
|
||||
|
||||
inst_bcu: bcu
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
op1_in => bcu_op_a,
|
||||
op2_in => bcu_op_b,
|
||||
flags => bcu_flags
|
||||
);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- MEM stage
|
||||
--------------------------------------------------------------------------
|
||||
@@ -745,59 +820,61 @@ proc_stage_MEM_n:
|
||||
if rising_edge(clk_1) then
|
||||
if stage_rst(2) = '1' then
|
||||
MEM_stage.op <= op_nop;
|
||||
MEM_stage.wreg_we <= '0';
|
||||
MEM_stage.reg_we <= '0';
|
||||
MEM_stage.ctrl <= ctrl_lines_default;
|
||||
MEM_stage.pa_off <= (others => '0');
|
||||
MEM_stage.events_in <= events_clr;
|
||||
elsif sdu.MEM_stall = '0' then
|
||||
MEM_stage.events_in <= EX_stage.events;
|
||||
MEM_stage.nop <= sdu.MEM_nop;
|
||||
MEM_stage.reg_a <= EX_stage.reg_a;
|
||||
MEM_stage.reg_b <= EX_stage.reg_b;
|
||||
MEM_stage.result_in <= EX_stage.result;
|
||||
MEM_stage.op <= EX_stage.op;
|
||||
MEM_stage.wreg_we <= EX_stage.wreg_we;
|
||||
MEM_stage.epc <= EX_stage.epc;
|
||||
MEM_stage.pcn <= EX_stage.pcn;
|
||||
MEM_stage.events_in <= EX_stage.events;
|
||||
MEM_stage.reg_we <= EX_stage.reg_we;
|
||||
MEM_stage.ctrl <= EX_stage.ctrl;
|
||||
MEM_stage.branch_not_taken <= EX_stage.branch_not_taken;
|
||||
if EX_stage.ctrl.dmem_en = '1' then
|
||||
MEM_stage.va <= EX_stage.va;
|
||||
end if;
|
||||
MEM_stage.pa_off <= EX_stage.pa_off;
|
||||
MEM_stage.reg_wptr <= EX_stage.reg_wptr;
|
||||
MEM_stage.nop <= sdu.MEM_nop;
|
||||
if MEM_stage.reg_wptr = EX_stage.reg_wptr then
|
||||
if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
|
||||
MEM_stage.ex_result <= MEM_stage.data;
|
||||
MEM_stage.result_in <= MEM_stage.result;
|
||||
end if;
|
||||
else
|
||||
MEM_stage.ex_result <= EX_stage.reg_b;
|
||||
MEM_stage.result_in <= EX_stage.reg_b;
|
||||
end if;
|
||||
if EX_stage.ctrl.cop_instr_en = '1' then
|
||||
if EX_stage.ctrl.cop_read = '1' then
|
||||
MEM_stage.ex_result <= cop_din;
|
||||
MEM_stage.result_in <= cop_din;
|
||||
end if;
|
||||
elsif EX_stage.ctrl.dmem_en = '0' then
|
||||
MEM_stage.ex_result <= EX_stage.result;
|
||||
MEM_stage.result_in <= EX_stage.result;
|
||||
end if;
|
||||
if sdu.MEM_nop = '1' then
|
||||
MEM_stage.op <= op_nop;
|
||||
MEM_stage.wreg_we <= '0';
|
||||
MEM_stage.reg_we <= '0';
|
||||
MEM_stage.ctrl <= ctrl_lines_default;
|
||||
else
|
||||
MEM_stage.pcn <= EX_stage.pcn;
|
||||
MEM_stage.epc <= EX_stage.epc;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_MEM_mux:
|
||||
process(MEM_stage, dmem_din)
|
||||
process(MEM_stage, dcache_qry_in.data)
|
||||
variable temp1 : word_t;
|
||||
variable temp2 : word_t;
|
||||
variable data : word_t;
|
||||
variable be : unsigned(3 downto 0);
|
||||
begin
|
||||
data := MEM_stage.ex_result;
|
||||
data := MEM_stage.result_in;
|
||||
if MEM_stage.ctrl.reg_link = '1' then
|
||||
data := MEM_stage.epc + 8;
|
||||
elsif MEM_stage.ctrl.dmem_en = '1' then
|
||||
temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
|
||||
temp1 := load_shift(dcache_qry_in.data, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
|
||||
temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
|
||||
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
|
||||
if be(0) = '1' then
|
||||
@@ -813,16 +890,16 @@ proc_stage_MEM_mux:
|
||||
data(31 downto 24) := temp2(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
MEM_stage.data <= data after 1 ns;
|
||||
MEM_stage.result <= data after 1 ns;
|
||||
|
||||
end process;
|
||||
|
||||
proc_stage_MEM_except:
|
||||
process(MEM_stage, c0_ctrl_in)
|
||||
process(MEM_stage, ctrl_in)
|
||||
begin
|
||||
MEM_stage.events <= MEM_stage.events_in;
|
||||
MEM_stage.events.Int <= c0_ctrl_in.int;
|
||||
MEM_stage.events.NMI <= c0_ctrl_in.NMI;
|
||||
MEM_stage.events.Int <= ctrl_in.int;
|
||||
MEM_stage.events.NMI <= ctrl_in.NMI;
|
||||
end process;
|
||||
|
||||
MEM_stage.exc <= event_is_active(MEM_stage.events);
|
||||
@@ -832,33 +909,49 @@ proc_stage_MEM_except:
|
||||
--------------------------------------------------------------------------
|
||||
proc_stage_WB_p:
|
||||
process(clk_1)
|
||||
variable branch_delay : std_logic;
|
||||
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if stage_rst(3) = '1' then
|
||||
WB_stage.op <= op_nop;
|
||||
WB_stage.wreg_we <= '1';
|
||||
WB_stage.reg_we <= '1';
|
||||
WB_stage.reg_wptr <= (others => '0');
|
||||
WB_stage.data <= (others => '0');
|
||||
WB_stage.epc <= (others => '0');
|
||||
WB_stage.events <= events_clr;
|
||||
elsif sdu.WB_stall = '0' then
|
||||
WB_stage.op <= MEM_stage.op;
|
||||
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
||||
WB_stage.reg_wptr <= MEM_stage.reg_wptr;
|
||||
WB_stage.data <= MEM_stage.data;
|
||||
WB_stage.exc <= '0';
|
||||
elsif sdu.WB_stall = '0' then
|
||||
WB_stage.nop <= sdu.WB_nop;
|
||||
WB_stage.reg_a <= MEM_stage.reg_a;
|
||||
WB_stage.reg_b <= MEM_stage.reg_b;
|
||||
WB_stage.result <= MEM_stage.result;
|
||||
WB_stage.op <= MEM_stage.op;
|
||||
WB_stage.epc <= MEM_stage.epc;
|
||||
branch_delay := MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
|
||||
WB_stage.bd <= branch_delay;
|
||||
WB_stage.exc_last <= WB_stage.exc;
|
||||
WB_stage.exc <= MEM_stage.exc;
|
||||
WB_stage.reg_we <= MEM_stage.reg_we;
|
||||
WB_stage.reg_wptr <= MEM_stage.reg_wptr;
|
||||
WB_stage.events <= MEM_stage.events;
|
||||
if sdu.stall_all = '0' then
|
||||
WB_stage.exc <= MEM_stage.exc;
|
||||
if MEM_stage.exc = '1' then
|
||||
WB_stage.events <= MEM_stage.events;
|
||||
if MEM_stage.exc = '1' and WB_stage.exc = '0' then
|
||||
ctrl_out.dmem_addr <= MEM_stage.va;
|
||||
ctrl_out.imem_addr <= MEM_stage.epc;
|
||||
ctrl_out.epc_wb <= MEM_stage.epc;
|
||||
ctrl_out.bd_wb <= WB_stage.bd;
|
||||
ctrl_out.events <= MEM_stage.events;
|
||||
if WB_stage.bd = '1' then
|
||||
ctrl_out.epc_wb <= WB_stage.epc;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
WB_stage.nop <= sdu.WB_nop;
|
||||
if sdu.WB_nop = '1' then
|
||||
WB_stage.op <= op_nop;
|
||||
WB_stage.wreg_we <= '0';
|
||||
else
|
||||
WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
|
||||
WB_stage.reg_we <= '0';
|
||||
end if;
|
||||
if WB_stage.exc = '0' then
|
||||
WB_stage.va <= MEM_stage.va;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@@ -1,3 +1,26 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
@@ -48,16 +71,16 @@ ARCHITECTURE behavior OF tlb IS
|
||||
signal hit_umuc : STD_LOGIC;
|
||||
signal entry_lo_res : tlb_entry_lo_t;
|
||||
signal qry_res : tlb_query_out_t;
|
||||
signal stat_res : tlb_status_t;
|
||||
|
||||
signal pa : word_t;
|
||||
signal hit : STD_LOGIC;
|
||||
signal valid : STD_LOGIC;
|
||||
signal vld_r : STD_LOGIC;
|
||||
|
||||
signal cam_rdy : STD_LOGIC;
|
||||
signal cam_hit_vld : STD_LOGIC;
|
||||
|
||||
signal vaddr_reg : word_t;
|
||||
signal write_reg : STD_LOGIC;
|
||||
|
||||
subtype reg_lo_t is unsigned(23 downto 0);
|
||||
subtype reg_hi_t is unsigned(25 downto 0);
|
||||
@@ -151,22 +174,16 @@ begin
|
||||
clk_rd <= clk;
|
||||
rdy <= cam_rdy;
|
||||
|
||||
stat_res.exc_vld <= valid;
|
||||
stat_res.exc_miss <= not hit;
|
||||
stat_res.exc_dirty <= hit and qry_res.flags.D and query_in.write;
|
||||
stat_res.write <= query_in.write;
|
||||
|
||||
qry_res.paddr <= pa;
|
||||
qry_res.hit <= hit;
|
||||
qry_res.vld <= vld_r;
|
||||
qry_res.miss <= not hit;
|
||||
qry_res.dirty <= hit and qry_res.flags.D and write_reg;
|
||||
qry_res.write <= write_reg;
|
||||
qry_res.flags.N <= entry_lo_res.N;
|
||||
qry_res.flags.D <= entry_lo_res.D;
|
||||
qry_res.flags.V <= entry_lo_res.V;
|
||||
qry_res.exc <= stat_res.exc_miss or stat_res.exc_dirty;
|
||||
qry_res.vld <= valid;
|
||||
qry_res.idx <= (hit_umc or hit_umuc) & reg_qry_entry_lo_addr;
|
||||
qry_res.paddr <= pa;
|
||||
|
||||
query_out <= qry_res;
|
||||
ctrl_out.stat <= stat_res;
|
||||
|
||||
pa <= entry_lo_res.PFN & vaddr_reg(lg2(TLB_PAGE_SIZE)-1 downto 0);
|
||||
|
||||
@@ -180,6 +197,25 @@ begin
|
||||
ctrl_out.entry_hi <= to_entry_hi(to_mips_01(reg_ctrl_entry_hi_dout));
|
||||
reg_ctrl_entry_hi_din <= to_reg_hi(ctrl_in.entry_hi);
|
||||
|
||||
registered_ctrl_out:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if query_in.vld = '1' then
|
||||
vaddr_reg <= query_in.vaddr;
|
||||
write_reg <= query_in.write;
|
||||
end if;
|
||||
vld_r <= query_in.vld;
|
||||
if ce = '1' then
|
||||
if ctrl_in.entry_re = '1' then
|
||||
|
||||
ctrl_out.entry_lo <= to_entry_lo(to_mips_01(reg_ctrl_entry_lo_dout));
|
||||
ctrl_out.entry_vld <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_reg_entry_lo: entity work.reg_dual
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -243,34 +279,9 @@ inst_cam_va: entity work.cam
|
||||
|
||||
);
|
||||
|
||||
proc_entry_lo_umc:
|
||||
process(clk)
|
||||
variable index : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if query_in.vld = '1' then
|
||||
hit_umc <= '0';
|
||||
if query_in.vaddr(31 downto 29) = "100" then -- 80000000 to 9FFFFFFF
|
||||
hit_umc <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_entry_lo_umuc:
|
||||
process(clk)
|
||||
variable index : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if query_in.vld = '1' then
|
||||
hit_umuc <= '0';
|
||||
if query_in.vaddr(31 downto 29) = "101" then -- A0000000 to BFFFFFFF
|
||||
hit_umuc <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
hit_umc <= '1' when vaddr_reg(31 downto 29) = "100" else '0';
|
||||
hit_umuc <= '1' when vaddr_reg(31 downto 29) = "101" else '0';
|
||||
|
||||
tlb_entry_lo_result_translate:
|
||||
if USE_TLB = true generate
|
||||
tlb_entry_lo_result:
|
||||
@@ -326,25 +337,5 @@ if USE_TLB = false generate
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
registered_output:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if query_in.vld = '1' then
|
||||
vaddr_reg <= query_in.vaddr;
|
||||
end if;
|
||||
valid <= query_in.vld;
|
||||
if ce = '1' then
|
||||
if ctrl_in.entry_re = '1' then
|
||||
|
||||
ctrl_out.entry_lo <= to_entry_lo(to_mips_01(reg_ctrl_entry_lo_dout));
|
||||
ctrl_out.entry_vld <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------
|
||||
end behavior;
|
||||
|
||||
+167
-112
@@ -31,10 +31,12 @@ use work.mips_types.all;
|
||||
entity mips_top is
|
||||
Generic
|
||||
(
|
||||
icache_size : natural := 8192; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 4096; -- words
|
||||
dcache_line : natural := 8 -- words
|
||||
icache_size : natural := 8192; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 4096; -- words
|
||||
dcache_line : natural := 8; -- words
|
||||
WITH_TLB : boolean := true;
|
||||
TRANSLATE_KSEG0_1 : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
@@ -67,44 +69,32 @@ architecture rtl of mips_top is
|
||||
COMPONENT pipeline is
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
imem_en : out STD_LOGIC;
|
||||
imem_addr : out word_t;
|
||||
imem_data : in word_t;
|
||||
dmem_err : in STD_LOGIC;
|
||||
dmem_rdy : in STD_LOGIC;
|
||||
dmem_en : out STD_LOGIC;
|
||||
dmem_we : out STD_LOGIC;
|
||||
dmem_be : out unsigned(3 downto 0);
|
||||
dmem_addr : out word_t;
|
||||
dmem_din : in word_t;
|
||||
dmem_dout : out word_t;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
c0_ctrl_out : out cop0_ctrl_in_t;
|
||||
c0_ctrl_in : in cop0_ctrl_out_t
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
imem_err : in STD_LOGIC;
|
||||
dmem_err : in STD_LOGIC;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
ctrl_out : out pipe_ctrl_out_t;
|
||||
ctrl_in : in pipe_ctrl_in_t;
|
||||
dtlb_qry_out : out tlb_query_in_t;
|
||||
dtlb_qry_in : in tlb_query_out_t;
|
||||
dcache_qry_out : out dcache_query_in_t;
|
||||
dcache_qry_in : in dcache_query_out_t;
|
||||
itlb_qry_out : out tlb_query_in_t;
|
||||
itlb_qry_in : in tlb_query_out_t;
|
||||
icache_qry_out : out icache_query_in_t;
|
||||
icache_qry_in : in icache_query_out_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal imem_err : std_logic;
|
||||
signal imem_rdy : std_logic;
|
||||
signal imem_en : std_logic;
|
||||
signal imem_addr : word_t;
|
||||
signal imem_din : word_t;
|
||||
signal dmem_err : std_logic;
|
||||
signal dmem_rdy : std_logic;
|
||||
signal dmem_en : std_logic;
|
||||
signal dmem_we : std_logic;
|
||||
signal dmem_addr : word_t;
|
||||
signal dmem_dout : word_t;
|
||||
signal dmem_din : word_t;
|
||||
signal dmem_be : unsigned(3 downto 0);
|
||||
|
||||
signal biu_busy : STD_LOGIC;
|
||||
signal biu_rst : STD_LOGIC;
|
||||
signal cpu_rst : STD_LOGIC;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
@@ -113,8 +103,14 @@ architecture rtl of mips_top is
|
||||
signal pipe_cop_ir_en : STD_LOGIC;
|
||||
signal pipe_cop_din : word_t;
|
||||
signal pipe_cop_dout : word_t;
|
||||
signal pipe_c0_ctrl_out : cop0_ctrl_in_t;
|
||||
signal pipe_c0_ctrl_in : cop0_ctrl_out_t;
|
||||
signal pipe_ctrl_in : pipe_ctrl_in_t;
|
||||
signal pipe_ctrl_out : pipe_ctrl_out_t;
|
||||
|
||||
signal cop0_ctrl_in : cop0_ctrl_in_t;
|
||||
signal cop0_ctrl_out : cop0_ctrl_out_t;
|
||||
|
||||
signal biu_ctrl_in : biu_ctrl_in_t;
|
||||
signal biu_ctrl_out : biu_ctrl_out_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Coprocessor
|
||||
@@ -149,53 +145,48 @@ architecture rtl of mips_top is
|
||||
COMPONENT biu
|
||||
GENERIC
|
||||
(
|
||||
icache_size : natural;
|
||||
icache_line : natural;
|
||||
dcache_size : natural;
|
||||
dcache_line : natural
|
||||
icache_size : natural;
|
||||
icache_line : natural;
|
||||
dcache_size : natural;
|
||||
dcache_line : natural;
|
||||
WRITE_FIFO_SIZE : natural;
|
||||
WITH_TLB : boolean;
|
||||
TRANSLATE_KSEG0_1 : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
busy : out STD_LOGIC;
|
||||
|
||||
imem_err : out STD_LOGIC;
|
||||
dmem_err : out STD_LOGIC;
|
||||
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
MDAT_I : in unsigned(31 downto 0);
|
||||
MDAT_O : out unsigned(31 downto 0);
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
cop0_ctrl_in : in cop0_ctrl_out_t;
|
||||
cpu_clk : in STD_LOGIC;
|
||||
cpu_imem_err : out STD_LOGIC;
|
||||
cpu_imem_rdy : out STD_LOGIC;
|
||||
cpu_imem_en : in STD_LOGIC;
|
||||
cpu_imem_addr : in word_t;
|
||||
cpu_imem_din : out word_t;
|
||||
cpu_dmem_err : out STD_LOGIC;
|
||||
cpu_dmem_rdy : out STD_LOGIC;
|
||||
cpu_dmem_en : in STD_LOGIC;
|
||||
cpu_dmem_we : in STD_LOGIC;
|
||||
cpu_dmem_be : in unsigned(3 downto 0);
|
||||
cpu_dmem_dout : in word_t;
|
||||
cpu_dmem_din : out word_t;
|
||||
cpu_dmem_addr : in word_t
|
||||
|
||||
ctrl_in : in biu_ctrl_in_t;
|
||||
ctrl_out : out biu_ctrl_out_t
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------------
|
||||
debug.imem_err <= imem_err;
|
||||
debug.dmem_err <= dmem_err;
|
||||
|
||||
process(CLK_I)
|
||||
process(cpu_clk)
|
||||
variable reset_delay : unsigned (31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if rising_edge(cpu_clk) then
|
||||
if RST_I = '1' then
|
||||
reset_delay := (others => '0');
|
||||
biu_rst <= '1';
|
||||
@@ -209,7 +200,7 @@ begin
|
||||
if reset_delay(31) = '1' then
|
||||
cpu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(16) = '1' then
|
||||
if reset_delay(16) = '1' and biu_busy = '0' then
|
||||
cpu_run <= '1';
|
||||
end if;
|
||||
end if;
|
||||
@@ -219,30 +210,29 @@ begin
|
||||
inst_pipeline: pipeline
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
clk => cpu_clk,
|
||||
ce => cpu_run,
|
||||
imem_err => imem_err,
|
||||
imem_rdy => imem_rdy,
|
||||
imem_en => imem_en,
|
||||
imem_addr => imem_addr,
|
||||
imem_data => imem_din,
|
||||
dmem_err => dmem_err,
|
||||
dmem_rdy => dmem_rdy,
|
||||
dmem_en => dmem_en,
|
||||
dmem_we => dmem_we,
|
||||
dmem_be => dmem_be,
|
||||
dmem_addr => dmem_addr,
|
||||
dmem_din => dmem_din,
|
||||
dmem_dout => dmem_dout,
|
||||
cop_ir => pipe_cop_ir,
|
||||
cop_ir_en => pipe_cop_ir_en,
|
||||
cop_din => pipe_cop_din,
|
||||
cop_dout => pipe_cop_dout,
|
||||
c0_ctrl_out => pipe_c0_ctrl_out,
|
||||
c0_ctrl_in => pipe_c0_ctrl_in
|
||||
rst => cpu_rst,
|
||||
clk => cpu_clk,
|
||||
ce => cpu_run,
|
||||
imem_err => imem_err,
|
||||
dmem_err => dmem_err,
|
||||
cop_ir => pipe_cop_ir,
|
||||
cop_ir_en => pipe_cop_ir_en,
|
||||
cop_din => pipe_cop_din,
|
||||
cop_dout => pipe_cop_dout,
|
||||
ctrl_out => pipe_ctrl_out,
|
||||
ctrl_in => pipe_ctrl_in,
|
||||
dtlb_qry_out => biu_ctrl_in.dtlb_qry,
|
||||
dtlb_qry_in => biu_ctrl_out.dtlb_qry,
|
||||
dcache_qry_out => biu_ctrl_in.dcache_qry,
|
||||
dcache_qry_in => biu_ctrl_out.dcache_qry,
|
||||
itlb_qry_out => biu_ctrl_in.itlb_qry,
|
||||
itlb_qry_in => biu_ctrl_out.itlb_qry,
|
||||
icache_qry_out => biu_ctrl_in.icache_qry,
|
||||
icache_qry_in => biu_ctrl_out.icache_qry
|
||||
);
|
||||
|
||||
pipe_ctrl_in <= cop0_ctrl_out.pipe;
|
||||
|
||||
inst_cop: cop
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -260,49 +250,114 @@ inst_cop: cop
|
||||
int => INT,
|
||||
ir_en => pipe_cop_ir_en,
|
||||
ir => pipe_cop_ir,
|
||||
ctrl_in => pipe_c0_ctrl_out,
|
||||
ctrl_out => pipe_c0_ctrl_in,
|
||||
ctrl_in => cop0_ctrl_in,
|
||||
ctrl_out => cop0_ctrl_out,
|
||||
dout => pipe_cop_din,
|
||||
din => pipe_cop_dout
|
||||
);
|
||||
|
||||
|
||||
cop0_ctrl_in.pipe <= pipe_ctrl_out;
|
||||
cop0_ctrl_in.itlb_ctrl <= biu_ctrl_out.itlb_ctrl;
|
||||
cop0_ctrl_in.dtlb_ctrl <= biu_ctrl_out.dtlb_ctrl;
|
||||
|
||||
inst_biu: biu
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => icache_size, -- words
|
||||
icache_line => icache_line, -- words
|
||||
dcache_size => dcache_size, -- words
|
||||
dcache_line => dcache_line -- words
|
||||
icache_size => icache_size, -- words
|
||||
icache_line => icache_line, -- words
|
||||
dcache_size => dcache_size, -- words
|
||||
dcache_line => dcache_line, -- words
|
||||
WRITE_FIFO_SIZE => 4,
|
||||
WITH_TLB => WITH_TLB,
|
||||
TRANSLATE_KSEG0_1 => TRANSLATE_KSEG0_1
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
|
||||
clk => cpu_clk,
|
||||
busy => biu_busy,
|
||||
|
||||
imem_err => imem_err,
|
||||
dmem_err => dmem_err,
|
||||
|
||||
RST_I => biu_rst,
|
||||
CLK_I => CLK_I,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
ADDR_O => ADDR_O,
|
||||
DAT_I => DAT_I,
|
||||
DAT_O => DAT_O,
|
||||
MDAT_I => DAT_I,
|
||||
MDAT_O => DAT_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
MRDY_O => MRDY_O,
|
||||
cop0_ctrl_in => pipe_c0_ctrl_in,
|
||||
cpu_clk => cpu_clk,
|
||||
cpu_imem_err => imem_err,
|
||||
cpu_imem_rdy => imem_rdy,
|
||||
cpu_imem_en => imem_en,
|
||||
cpu_imem_addr => imem_addr,
|
||||
cpu_imem_din => imem_din,
|
||||
cpu_dmem_err => dmem_err,
|
||||
cpu_dmem_rdy => dmem_rdy,
|
||||
cpu_dmem_en => dmem_en,
|
||||
cpu_dmem_we => dmem_we,
|
||||
cpu_dmem_be => dmem_be,
|
||||
cpu_dmem_addr => dmem_addr,
|
||||
cpu_dmem_din => dmem_din,
|
||||
cpu_dmem_dout => dmem_dout
|
||||
|
||||
ctrl_in => biu_ctrl_in,
|
||||
ctrl_out => biu_ctrl_out
|
||||
|
||||
);
|
||||
|
||||
biu_ctrl_in.icache <= cop0_ctrl_out.icache;
|
||||
biu_ctrl_in.dcache <= cop0_ctrl_out.dcache;
|
||||
biu_ctrl_in.itlb_ctrl <= cop0_ctrl_out.itlb_ctrl;
|
||||
biu_ctrl_in.dtlb_ctrl <= cop0_ctrl_out.dtlb_ctrl;
|
||||
-- biu_ctrl_in.itlb_qry <= pipe_ctrl_out.itlb_qry;
|
||||
-- biu_ctrl_in.dtlb_qry <= pipe_ctrl_out.dtlb_qry;
|
||||
|
||||
-------------------------------------------
|
||||
-- debug
|
||||
-------------------------------------------
|
||||
debug.imem_err <= imem_err;
|
||||
debug.dmem_err <= dmem_err;
|
||||
|
||||
debug_imem_din_register:
|
||||
process(cpu_clk)
|
||||
variable en_r: std_logic;
|
||||
variable addr_r: word_t;
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
debug.imem_din_vld <= '0';
|
||||
if biu_ctrl_out.icache_qry.rdy = '1' then
|
||||
if en_r = '1' then
|
||||
debug.imem_addr_reg <= addr_r;
|
||||
debug.imem_din_reg <= biu_ctrl_out.icache_qry.data;
|
||||
debug.imem_din_vld <= '1';
|
||||
end if;
|
||||
if biu_ctrl_in.icache_qry.en = '1' then
|
||||
addr_r := biu_ctrl_in.icache_qry.addr;
|
||||
end if;
|
||||
en_r := biu_ctrl_in.icache_qry.en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
debug_dmem_din_register:
|
||||
process(cpu_clk)
|
||||
variable en_r: std_logic;
|
||||
variable we_r: std_logic;
|
||||
variable addr_r: word_t;
|
||||
variable dout_r: word_t;
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
debug.dmem_din_vld <= '0';
|
||||
debug.dmem_dout_vld <= '0';
|
||||
if biu_ctrl_out.dcache_qry.rdy = '1' then
|
||||
if en_r = '1' then
|
||||
debug.dmem_addr_reg <= addr_r;
|
||||
debug.dmem_din_reg <= biu_ctrl_out.dcache_qry.data;
|
||||
debug.dmem_din_vld <= not we_r;
|
||||
debug.dmem_dout_reg <= dout_r;
|
||||
debug.dmem_dout_vld <= we_r;
|
||||
end if;
|
||||
if biu_ctrl_in.dcache_qry.en = '1' then
|
||||
dout_r := biu_ctrl_in.dcache_qry.data;
|
||||
addr_r := biu_ctrl_in.dcache_qry.addr;
|
||||
end if;
|
||||
en_r := biu_ctrl_in.dcache_qry.en;
|
||||
we_r := biu_ctrl_in.dcache_qry.we;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
|
||||
@@ -26,12 +26,18 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_util_pkg.all;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
package mips_types is
|
||||
|
||||
-- Revision of the CPU
|
||||
constant REVISION : integer := 13;
|
||||
constant WORD_WIDTH : integer := 32;
|
||||
constant REVISION : integer := 14;
|
||||
constant WORD_WIDTH : integer := 32;
|
||||
constant TLB_PAGE_SIZE : positive := 4096;
|
||||
constant TLB_NUM_ASIDS : positive := 64;
|
||||
constant TLB_NUM_ENTRIES : positive := 32;
|
||||
|
||||
--Types
|
||||
subtype instr_name_t is string(1 to 12);
|
||||
@@ -45,9 +51,17 @@ package mips_types is
|
||||
|
||||
type chip_debug_t is record
|
||||
imem_err : std_logic;
|
||||
imem_addr_reg : word_t;
|
||||
imem_din_reg : word_t;
|
||||
imem_din_vld : std_logic;
|
||||
dmem_err : std_logic;
|
||||
dmem_addr_reg : word_t;
|
||||
dmem_din_reg : word_t;
|
||||
dmem_din_vld : std_logic;
|
||||
dmem_dout_reg : word_t;
|
||||
dmem_dout_vld : std_logic;
|
||||
end record;
|
||||
|
||||
|
||||
type op_t is
|
||||
(
|
||||
op_illegal,
|
||||
@@ -159,11 +173,14 @@ package mips_types is
|
||||
type wptr_src_t is (wptr_src_imm, wptr_src_const);
|
||||
|
||||
type pc_t is record
|
||||
curr : word_t;
|
||||
last : word_t;
|
||||
nxt : word_t;
|
||||
pc_branch : word_t;
|
||||
branch_take : std_logic;
|
||||
curr : word_t;
|
||||
last : word_t;
|
||||
nxt : word_t;
|
||||
pc_branch : word_t;
|
||||
pc_branch_revert : word_t;
|
||||
branch_take : std_logic;
|
||||
branch_not_taken : std_logic;
|
||||
plus4 : word_t;
|
||||
end record;
|
||||
|
||||
type alu_outsel_t is
|
||||
@@ -227,6 +244,12 @@ package mips_types is
|
||||
syscall : STD_LOGIC;
|
||||
break : STD_LOGIC;
|
||||
illegal : STD_LOGIC;
|
||||
ITLB_MOD : STD_LOGIC;
|
||||
ITLB_LOAD : STD_LOGIC;
|
||||
ITLB_STORE : STD_LOGIC;
|
||||
DTLB_MOD : STD_LOGIC;
|
||||
DTLB_LOAD : STD_LOGIC;
|
||||
DTLB_STORE : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type exc_flags_t is record
|
||||
@@ -239,6 +262,12 @@ package mips_types is
|
||||
Sys : STD_LOGIC;
|
||||
Bp : STD_LOGIC;
|
||||
RI : STD_LOGIC;
|
||||
ITLB_MOD : STD_LOGIC;
|
||||
ITLB_LOAD : STD_LOGIC;
|
||||
ITLB_STORE : STD_LOGIC;
|
||||
DTLB_MOD : STD_LOGIC;
|
||||
DTLB_LOAD : STD_LOGIC;
|
||||
DTLB_STORE : STD_LOGIC;
|
||||
IBE : STD_LOGIC;
|
||||
DBE : STD_LOGIC;
|
||||
end record;
|
||||
@@ -249,25 +278,108 @@ package mips_types is
|
||||
cause : word_t;
|
||||
end record;
|
||||
|
||||
type icache_query_in_t is record
|
||||
en : std_logic;
|
||||
nc : std_logic;
|
||||
addr : word_t;
|
||||
end record;
|
||||
|
||||
type icache_query_out_t is record
|
||||
rdy : std_logic;
|
||||
data : word_t;
|
||||
end record;
|
||||
|
||||
type dcache_query_in_t is record
|
||||
en : std_logic;
|
||||
we : std_logic;
|
||||
be : unsigned(3 downto 0);
|
||||
nc : std_logic;
|
||||
addr : word_t;
|
||||
data : word_t;
|
||||
end record;
|
||||
|
||||
type dcache_query_out_t is record
|
||||
rdy : std_logic;
|
||||
data : word_t;
|
||||
end record;
|
||||
|
||||
type cache_ctrl_t is record
|
||||
inv_addr : word_t;
|
||||
inv_at : STD_LOGIC;
|
||||
inv_all : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_in_t is record
|
||||
sdu : sdu_t;
|
||||
events : event_t;
|
||||
bd_wb : STD_LOGIC;
|
||||
epc_mem : word_t;
|
||||
epc_wb : word_t;
|
||||
imem_addr : word_t;
|
||||
dmem_addr : word_t;
|
||||
exc_req : STD_LOGIC;
|
||||
exc_ack : STD_LOGIC;
|
||||
type tlb_flags_t is record
|
||||
N : std_logic;
|
||||
D : std_logic;
|
||||
V : std_logic;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_out_t is record
|
||||
type tlb_entry_lo_t is record
|
||||
PFN : unsigned (31 downto lg2(TLB_PAGE_SIZE));
|
||||
G : std_logic;
|
||||
N : std_logic;
|
||||
D : std_logic;
|
||||
V : std_logic;
|
||||
end record;
|
||||
|
||||
type tlb_entry_hi_t is record
|
||||
VPN : unsigned (31 downto lg2(TLB_PAGE_SIZE));
|
||||
ASID : unsigned (lg2(TLB_NUM_ASIDS)-1 downto 0);
|
||||
end record;
|
||||
|
||||
type tlb_query_in_t is record
|
||||
vld : std_logic;
|
||||
write : std_logic;
|
||||
vaddr : word_t;
|
||||
end record;
|
||||
|
||||
type tlb_query_out_t is record
|
||||
vld : std_logic;
|
||||
paddr : word_t;
|
||||
miss : STD_LOGIC;
|
||||
dirty : std_logic;
|
||||
write : std_logic;
|
||||
flags : tlb_flags_t;
|
||||
end record;
|
||||
|
||||
type tlb_ctrl_in_t is record
|
||||
entry_we : STD_LOGIC;
|
||||
entry_re : STD_LOGIC;
|
||||
entry_rd_idx : unsigned (lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
entry_wr_idx : unsigned (lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
entry_lo : tlb_entry_lo_t;
|
||||
entry_hi : tlb_entry_hi_t;
|
||||
end record;
|
||||
|
||||
type tlb_ctrl_out_t is record
|
||||
entry_vld : std_logic;
|
||||
entry_lo : tlb_entry_lo_t;
|
||||
entry_hi : tlb_entry_hi_t;
|
||||
entry_prb_idx : unsigned (lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
end record;
|
||||
|
||||
type biu_ctrl_in_t is record
|
||||
itlb_ctrl : tlb_ctrl_in_t;
|
||||
dtlb_ctrl : tlb_ctrl_in_t;
|
||||
icache : cache_ctrl_t;
|
||||
dcache : cache_ctrl_t;
|
||||
itlb_qry : tlb_query_in_t;
|
||||
dtlb_qry : tlb_query_in_t;
|
||||
icache_qry : icache_query_in_t;
|
||||
dcache_qry : dcache_query_in_t;
|
||||
end record;
|
||||
|
||||
type biu_ctrl_out_t is record
|
||||
itlb_ctrl : tlb_ctrl_out_t;
|
||||
dtlb_ctrl : tlb_ctrl_out_t;
|
||||
itlb_qry : tlb_query_out_t;
|
||||
dtlb_qry : tlb_query_out_t;
|
||||
icache_qry : icache_query_out_t;
|
||||
dcache_qry : dcache_query_out_t;
|
||||
end record;
|
||||
|
||||
type pipe_ctrl_in_t is record
|
||||
EB : STD_LOGIC;
|
||||
exc_inject : STD_LOGIC;
|
||||
exc_commit : STD_LOGIC;
|
||||
@@ -277,6 +389,29 @@ package mips_types is
|
||||
NMI : STD_LOGIC;
|
||||
int : STD_LOGIC;
|
||||
exc_vec : word_t;
|
||||
end record;
|
||||
|
||||
type pipe_ctrl_out_t is record
|
||||
sdu : sdu_t;
|
||||
events : event_t;
|
||||
bd_wb : STD_LOGIC;
|
||||
epc_wb : word_t;
|
||||
imem_addr : word_t;
|
||||
dmem_addr : word_t;
|
||||
exc_req : STD_LOGIC;
|
||||
exc_ack : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_in_t is record
|
||||
pipe : pipe_ctrl_out_t;
|
||||
itlb_ctrl : tlb_ctrl_out_t;
|
||||
dtlb_ctrl : tlb_ctrl_out_t;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_out_t is record
|
||||
pipe : pipe_ctrl_in_t;
|
||||
itlb_ctrl : tlb_ctrl_in_t;
|
||||
dtlb_ctrl : tlb_ctrl_in_t;
|
||||
icache : cache_ctrl_t;
|
||||
dcache : cache_ctrl_t;
|
||||
end record;
|
||||
@@ -337,76 +472,93 @@ package mips_types is
|
||||
type ID_t is record
|
||||
nop : STD_LOGIC;
|
||||
exc : std_logic;
|
||||
IR : word_t;
|
||||
op : op_t;
|
||||
pcn : word_t;
|
||||
IR : word_t;
|
||||
epc : word_t;
|
||||
pcn : word_t;
|
||||
jimm32 : word_t;
|
||||
bimm18 : word_t;
|
||||
imm : word_t;
|
||||
shamt : shamt_t;
|
||||
ctrl : ctrl_lines_t;
|
||||
va : word_t;
|
||||
reg_write : STD_LOGIC;
|
||||
reg_a_rptr : reg_ptr_t;
|
||||
reg_b_rptr : reg_ptr_t;
|
||||
reg_a : word_t;
|
||||
reg_b : word_t;
|
||||
events : event_t;
|
||||
bcu_flags : bcu_flags_t;
|
||||
itlb_qry : tlb_query_out_t;
|
||||
end record;
|
||||
|
||||
type EX_t is record
|
||||
nop : STD_LOGIC;
|
||||
exc : std_logic;
|
||||
IR : word_t;
|
||||
op : op_t;
|
||||
pcn : word_t;
|
||||
IR : word_t;
|
||||
epc : word_t;
|
||||
pcn : word_t;
|
||||
reg_a : word_t;
|
||||
reg_b : word_t;
|
||||
result : word_t;
|
||||
ctrl : ctrl_lines_t;
|
||||
shift_ctrl : shift_ctrl_t;
|
||||
alu_op1 : word_t;
|
||||
alu_op2 : word_t;
|
||||
alu_op2_s : word_t;
|
||||
alu_flags : alu_flags_t;
|
||||
result : word_t;
|
||||
reg_write : STD_LOGIC;
|
||||
wreg_we : STD_LOGIC;
|
||||
reg_we : STD_LOGIC;
|
||||
reg_wptr : reg_ptr_t;
|
||||
reg_a_rptr : reg_ptr_t;
|
||||
reg_b_rptr : reg_ptr_t;
|
||||
va : word_t;
|
||||
dmem_en : STD_LOGIC;
|
||||
pa_off : unsigned(1 downto 0);
|
||||
events_in : event_t;
|
||||
events : event_t;
|
||||
bcu_flags : bcu_flags_t;
|
||||
branch_not_taken : std_logic;
|
||||
dtlb_qry : tlb_query_out_t;
|
||||
end record;
|
||||
|
||||
type MEM_t is record
|
||||
nop : STD_LOGIC;
|
||||
exc : std_logic;
|
||||
op : op_t;
|
||||
pcn : word_t;
|
||||
epc : word_t;
|
||||
pcn : word_t;
|
||||
reg_a : word_t;
|
||||
reg_b : word_t;
|
||||
result : word_t;
|
||||
result_in : word_t;
|
||||
ctrl : ctrl_lines_t;
|
||||
ex_result : word_t;
|
||||
reg_wptr : reg_ptr_t;
|
||||
wreg_we : STD_LOGIC;
|
||||
data : word_t;
|
||||
reg_we : STD_LOGIC;
|
||||
va : word_t;
|
||||
pa_off : unsigned(1 downto 0);
|
||||
events_in : event_t;
|
||||
events : event_t;
|
||||
bcu_flags : bcu_flags_t;
|
||||
branch_not_taken : std_logic;
|
||||
end record;
|
||||
|
||||
type WB_t is record
|
||||
nop : STD_LOGIC;
|
||||
epc : word_t;
|
||||
reg_a : word_t;
|
||||
reg_b : word_t;
|
||||
result : word_t;
|
||||
bd : STD_LOGIC;
|
||||
exc : std_logic;
|
||||
exc_last : std_logic;
|
||||
events : event_t;
|
||||
op : op_t;
|
||||
reg_wptr : reg_ptr_t;
|
||||
wreg_we : STD_LOGIC;
|
||||
data : word_t;
|
||||
bd : STD_LOGIC;
|
||||
reg_we : STD_LOGIC;
|
||||
va : word_t;
|
||||
bcu_flags : bcu_flags_t;
|
||||
end record;
|
||||
|
||||
|
||||
@@ -422,9 +574,7 @@ package mips_types is
|
||||
function events_clr return event_t;
|
||||
function event_is_active(e : event_t) return std_logic;
|
||||
function "or" (a, b : event_t) return event_t;
|
||||
|
||||
function lg2(x : natural) return natural;
|
||||
function po2(x : natural) return natural;
|
||||
function "or" (a, b : tlb_flags_t) return tlb_flags_t;
|
||||
|
||||
end mips_types;
|
||||
|
||||
@@ -608,6 +758,12 @@ package body mips_types is
|
||||
result.syscall := '0';
|
||||
result.break := '0';
|
||||
result.illegal := '0';
|
||||
result.ITLB_MOD := '0';
|
||||
result.ITLB_LOAD := '0';
|
||||
result.ITLB_STORE := '0';
|
||||
result.DTLB_MOD := '0';
|
||||
result.DTLB_LOAD := '0';
|
||||
result.DTLB_STORE := '0';
|
||||
|
||||
return result;
|
||||
|
||||
@@ -630,6 +786,12 @@ package body mips_types is
|
||||
result := result or e.syscall;
|
||||
result := result or e.break;
|
||||
result := result or e.illegal;
|
||||
result := result or e.ITLB_MOD;
|
||||
result := result or e.ITLB_LOAD;
|
||||
result := result or e.ITLB_STORE;
|
||||
result := result or e.DTLB_MOD;
|
||||
result := result or e.DTLB_LOAD;
|
||||
result := result or e.DTLB_STORE;
|
||||
|
||||
return result;
|
||||
|
||||
@@ -650,23 +812,28 @@ package body mips_types is
|
||||
result.syscall := a.syscall or b.syscall;
|
||||
result.break := a.break or b.break;
|
||||
result.illegal := a.illegal or b.illegal;
|
||||
result.ITLB_MOD := a.ITLB_MOD or b.ITLB_MOD;
|
||||
result.ITLB_LOAD := a.ITLB_LOAD or b.ITLB_LOAD;
|
||||
result.ITLB_STORE := a.ITLB_STORE or b.ITLB_STORE;
|
||||
result.DTLB_MOD := a.DTLB_MOD or b.DTLB_MOD;
|
||||
result.DTLB_LOAD := a.DTLB_LOAD or b.DTLB_LOAD;
|
||||
result.DTLB_STORE := a.DTLB_STORE or b.DTLB_STORE;
|
||||
|
||||
return result;
|
||||
|
||||
end "or";
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function lg2(x : natural) return natural is
|
||||
function "or" (a, b : tlb_flags_t) return tlb_flags_t is
|
||||
variable result : tlb_flags_t;
|
||||
begin
|
||||
return natural(ceil(log2(real(x))));
|
||||
end lg2;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function po2(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**lg2(x);
|
||||
end po2;
|
||||
result.N := a.N or b.N;
|
||||
result.D := a.D or b.D;
|
||||
result.V := a.V or b.V;
|
||||
|
||||
return result;
|
||||
|
||||
end "or";
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end mips_types;
|
||||
|
||||
@@ -0,0 +1,410 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_biu IS
|
||||
END tb_biu;
|
||||
|
||||
ARCHITECTURE behavior OF tb_biu IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal index_in : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_we : STD_LOGIC := '0';
|
||||
signal entry_lo_in : tlb_entry_lo_t;
|
||||
signal entry_hi_in : tlb_entry_hi_t;
|
||||
|
||||
signal index_out : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_re : STD_LOGIC := '0';
|
||||
signal entry_lo_out : tlb_entry_lo_t;
|
||||
signal entry_hi_out : tlb_entry_hi_t;
|
||||
|
||||
-- CPU control/data
|
||||
signal cpu_imem_err : STD_LOGIC := '0';
|
||||
signal cpu_imem_en : STD_LOGIC := '0';
|
||||
signal cpu_imem_addr : word_t := (others => '-');
|
||||
signal cpu_imem_dout : word_t;
|
||||
signal cpu_imem_rdy : STD_LOGIC;
|
||||
|
||||
signal cpu_dmem_err : STD_LOGIC := '0';
|
||||
signal cpu_dmem_en : STD_LOGIC := '0';
|
||||
signal cpu_dmem_we : STD_LOGIC := '0';
|
||||
signal cpu_dmem_addr : word_t := (others => '-');
|
||||
signal cpu_dmem_be : unsigned(3 downto 0) := (others => '1');
|
||||
signal cpu_dmem_din : word_t := X"BFC0_BABE";
|
||||
signal cpu_dmem_dout : word_t;
|
||||
signal cpu_dmem_rdy : STD_LOGIC;
|
||||
|
||||
-- BIU control
|
||||
signal ctrl_in : biu_ctrl_in_t;
|
||||
signal ctrl_out : biu_ctrl_out_t;
|
||||
|
||||
type op_descr_t is (op_idle, op_entry_i_write, op_entry_d_write, op_cpu_i_read, op_cpu_d_read, op_cpu_d_write);
|
||||
signal op_descr : op_descr_t := op_idle;
|
||||
|
||||
signal cpu_imem_din_reg : word_t;
|
||||
signal cpu_imem_din_vld : STD_LOGIC;
|
||||
signal cpu_dmem_din_reg : word_t;
|
||||
signal cpu_dmem_din_vld : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_biu: entity work.biu
|
||||
GENERIC MAP
|
||||
(
|
||||
ICACHE_SIZE => 1024, -- words
|
||||
ICACHE_LINE => 8, -- words
|
||||
DCACHE_SIZE => 1024, -- words
|
||||
DCACHE_LINE => 8, -- words
|
||||
WRITE_FIFO_SIZE => 4, -- words
|
||||
WITH_TLB => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK,
|
||||
|
||||
imem_err => cpu_imem_err,
|
||||
imem_rdy => cpu_imem_rdy,
|
||||
imem_en => cpu_imem_en,
|
||||
imem_addr => cpu_imem_addr,
|
||||
imem_dout => cpu_imem_dout,
|
||||
dmem_err => cpu_dmem_err,
|
||||
dmem_rdy => cpu_dmem_rdy,
|
||||
dmem_en => cpu_dmem_en,
|
||||
dmem_we => cpu_dmem_we,
|
||||
dmem_be => cpu_dmem_be,
|
||||
dmem_dout => cpu_dmem_dout,
|
||||
dmem_din => cpu_dmem_din,
|
||||
dmem_addr => cpu_dmem_addr,
|
||||
|
||||
RST_I => RST,
|
||||
CLK_I => CLK,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
MRDY_O => MRDY_O,
|
||||
|
||||
ctrl_in => ctrl_in,
|
||||
ctrl_out => ctrl_out
|
||||
|
||||
);
|
||||
|
||||
|
||||
inst_rom_wb: entity work.rom_wb
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- NUM_WORDS => 256
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => CLK,
|
||||
RST_I => RST,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
-- SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
-- DAT_I => MDAT_O,
|
||||
DAT_O => MDAT_I
|
||||
);
|
||||
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
cpu_imem_din_register:
|
||||
process(clk)
|
||||
variable en2: std_logic;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cpu_imem_din_vld <= '0';
|
||||
if en2 = '1' and cpu_imem_rdy = '1' then
|
||||
cpu_imem_din_reg <= cpu_imem_dout;
|
||||
cpu_imem_din_vld <= '1';
|
||||
end if;
|
||||
en2 := cpu_imem_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_dmem_din_register:
|
||||
process(clk)
|
||||
variable en2: std_logic;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cpu_dmem_din_vld <= '0';
|
||||
if en2 = '1' and cpu_dmem_rdy = '1' then
|
||||
cpu_dmem_din_reg <= cpu_dmem_dout;
|
||||
cpu_dmem_din_vld <= '1';
|
||||
end if;
|
||||
en2 := cpu_dmem_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
ctrl_in.icache.inv_addr <= X"BEEF_BABE";
|
||||
ctrl_in.icache.inv_at <= '0';
|
||||
ctrl_in.icache.inv_all <= '0';
|
||||
|
||||
ctrl_in.dcache.inv_addr <= X"BEEF_BABE";
|
||||
ctrl_in.dcache.inv_at <= '0';
|
||||
ctrl_in.dcache.inv_all <= '0';
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_entry_i_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
|
||||
begin
|
||||
|
||||
op_descr <= op_entry_i_write;
|
||||
|
||||
ctrl_in.itlb.entry_wr_idx <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
|
||||
|
||||
ctrl_in.itlb.entry_hi.vpn <= vpn;
|
||||
ctrl_in.itlb.entry_hi.asid <= asid;
|
||||
|
||||
ctrl_in.itlb.entry_lo.pfn <= pfn;
|
||||
ctrl_in.itlb.entry_lo.n <= n;
|
||||
ctrl_in.itlb.entry_lo.d <= d;
|
||||
ctrl_in.itlb.entry_lo.v <= v;
|
||||
ctrl_in.itlb.entry_lo.g <= g;
|
||||
|
||||
ctrl_in.itlb.entry_we <= '1';
|
||||
wait until rising_edge(CLK);
|
||||
ctrl_in.itlb.entry_we <= '0';
|
||||
|
||||
end procedure cmd_entry_i_write;
|
||||
|
||||
procedure cmd_entry_d_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
|
||||
begin
|
||||
|
||||
op_descr <= op_entry_d_write;
|
||||
ctrl_in.dtlb.entry_wr_idx <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
|
||||
|
||||
ctrl_in.dtlb.entry_hi.vpn <= vpn;
|
||||
ctrl_in.dtlb.entry_hi.asid <= asid;
|
||||
|
||||
ctrl_in.dtlb.entry_lo.pfn <= pfn;
|
||||
ctrl_in.dtlb.entry_lo.n <= n;
|
||||
ctrl_in.dtlb.entry_lo.d <= d;
|
||||
ctrl_in.dtlb.entry_lo.v <= v;
|
||||
ctrl_in.dtlb.entry_lo.g <= g;
|
||||
|
||||
ctrl_in.dtlb.entry_we <= '1';
|
||||
wait until rising_edge(CLK);
|
||||
ctrl_in.dtlb.entry_we <= '0';
|
||||
|
||||
end procedure cmd_entry_d_write;
|
||||
|
||||
procedure cpu_i_read(addr : unsigned) is
|
||||
begin
|
||||
|
||||
op_descr <= op_cpu_i_read;
|
||||
cpu_imem_addr <= addr;
|
||||
cpu_imem_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_imem_rdy = '1';
|
||||
cpu_imem_en <= '0';
|
||||
|
||||
end procedure cpu_i_read;
|
||||
|
||||
procedure cpu_d_read(addr : unsigned) is
|
||||
begin
|
||||
|
||||
op_descr <= op_cpu_d_read;
|
||||
cpu_dmem_addr <= addr;
|
||||
cpu_dmem_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_dmem_rdy = '1';
|
||||
cpu_dmem_en <= '0';
|
||||
|
||||
end procedure cpu_d_read;
|
||||
|
||||
procedure cpu_d_write(addr, data : unsigned) is
|
||||
begin
|
||||
|
||||
op_descr <= op_cpu_d_write;
|
||||
cpu_dmem_we <= '1';
|
||||
cpu_dmem_addr <= addr;
|
||||
cpu_dmem_din <= data;
|
||||
cpu_dmem_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_dmem_rdy = '1';
|
||||
cpu_dmem_en <= '0';
|
||||
|
||||
end procedure cpu_d_write;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK) and cpu_imem_rdy = '1' and cpu_dmem_rdy = '1';
|
||||
|
||||
cmd_entry_i_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_i_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
|
||||
|
||||
cmd_entry_d_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_d_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
|
||||
|
||||
cpu_i_read(X"BFC0_0200");
|
||||
cpu_i_read(X"BFC0_0180");
|
||||
cpu_d_read(X"BFC0_0200");
|
||||
|
||||
cpu_i_read(X"8000_0204");
|
||||
cpu_i_read(X"8000_0300");
|
||||
cpu_i_read(X"8000_0304");
|
||||
cpu_i_read(X"8000_0308");
|
||||
|
||||
cpu_i_read(X"9000_0208");
|
||||
cpu_i_read(X"9000_030C");
|
||||
cpu_i_read(X"9100_0310");
|
||||
cpu_i_read(X"9200_0314");
|
||||
|
||||
cpu_i_read(X"A000_020C");
|
||||
cpu_i_read(X"A000_0318");
|
||||
cpu_i_read(X"A100_031C");
|
||||
cpu_i_read(X"A200_0320");
|
||||
|
||||
cpu_i_read(X"B000_0210");
|
||||
cpu_i_read(X"B000_0324");
|
||||
cpu_i_read(X"B000_0328");
|
||||
cpu_i_read(X"B000_032C");
|
||||
|
||||
cpu_i_read(X"0000_0400");
|
||||
cpu_i_read(X"0000_1420");
|
||||
cpu_i_read(X"0000_2440");
|
||||
cpu_i_read(X"0000_3460");
|
||||
cpu_i_read(X"0000_4480");
|
||||
cpu_i_read(X"0000_54A0");
|
||||
cpu_i_read(X"0000_64C0");
|
||||
cpu_i_read(X"0000_74E0");
|
||||
cpu_i_read(X"0000_8500");
|
||||
cpu_i_read(X"0000_9520");
|
||||
|
||||
cpu_i_read(X"0000_0400");
|
||||
cpu_i_read(X"0000_1420");
|
||||
cpu_i_read(X"0000_2440");
|
||||
cpu_i_read(X"0000_3460");
|
||||
cpu_i_read(X"0000_4480");
|
||||
cpu_i_read(X"0000_54A0");
|
||||
cpu_i_read(X"0000_64C0");
|
||||
cpu_i_read(X"0000_74E0");
|
||||
|
||||
|
||||
cpu_i_read(X"0000_0400");
|
||||
|
||||
cpu_i_read(X"0000_0410");
|
||||
cpu_i_read(X"0000_0404");
|
||||
cpu_i_read(X"0000_0408");
|
||||
cpu_i_read(X"0000_0404");
|
||||
cpu_i_read(X"0000_0434");
|
||||
cpu_i_read(X"0000_0400");
|
||||
|
||||
|
||||
---------------------------------------------
|
||||
cpu_d_read(X"BFC0_0200");
|
||||
cpu_d_read(X"BFC0_0180");
|
||||
|
||||
cpu_d_read(X"8000_0204");
|
||||
cpu_d_read(X"8000_0300");
|
||||
cpu_d_read(X"8000_0304");
|
||||
cpu_d_read(X"8000_0308");
|
||||
|
||||
cpu_d_read(X"9000_0208");
|
||||
cpu_d_read(X"9000_030C");
|
||||
cpu_d_read(X"9100_0310");
|
||||
cpu_d_read(X"9200_0314");
|
||||
|
||||
cpu_d_read(X"A000_020C");
|
||||
cpu_d_read(X"A000_0318");
|
||||
cpu_d_read(X"A100_031C");
|
||||
cpu_d_read(X"A200_0320");
|
||||
|
||||
cpu_d_read(X"B000_0210");
|
||||
cpu_d_read(X"B000_0324");
|
||||
cpu_d_read(X"B000_0328");
|
||||
cpu_d_read(X"B000_032C");
|
||||
|
||||
cpu_d_read(X"0000_0400");
|
||||
cpu_d_read(X"0000_1420");
|
||||
cpu_d_read(X"0000_2440");
|
||||
cpu_d_read(X"0000_3460");
|
||||
cpu_d_read(X"0000_4480");
|
||||
cpu_d_read(X"0000_54A0");
|
||||
cpu_d_read(X"0000_64C0");
|
||||
cpu_d_read(X"0000_74E0");
|
||||
cpu_d_read(X"0000_8500");
|
||||
cpu_d_read(X"0000_9520");
|
||||
|
||||
cpu_d_read(X"0000_0400");
|
||||
cpu_d_read(X"0000_1420");
|
||||
cpu_d_read(X"0000_2440");
|
||||
cpu_d_read(X"0000_3460");
|
||||
cpu_d_read(X"0000_4480");
|
||||
cpu_d_read(X"0000_54A0");
|
||||
cpu_d_read(X"0000_64C0");
|
||||
cpu_d_read(X"0000_74E0");
|
||||
cpu_d_write(X"0000_0400", X"AAAA_AAAA");
|
||||
|
||||
cpu_d_read(X"0000_0400");
|
||||
|
||||
cpu_d_read(X"0000_0410");
|
||||
cpu_d_read(X"0000_0404");
|
||||
cpu_d_read(X"0000_0408");
|
||||
cpu_d_write(X"0000_0404", X"5555_5555");
|
||||
cpu_d_read(X"0000_0404");
|
||||
cpu_d_write(X"0000_0404", X"6666_6666");
|
||||
cpu_d_read(X"0000_0434");
|
||||
cpu_d_write(X"0000_0400", X"1111_1111");
|
||||
cpu_d_write(X"0000_0404", X"2222_2222");
|
||||
cpu_d_write(X"0000_0408", X"3333_3333");
|
||||
cpu_d_write(X"0000_040C", X"4444_4444");
|
||||
cpu_d_read(X"0000_0400");
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,265 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
|
||||
ENTITY tb_cam IS
|
||||
END tb_cam;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cam IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant DATA_WIDTH : integer := 20;
|
||||
constant CAM_NUM_ENTRIES : integer := 32;
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
signal cam_we : std_logic := '0';
|
||||
signal cam_re : std_logic := '0';
|
||||
signal cam_vld : std_logic := '0';
|
||||
signal cam_rdy : std_logic := '-';
|
||||
|
||||
signal cam_addr : unsigned(lg2(CAM_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal cam_rtag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal cam_wtag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal cam_hit : unsigned (CAM_NUM_ENTRIES-1 downto 0);
|
||||
signal cam_hit_vld : std_logic := '-';
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_cam: entity work.cam
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => CAM_NUM_ENTRIES,
|
||||
DATA_WIDTH => DATA_WIDTH,
|
||||
CAM_RAM_MAX_WIDTH => 15
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
clk_rd => CLK_O,
|
||||
|
||||
rdy => cam_rdy,
|
||||
|
||||
re => cam_re,
|
||||
we => cam_we,
|
||||
vld => cam_vld,
|
||||
addr => cam_addr,
|
||||
tag_rd => cam_rtag,
|
||||
tag_wr => cam_wtag,
|
||||
|
||||
hit_vld => cam_hit_vld,
|
||||
hit => cam_hit
|
||||
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
variable tag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
procedure cam_entry_write(index : integer; data : unsigned; valid : std_logic) is
|
||||
begin
|
||||
|
||||
cam_wtag <= data;
|
||||
cam_addr <= to_unsigned(index, lg2(CAM_NUM_ENTRIES));
|
||||
cam_vld <= valid;
|
||||
cam_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_we <= '0';
|
||||
|
||||
end procedure cam_entry_write;
|
||||
|
||||
procedure cam_lookup(data : unsigned) is
|
||||
begin
|
||||
|
||||
cam_rtag <= data;
|
||||
cam_re <= '1';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_re <= '0';
|
||||
|
||||
end procedure cam_lookup;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
-----------------------
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_entry_write(i, tag, '1');
|
||||
tag := tag + X"0100_0";
|
||||
end loop;
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_lookup(tag);
|
||||
tag := tag + X"0100_0";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
RST_O <= '1';
|
||||
wait for 6*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
RST_O <= '0';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
-----------------------
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_entry_write(i, tag, '1');
|
||||
tag := tag + X"0010_0";
|
||||
end loop;
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_lookup(tag);
|
||||
tag := tag + X"0010_0";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
RST_O <= '1';
|
||||
wait for 6*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
RST_O <= '0';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
-----------------------
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_entry_write(i, tag, '1');
|
||||
tag := tag + X"0001_0";
|
||||
end loop;
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_lookup(tag);
|
||||
tag := tag + X"0001_0";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
RST_O <= '1';
|
||||
wait for 6*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
RST_O <= '0';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
-----------------------
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_entry_write(i, tag, '1');
|
||||
tag := tag + X"0000_1";
|
||||
end loop;
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_lookup(tag);
|
||||
tag := tag + X"0000_1";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
RST_O <= '1';
|
||||
wait for 6*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
RST_O <= '0';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
-----------------------
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_entry_write(i, tag, '1');
|
||||
tag := tag + X"0102_3";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
tag := X"CAF0_0";
|
||||
for i in 0 to CAM_NUM_ENTRIES-1 loop
|
||||
cam_lookup(tag);
|
||||
tag := tag + X"0102_3";
|
||||
end loop;
|
||||
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
RST_O <= '1';
|
||||
wait for 6*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
RST_O <= '0';
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
-----------------------
|
||||
-- overwrite
|
||||
cam_entry_write(2, X"BEEF_2", '1');
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
|
||||
-- overwrite entry
|
||||
cam_entry_write(2, X"CAFE_2", '1');
|
||||
-- new entry
|
||||
cam_entry_write(3, X"CAFE_3", '1');
|
||||
cam_entry_write(4, X"CAFE_4", '1');
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_entry_write(1, X"CAFE_1", '0');
|
||||
cam_entry_write(2, X"CAFE_2", '0');
|
||||
cam_entry_write(3, X"CAFE_3", '0');
|
||||
cam_entry_write(4, X"CAFE_4", '0');
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_lookup(X"BEEF_2");
|
||||
cam_lookup(X"CAFE_1");
|
||||
cam_lookup(X"CAFE_2");
|
||||
cam_lookup(X"CAFE_3");
|
||||
cam_lookup(X"CAFE_4");
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_entry_write(1, X"CAFE_1", '1');
|
||||
cam_entry_write(2, X"CAFE_2", '1');
|
||||
cam_entry_write(3, X"CAFE_3", '1');
|
||||
cam_entry_write(4, X"CAFE_4", '1');
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_lookup(X"CAFE_1");
|
||||
cam_lookup(X"CAFE_2");
|
||||
cam_lookup(X"CAFE_3");
|
||||
cam_lookup(X"CAFE_4");
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
cam_entry_write(7, X"CAFE_7", '0');
|
||||
|
||||
wait for 8*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and cam_rdy = '1';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,389 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_dcache IS
|
||||
END tb_dcache;
|
||||
|
||||
ARCHITECTURE behavior OF tb_dcache IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant TLB_NUM_ENTRIES : integer := 8;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal ce : std_logic := '1';
|
||||
|
||||
signal index_in : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_we : STD_LOGIC := '0';
|
||||
signal entry_lo_in : tlb_entry_lo_t;
|
||||
signal entry_hi_in : tlb_entry_hi_t;
|
||||
|
||||
signal index_out : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_re : STD_LOGIC := '0';
|
||||
signal entry_lo_out : tlb_entry_lo_t;
|
||||
signal entry_hi_out : tlb_entry_hi_t;
|
||||
|
||||
signal tlb_in : tlb_query_in_t;
|
||||
signal tlb_out : tlb_query_out_t;
|
||||
|
||||
signal tlb_index_hit : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
signal tlb_va : word_t := (others => '-');
|
||||
|
||||
signal tlb_pa : word_t;
|
||||
signal tlb_flags : tlb_flags_t;
|
||||
signal tlb_hit : STD_LOGIC;
|
||||
|
||||
-- CPU control/data
|
||||
signal cpu_en : STD_LOGIC := '0';
|
||||
signal cpu_we : STD_LOGIC := '0';
|
||||
signal cpu_addr : word_t := (others => '-');
|
||||
signal cpu_be : unsigned(3 downto 0) := (others => '1');
|
||||
signal cpu_din : word_t := X"BFC0_BABE";
|
||||
signal cpu_dout : word_t;
|
||||
signal cpu_rdy : STD_LOGIC;
|
||||
|
||||
-- Cache control
|
||||
signal dcache_ctrl_in : cache_ctrl_t;
|
||||
|
||||
-- busmaster data
|
||||
signal bus_din : word_t := (others => '-');
|
||||
signal bus_din_rdy : std_logic := '0';
|
||||
signal bus_din_vld : std_logic := '0';
|
||||
|
||||
signal bus_dout : word_t := (others => '-');
|
||||
signal bus_dout_vld : std_logic := '0';
|
||||
signal bus_dout_rdy : std_logic := '0';
|
||||
|
||||
-- busmaster command
|
||||
signal bus_cmd_rdy : std_logic := '0';
|
||||
signal bus_cmd_we : std_logic := '0';
|
||||
signal bus_cmd_cycle_en : std_logic := '0';
|
||||
signal bus_cmd : bm_cmd_t;
|
||||
signal bus_cyc_complete : std_logic := '0';
|
||||
|
||||
signal cpu_din_reg : word_t;
|
||||
signal cpu_din_vld : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_tlb : entity work.tlb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => TLB_NUM_ENTRIES
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
ce => ce,
|
||||
|
||||
index_in => index_in,
|
||||
entry_we => entry_we,
|
||||
entry_lo_in => entry_lo_in,
|
||||
entry_hi_in => entry_hi_in,
|
||||
|
||||
index_out => index_out,
|
||||
entry_re => entry_re,
|
||||
entry_lo_out => entry_lo_out,
|
||||
entry_hi_out => entry_hi_out,
|
||||
|
||||
tlb_query_in => tlb_in,
|
||||
tlb_query_out => tlb_out
|
||||
);
|
||||
|
||||
dcache_ctrl_in.inv_addr <= X"BEEF_BABE";
|
||||
dcache_ctrl_in.inv_at <= '0';
|
||||
dcache_ctrl_in.inv_all <= '0';
|
||||
|
||||
inst_dcache: entity work.dcache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => 1024,
|
||||
line_size => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
|
||||
-- CPU control/data
|
||||
en => cpu_en,
|
||||
we => cpu_we,
|
||||
addr => cpu_addr,
|
||||
be => cpu_be,
|
||||
din => cpu_din,
|
||||
dout => cpu_dout,
|
||||
rdy => cpu_rdy,
|
||||
|
||||
-- Cache control
|
||||
ctrl_in => dcache_ctrl_in,
|
||||
tlb_query_in => tlb_out,
|
||||
tlb_query_out => tlb_in,
|
||||
|
||||
-- busmaster data
|
||||
bus_din => bus_din,
|
||||
bus_din_rdy => bus_din_rdy,
|
||||
bus_din_vld => bus_din_vld,
|
||||
|
||||
bus_dout => bus_dout,
|
||||
bus_dout_vld => bus_dout_vld,
|
||||
bus_dout_rdy => bus_dout_rdy,
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy => bus_cmd_rdy,
|
||||
bus_cmd_we => bus_cmd_we,
|
||||
bus_cmd_cycle_en => bus_cmd_cycle_en,
|
||||
bus_cmd_out => bus_cmd,
|
||||
bus_cyc_complete => bus_cyc_complete
|
||||
);
|
||||
|
||||
|
||||
inst_busmaster_sync : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => DATA_WIDTH,
|
||||
FIFO_DEPTH => 4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
|
||||
cmd_cycle_finished => bus_cyc_complete,
|
||||
cmd_cycle_en => bus_cmd_cycle_en,
|
||||
|
||||
cmd_rdy => bus_cmd_rdy,
|
||||
cmd_we => bus_cmd_we,
|
||||
cmd_in => bus_cmd,
|
||||
|
||||
din_rdy => bus_dout_rdy,
|
||||
din_we => bus_dout_vld,
|
||||
din => bus_dout,
|
||||
|
||||
dout => bus_din,
|
||||
dout_vld => bus_din_vld,
|
||||
dout_re => bus_din_rdy,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
inst_rom_wb: entity work.rom_wb
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- NUM_WORDS => 256
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => CLK,
|
||||
RST_I => RST,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
-- SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
-- DAT_I => MDAT_O,
|
||||
DAT_O => MDAT_I
|
||||
);
|
||||
|
||||
|
||||
cpu_din_register:
|
||||
process(clk)
|
||||
variable en2: std_logic;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cpu_din_vld <= '0';
|
||||
if en2 = '1' and cpu_rdy = '1' then
|
||||
cpu_din_reg <= cpu_dout;
|
||||
cpu_din_vld <= '1';
|
||||
end if;
|
||||
en2 := cpu_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
|
||||
begin
|
||||
|
||||
index_in <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
|
||||
|
||||
entry_hi_in.vpn <= vpn;
|
||||
entry_hi_in.asid <= asid;
|
||||
entry_hi_in.g <= g;
|
||||
|
||||
entry_lo_in.pfn <= pfn;
|
||||
entry_lo_in.n <= n;
|
||||
entry_lo_in.d <= d;
|
||||
entry_lo_in.v <= v;
|
||||
|
||||
entry_we <= '1';
|
||||
wait until rising_edge(CLK);
|
||||
entry_we <= '0';
|
||||
|
||||
end procedure cmd_entry_write;
|
||||
|
||||
procedure cpu_read(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cpu_we <= '0';
|
||||
cpu_addr <= addr;
|
||||
cpu_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
cpu_en <= '0';
|
||||
|
||||
end procedure cpu_read;
|
||||
|
||||
procedure cpu_write(addr, data : unsigned) is
|
||||
begin
|
||||
|
||||
cpu_we <= '1';
|
||||
cpu_addr <= addr;
|
||||
cpu_din <= data;
|
||||
cpu_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
cpu_en <= '0';
|
||||
|
||||
end procedure cpu_write;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
|
||||
cmd_entry_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
|
||||
cmd_entry_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
|
||||
|
||||
|
||||
cpu_read(X"BFC0_0200");
|
||||
cpu_read(X"BFC0_0180");
|
||||
|
||||
cpu_read(X"8000_0204");
|
||||
cpu_read(X"8000_0300");
|
||||
cpu_read(X"8000_0304");
|
||||
cpu_read(X"8000_0308");
|
||||
|
||||
cpu_read(X"9000_0208");
|
||||
cpu_read(X"9000_030C");
|
||||
cpu_read(X"9100_0310");
|
||||
cpu_read(X"9200_0314");
|
||||
|
||||
cpu_read(X"A000_020C");
|
||||
cpu_read(X"A000_0318");
|
||||
cpu_read(X"A100_031C");
|
||||
cpu_read(X"A200_0320");
|
||||
|
||||
cpu_read(X"B000_0210");
|
||||
cpu_read(X"B000_0324");
|
||||
cpu_read(X"B000_0328");
|
||||
cpu_read(X"B000_032C");
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
cpu_read(X"0000_1420");
|
||||
cpu_read(X"0000_2440");
|
||||
cpu_read(X"0000_3460");
|
||||
cpu_read(X"0000_4480");
|
||||
cpu_read(X"0000_54A0");
|
||||
cpu_read(X"0000_64C0");
|
||||
cpu_read(X"0000_74E0");
|
||||
cpu_read(X"0000_8500");
|
||||
cpu_read(X"0000_9520");
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
cpu_read(X"0000_1420");
|
||||
cpu_read(X"0000_2440");
|
||||
cpu_read(X"0000_3460");
|
||||
cpu_read(X"0000_4480");
|
||||
cpu_read(X"0000_54A0");
|
||||
cpu_read(X"0000_64C0");
|
||||
cpu_read(X"0000_74E0");
|
||||
cpu_write(X"0000_0400", X"AAAA_AAAA");
|
||||
|
||||
-- cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
|
||||
cpu_read(X"0000_0410");
|
||||
cpu_read(X"0000_0404");
|
||||
cpu_read(X"0000_0408");
|
||||
cpu_write(X"0000_0404", X"5555_5555");
|
||||
cpu_read(X"0000_0404");
|
||||
cpu_write(X"0000_0404", X"6666_6666");
|
||||
cpu_read(X"0000_0434");
|
||||
cpu_write(X"0000_0400", X"1111_1111");
|
||||
cpu_write(X"0000_0404", X"2222_2222");
|
||||
cpu_write(X"0000_0408", X"3333_3333");
|
||||
cpu_write(X"0000_040C", X"4444_4444");
|
||||
cpu_write(X"0000_0400", X"1111_1111");
|
||||
cpu_write(X"0000_0404", X"2222_2222");
|
||||
cpu_write(X"0000_0408", X"3333_3333");
|
||||
cpu_write(X"0000_040C", X"4444_4444");
|
||||
cpu_write(X"0000_0400", X"1111_1111");
|
||||
cpu_write(X"0000_0404", X"2222_2222");
|
||||
cpu_write(X"0000_0408", X"3333_3333");
|
||||
cpu_write(X"0000_040C", X"4444_4444");
|
||||
cpu_write(X"0000_0400", X"1111_1111");
|
||||
cpu_write(X"0000_0404", X"2222_2222");
|
||||
cpu_write(X"0000_0408", X"3333_3333");
|
||||
cpu_write(X"0000_040C", X"4444_4444");
|
||||
cpu_write(X"0000_0400", X"1111_1111");
|
||||
cpu_write(X"0000_0404", X"2222_2222");
|
||||
cpu_write(X"0000_0408", X"3333_3333");
|
||||
cpu_write(X"0000_040C", X"4444_4444");
|
||||
cpu_read(X"0000_0400");
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,363 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_icache IS
|
||||
END tb_icache;
|
||||
|
||||
ARCHITECTURE behavior OF tb_icache IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant TLB_NUM_ENTRIES : integer := 8;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal ce : std_logic := '1';
|
||||
|
||||
signal index_in : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_we : STD_LOGIC := '0';
|
||||
signal entry_lo_in : tlb_entry_lo_t;
|
||||
signal entry_hi_in : tlb_entry_hi_t;
|
||||
|
||||
signal index_out : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
|
||||
signal entry_re : STD_LOGIC := '0';
|
||||
signal entry_lo_out : tlb_entry_lo_t;
|
||||
signal entry_hi_out : tlb_entry_hi_t;
|
||||
|
||||
signal tlb_in : tlb_query_in_t;
|
||||
signal tlb_out : tlb_query_out_t;
|
||||
|
||||
signal tlb_index_hit : unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0);
|
||||
signal tlb_va : word_t := (others => '-');
|
||||
|
||||
signal tlb_pa : word_t;
|
||||
signal tlb_flags : tlb_flags_t;
|
||||
signal tlb_hit : STD_LOGIC;
|
||||
|
||||
-- CPU control/data
|
||||
signal cpu_en : STD_LOGIC := '0';
|
||||
signal cpu_we : STD_LOGIC := '0';
|
||||
signal cpu_be : unsigned(3 downto 0) := (others => '1');
|
||||
signal cpu_addr : word_t := (others => '-');
|
||||
signal cpu_dout : word_t;
|
||||
signal cpu_din : word_t := X"BFC0_BABE";
|
||||
signal cpu_rdy : STD_LOGIC;
|
||||
|
||||
-- Cache control
|
||||
signal icache_ctrl_in : cache_ctrl_t;
|
||||
|
||||
-- busmaster data
|
||||
signal bus_din : word_t := (others => '-');
|
||||
signal bus_din_rdy : std_logic := '0';
|
||||
signal bus_din_vld : std_logic := '0';
|
||||
|
||||
signal bus_dout : word_t := (others => '-');
|
||||
signal bus_dout_vld : std_logic := '0';
|
||||
signal bus_dout_rdy : std_logic := '0';
|
||||
|
||||
-- busmaster command
|
||||
signal bus_cmd_rdy : std_logic := '0';
|
||||
signal bus_cmd_we : std_logic := '0';
|
||||
signal bus_cmd_cycle_en : std_logic := '0';
|
||||
signal bus_cmd : bm_cmd_t;
|
||||
signal bus_cyc_complete : std_logic := '0';
|
||||
|
||||
signal cpu_din_reg : word_t;
|
||||
signal cpu_din_vld : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_tlb : entity work.tlb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => TLB_NUM_ENTRIES
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
ce => ce,
|
||||
|
||||
index_in => index_in,
|
||||
entry_we => entry_we,
|
||||
entry_lo_in => entry_lo_in,
|
||||
entry_hi_in => entry_hi_in,
|
||||
|
||||
index_out => index_out,
|
||||
entry_re => entry_re,
|
||||
entry_lo_out => entry_lo_out,
|
||||
entry_hi_out => entry_hi_out,
|
||||
|
||||
tlb_query_in => tlb_in,
|
||||
tlb_query_out => tlb_out
|
||||
);
|
||||
|
||||
icache_ctrl_in.inv_addr <= X"BEEF_BABE";
|
||||
icache_ctrl_in.inv_at <= '0';
|
||||
icache_ctrl_in.inv_all <= '0';
|
||||
|
||||
inst_icache: entity work.icache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => 1024,
|
||||
line_size => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
|
||||
-- CPU control/data
|
||||
en => cpu_en,
|
||||
addr => cpu_addr,
|
||||
dout => cpu_dout,
|
||||
rdy => cpu_rdy,
|
||||
|
||||
-- Cache control
|
||||
ctrl_in => icache_ctrl_in,
|
||||
tlb_query_in => tlb_out,
|
||||
tlb_query_out => tlb_in,
|
||||
|
||||
-- busmaster data
|
||||
bus_din => bus_din,
|
||||
bus_din_rdy => bus_din_rdy,
|
||||
bus_din_vld => bus_din_vld,
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_rdy => bus_cmd_rdy,
|
||||
bus_cmd_we => bus_cmd_we,
|
||||
bus_cmd_cycle_en => bus_cmd_cycle_en,
|
||||
bus_cmd_out => bus_cmd,
|
||||
bus_cyc_complete => bus_cyc_complete
|
||||
);
|
||||
|
||||
|
||||
inst_busmaster_sync : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => DATA_WIDTH,
|
||||
FIFO_DEPTH => 4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
|
||||
cmd_cycle_finished => bus_cyc_complete,
|
||||
cmd_cycle_en => bus_cmd_cycle_en,
|
||||
|
||||
cmd_rdy => bus_cmd_rdy,
|
||||
cmd_we => bus_cmd_we,
|
||||
cmd_in => bus_cmd,
|
||||
|
||||
din_rdy => bus_dout_rdy,
|
||||
din_we => bus_dout_vld,
|
||||
din => bus_dout,
|
||||
|
||||
dout => bus_din,
|
||||
dout_vld => bus_din_vld,
|
||||
dout_re => bus_din_rdy,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
inst_rom_wb: entity work.rom_wb
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- NUM_WORDS => 256
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => CLK,
|
||||
RST_I => RST,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
-- SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
-- DAT_I => MDAT_O,
|
||||
DAT_O => MDAT_I
|
||||
);
|
||||
|
||||
|
||||
cpu_din_register:
|
||||
process(clk)
|
||||
variable en2: std_logic;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cpu_din_vld <= '0';
|
||||
if en2 = '1' and cpu_rdy = '1' then
|
||||
cpu_din_reg <= cpu_dout;
|
||||
cpu_din_vld <= '1';
|
||||
end if;
|
||||
en2 := cpu_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
|
||||
begin
|
||||
|
||||
index_in <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
|
||||
|
||||
entry_hi_in.vpn <= vpn;
|
||||
entry_hi_in.asid <= asid;
|
||||
entry_hi_in.g <= g;
|
||||
|
||||
entry_lo_in.pfn <= pfn;
|
||||
entry_lo_in.n <= n;
|
||||
entry_lo_in.d <= d;
|
||||
entry_lo_in.v <= v;
|
||||
|
||||
entry_we <= '1';
|
||||
wait until rising_edge(CLK);
|
||||
entry_we <= '0';
|
||||
|
||||
end procedure cmd_entry_write;
|
||||
|
||||
procedure cpu_read(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cpu_we <= '0';
|
||||
cpu_addr <= addr;
|
||||
cpu_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
cpu_en <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
end procedure cpu_read;
|
||||
|
||||
procedure cpu_write(addr, data : unsigned) is
|
||||
begin
|
||||
|
||||
cpu_we <= '1';
|
||||
cpu_addr <= addr;
|
||||
cpu_din <= data;
|
||||
cpu_en <= '1';
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
cpu_en <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
end procedure cpu_write;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK) and cpu_rdy = '1';
|
||||
|
||||
cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(1, "110000", X"0000_1", X"11DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(2, "110000", X"0000_2", X"22DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(3, "110000", X"0000_3", X"33DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(4, "110000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(5, "110000", X"0000_5", X"55DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(6, "110000", X"0000_6", X"66DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(7, "110000", X"0000_7", X"77DE_F", '0', '0', '0', '1');
|
||||
|
||||
cpu_read(X"BFC0_0200");
|
||||
cpu_read(X"BFC0_0180");
|
||||
|
||||
cpu_read(X"8000_0204");
|
||||
cpu_read(X"8000_0300");
|
||||
cpu_read(X"8000_0304");
|
||||
cpu_read(X"8000_0308");
|
||||
|
||||
cpu_read(X"9000_0208");
|
||||
cpu_read(X"9000_030C");
|
||||
cpu_read(X"9100_0310");
|
||||
cpu_read(X"9200_0314");
|
||||
|
||||
cpu_read(X"A000_020C");
|
||||
cpu_read(X"A000_0318");
|
||||
cpu_read(X"A100_031C");
|
||||
cpu_read(X"A200_0320");
|
||||
|
||||
cpu_read(X"B000_0210");
|
||||
cpu_read(X"B000_0324");
|
||||
cpu_read(X"B000_0328");
|
||||
cpu_read(X"B000_032C");
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
cpu_read(X"0000_1420");
|
||||
cpu_read(X"0000_2440");
|
||||
cpu_read(X"0000_3460");
|
||||
cpu_read(X"0000_4480");
|
||||
cpu_read(X"0000_54A0");
|
||||
cpu_read(X"0000_64C0");
|
||||
cpu_read(X"0000_74E0");
|
||||
cpu_read(X"0000_8500");
|
||||
cpu_read(X"0000_9520");
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
cpu_read(X"0000_1420");
|
||||
cpu_read(X"0000_2440");
|
||||
cpu_read(X"0000_3460");
|
||||
cpu_read(X"0000_4480");
|
||||
cpu_read(X"0000_54A0");
|
||||
cpu_read(X"0000_64C0");
|
||||
cpu_read(X"0000_74E0");
|
||||
cpu_write(X"0000_0400", X"AAAA_AAAA");
|
||||
|
||||
-- cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
|
||||
|
||||
cpu_read(X"0000_0400");
|
||||
|
||||
cpu_read(X"0000_0410");
|
||||
cpu_read(X"0000_0404");
|
||||
cpu_read(X"0000_0408");
|
||||
cpu_write(X"0000_0404", X"5555_5555");
|
||||
cpu_read(X"0000_0404");
|
||||
cpu_read(X"0000_0400");
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,211 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_util_pkg.all;
|
||||
|
||||
ENTITY tb_tlb IS
|
||||
END tb_tlb;
|
||||
|
||||
ARCHITECTURE behavior OF tb_tlb IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
signal ce : std_logic := '1';
|
||||
|
||||
signal tlb_rdy : std_logic;
|
||||
|
||||
signal tlb_ctrl_in : tlb_ctrl_in_t;
|
||||
signal tlb_ctrl_out : tlb_ctrl_out_t;
|
||||
signal tlb_query_in : tlb_query_in_t;
|
||||
signal tlb_query_out : tlb_query_out_t;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_uut : entity work.tlb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_ENTRIES => TLB_NUM_ENTRIES,
|
||||
CACHE_KSEG1 => false,
|
||||
USE_TLB => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
ce => ce,
|
||||
|
||||
rdy => tlb_rdy,
|
||||
|
||||
ctrl_in => tlb_ctrl_in,
|
||||
ctrl_out => tlb_ctrl_out,
|
||||
|
||||
query_in => tlb_query_in,
|
||||
query_out => tlb_query_out
|
||||
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
|
||||
begin
|
||||
|
||||
tlb_ctrl_in.entry_wr_idx <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
|
||||
|
||||
tlb_ctrl_in.entry_hi.vpn <= vpn;
|
||||
tlb_ctrl_in.entry_hi.asid <= asid;
|
||||
|
||||
tlb_ctrl_in.entry_lo.pfn <= pfn;
|
||||
tlb_ctrl_in.entry_lo.g <= g;
|
||||
tlb_ctrl_in.entry_lo.n <= n;
|
||||
tlb_ctrl_in.entry_lo.d <= d;
|
||||
tlb_ctrl_in.entry_lo.v <= v;
|
||||
|
||||
tlb_ctrl_in.entry_we <= '1';
|
||||
wait until rising_edge(CLK_O) and tlb_rdy = '1';
|
||||
tlb_ctrl_in.entry_we <= '0';
|
||||
|
||||
end procedure cmd_entry_write;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
tlb_ctrl_in.entry_we <= '0';
|
||||
tlb_ctrl_in.entry_re <= '0';
|
||||
tlb_query_in.vld <= '0';
|
||||
tlb_query_in.write <= '0';
|
||||
tlb_query_in.vaddr <= X"BFC0_CAFE";
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O) and tlb_rdy = '1';
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
tlb_query_in.vaddr <= X"9FC0_CAFE";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
|
||||
cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(1, "110000", X"0000_1", X"01DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(2, "110000", X"0000_2", X"02DE_F", '0', '0', '0', '0');
|
||||
cmd_entry_write(3, "110000", X"0000_3", X"43DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(4, "100000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(5, "110000", X"0000_5", X"65DE_F", '0', '0', '0', '1');
|
||||
cmd_entry_write(6, "100000", X"0000_6", X"66DE_F", '1', '0', '0', '1');
|
||||
cmd_entry_write(7, "110000", X"0000_7", X"67DE_F", '0', '0', '0', '1');
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
|
||||
tlb_query_in.vaddr <= X"8000_BABE";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"8000_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"8100_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"8200_1234";
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"9000_BABE";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"9000_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"9100_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"9200_1234";
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"A000_BABE";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"A000_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"A100_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"A200_1234";
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"B000_BABE";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"B000_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"B100_1234";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"B200_1234";
|
||||
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= X"0000_0CAF";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
|
||||
cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
tlb_query_in.vaddr <= X"0000_0CAF";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
tlb_query_in.write <= '1';
|
||||
tlb_query_in.vaddr <= X"0008_0CAF";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '1';
|
||||
tlb_query_in.write <= '1';
|
||||
tlb_query_in.vaddr <= X"0000_0CAF";
|
||||
wait until rising_edge(CLK_O);
|
||||
tlb_query_in.vld <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -25,6 +25,7 @@
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
USE std.textio.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
@@ -41,8 +42,10 @@ ARCHITECTURE behavior OF tb_mips_top IS
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant SRAM_ADDR_WIDTH : integer := 17; -- bits
|
||||
constant FLASH_ADDR_WIDTH : integer := 17; -- bits
|
||||
|
||||
signal debug : chip_debug_t;
|
||||
constant WITH_TLB : boolean := true;
|
||||
constant KSEG_01_TRANSLATED : boolean := true;
|
||||
signal debug : chip_debug_t;
|
||||
signal tb_fin : STD_LOGIC := '0';
|
||||
|
||||
-- Master
|
||||
signal nmi : STD_LOGIC := '0';
|
||||
@@ -115,7 +118,43 @@ ARCHITECTURE behavior OF tb_mips_top IS
|
||||
type word_array_t is array (natural range <>) of unsigned(31 downto 0);
|
||||
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
|
||||
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
|
||||
|
||||
subtype nibble_t is unsigned (3 downto 0);
|
||||
|
||||
function to_character(x : nibble_t) return character is
|
||||
type cnv_tbl_t is array (0 to 15) of character;
|
||||
variable cnv_tbl : cnv_tbl_t := "0123456789ABCDEF";
|
||||
variable result : character;
|
||||
begin
|
||||
for i in nibble_t'low to nibble_t'high loop
|
||||
result := '0';
|
||||
if x(i) /= '0' and x(i) /= '1' then
|
||||
result := 'X';
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
if result = '0' then
|
||||
result := cnv_tbl(to_integer(x));
|
||||
end if;
|
||||
|
||||
return result;
|
||||
end to_character;
|
||||
|
||||
|
||||
function to_string(x : word_t ) return string is
|
||||
variable result : string (1 to 8);
|
||||
variable j : integer := 32;
|
||||
variable nibble : nibble_t;
|
||||
begin
|
||||
for i in 1 to 8 loop
|
||||
nibble := x(j-1 downto j-4);
|
||||
j := j - 4;
|
||||
result(i) := to_character(nibble);
|
||||
end loop;
|
||||
return result;
|
||||
|
||||
end to_string;
|
||||
|
||||
BEGIN
|
||||
|
||||
------------------------------------------------------------------
|
||||
@@ -128,6 +167,46 @@ CLK_GEN: process
|
||||
------------------------------------------------------------------
|
||||
-- Memory mux
|
||||
------------------------------------------------------------------
|
||||
-- rom_u : Virtual = 0xBFC00000, Physical = 0x1FC00000
|
||||
-- rom_c : Virtual = 0x9FC00000, Physical = 0x1FC00000
|
||||
|
||||
-- ram_u : Virtual = 0xA0000000, Physical = 0x00000000
|
||||
-- ram_c : Virtual = 0x80000000, Physical = 0x00000000
|
||||
-- flash_u : Virtual = 0xA4000000, Physical = 0x04000000
|
||||
-- flash_c : Virtual = 0x88000000, Physical = 0x08000000
|
||||
-- io_u : Virtual = 0xA8000000, Physical = 0x0C000000
|
||||
-- io_c : Virtual = 0x88000000, Physical = 0x0C000000
|
||||
|
||||
gen_mem_mux_translate:
|
||||
if KSEG_01_TRANSLATED = true generate
|
||||
mem_mux:
|
||||
process(ADDR_O)
|
||||
begin
|
||||
mem_area <= mem_dead;
|
||||
flash_page_mode_en <= '0';
|
||||
if ADDR_O(31 downto 28) = X"0" then
|
||||
if ADDR_O(27 downto 26) = "00" then
|
||||
mem_area <= mem_sram;
|
||||
elsif ADDR_O(27 downto 26) = "01" then
|
||||
mem_area <= mem_flash;
|
||||
elsif ADDR_O(27 downto 26) = "10" then
|
||||
mem_area <= mem_flash;
|
||||
flash_page_mode_en <= '1';
|
||||
elsif ADDR_O(27 downto 26) = "11" then
|
||||
if ADDR_O(18 downto 16) = "000" then
|
||||
mem_area <= mem_gpio;
|
||||
elsif ADDR_O(18 downto 16) = "001" then
|
||||
mem_area <= mem_uart;
|
||||
end if;
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"1" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_mem_mux_non_translate:
|
||||
if KSEG_01_TRANSLATED = false generate
|
||||
mem_mux:
|
||||
process(ADDR_O)
|
||||
begin
|
||||
@@ -152,6 +231,7 @@ mem_mux:
|
||||
mem_area <= mem_sram;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
signal_mux:
|
||||
process(mem_area, CYC_O)
|
||||
@@ -199,8 +279,10 @@ signal_mux:
|
||||
uut: entity work.mips_top
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => 1024, -- words
|
||||
dcache_size => 1024 -- words
|
||||
icache_size => 256, -- words
|
||||
dcache_size => 256, -- words
|
||||
WITH_TLB => WITH_TLB,
|
||||
TRANSLATE_KSEG0_1 => KSEG_01_TRANSLATED
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
@@ -394,14 +476,16 @@ SRAM_WRITE:
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------------
|
||||
FLASH_READ:
|
||||
process(rst, flash_cs_n, flash_oe_n, flash_a)
|
||||
type file_t is file of integer;
|
||||
-- file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
|
||||
file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
|
||||
-- file load_flash : file_t open read_mode is "test_dcache.flash.bin";
|
||||
-- file load_flash : file_t open read_mode is "test_tlb_sim.elf.flash.bin";
|
||||
file load_flash : file_t open read_mode is "test_exception_sim.elf.flash.bin";
|
||||
-- file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
|
||||
-- file load_flash : file_t open read_mode is "test_dcache_sim.elf.flash.bin";
|
||||
-- file load_flash : file_t open read_mode is "dhry.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
@@ -437,6 +521,62 @@ FLASH_READ:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
icache_trace_write:
|
||||
process(clk)
|
||||
type file_t is file of string;
|
||||
file f : file_t open write_mode is "icache_trace.dat";
|
||||
variable file_opened : std_logic;
|
||||
variable saddr : string(1 to 8);
|
||||
variable sdata : string(1 to 8);
|
||||
begin
|
||||
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
file_opened := '1';
|
||||
elsif file_opened = '1' then
|
||||
if debug.imem_din_vld = '1' then
|
||||
saddr := to_string(debug.imem_addr_reg);
|
||||
sdata := to_string(debug.imem_din_reg);
|
||||
write(f, saddr & " : " & sdata & CR);
|
||||
end if;
|
||||
else
|
||||
file_close(f);
|
||||
file_opened := '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
dcache_trace_write:
|
||||
process(clk)
|
||||
type file_t is file of string;
|
||||
file f : file_t open write_mode is "dcache_trace.dat";
|
||||
variable file_opened : std_logic;
|
||||
variable saddr : string(1 to 8);
|
||||
variable sdata : string(1 to 8);
|
||||
begin
|
||||
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
file_opened := '1';
|
||||
elsif file_opened = '1' then
|
||||
if debug.dmem_din_vld = '1' then
|
||||
saddr := to_string(debug.dmem_addr_reg);
|
||||
sdata := to_string(debug.dmem_din_reg);
|
||||
write(f, saddr & " : " & sdata & " R" & CR);
|
||||
elsif debug.dmem_dout_vld = '1' then
|
||||
saddr := to_string(debug.dmem_addr_reg);
|
||||
sdata := to_string(debug.dmem_dout_reg);
|
||||
write(f, saddr & " : " & sdata & " W" & CR);
|
||||
end if;
|
||||
else
|
||||
file_close(f);
|
||||
file_opened := '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
STIMULUS: process
|
||||
|
||||
@@ -446,12 +586,13 @@ STIMULUS: process
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
wait for 778254*CLK_PERIOD;
|
||||
|
||||
wait for 1200000*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk);
|
||||
nmi <= '0';
|
||||
wait for 3000*CLK_PERIOD;
|
||||
tb_fin <= '1';
|
||||
wait until rising_edge(clk);
|
||||
nmi <= '0';
|
||||
tb_fin <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/singleshot.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/ps2_port/src/ps2_core.vhd"
|
||||
vhdl work "../../../../lib/ps2_port/src/debounce.vhd"
|
||||
vhdl work "../../../../lib/misc/async_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
|
||||
vhdl work "../../src/clockgen_virtex4.vhd"
|
||||
vhdl work "../../src/async_defs.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "../../../../lib/ps2_port/src/ps2_wb.vhd"
|
||||
vhdl work "../../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/async_port_wb.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -0,0 +1,33 @@
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Match_cycle:Auto
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,62 @@
|
||||
set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp"
|
||||
set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst"
|
||||
run
|
||||
-ifn mips_sys.prj
|
||||
-ifmt mixed
|
||||
-ofn mips_sys
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top mips_sys
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso mips_sys.lso
|
||||
-keep_hierarchy NO
|
||||
-netlist_hierarchy as_optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing NO
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing Yes
|
||||
-move_first_stage YES
|
||||
-move_last_stage YES
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob true
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,47 @@
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\ps2_port\src\ps2_core.vhd"
|
||||
vhdl work "W:\vhdl\lib\ps2_port\src\debounce.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\ps2_port\src\ps2_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\ps2_port\src\ps2_phy_virtex.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
|
||||
@@ -0,0 +1,503 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_ssram_a<24> LOC = T21;
|
||||
NET sys_flash_ssram_a<23> LOC = U20;
|
||||
NET sys_flash_ssram_a<22> LOC = T19;
|
||||
NET sys_flash_ssram_a<21> LOC = AC5;
|
||||
NET sys_flash_ssram_a<20> LOC = AB5;
|
||||
NET sys_flash_ssram_a<19> LOC = AC4;
|
||||
NET sys_flash_ssram_a<18> LOC = AB4;
|
||||
NET sys_flash_ssram_a<17> LOC = AB3;
|
||||
NET sys_flash_ssram_a<16> LOC = AA4;
|
||||
NET sys_flash_ssram_a<15> LOC = AA3;
|
||||
NET sys_flash_ssram_a<14> LOC = W5;
|
||||
NET sys_flash_ssram_a<13> LOC = W6;
|
||||
NET sys_flash_ssram_a<12> LOC = W3;
|
||||
NET sys_flash_ssram_a<11> LOC = AF3;
|
||||
NET sys_flash_ssram_a<10> LOC = AE3;
|
||||
NET sys_flash_ssram_a<9> LOC = AD2;
|
||||
NET sys_flash_ssram_a<8> LOC = AD1;
|
||||
NET sys_flash_ssram_a<7> LOC = AC2;
|
||||
NET sys_flash_ssram_a<6> LOC = AC1;
|
||||
NET sys_flash_ssram_a<5> LOC = AB2;
|
||||
NET sys_flash_ssram_a<4> LOC = AB1;
|
||||
NET sys_flash_ssram_a<3> LOC = AA1;
|
||||
NET sys_flash_ssram_a<2> LOC = Y2;
|
||||
NET sys_flash_ssram_a<1> LOC = Y1;
|
||||
NET sys_flash_ssram_a<0> LOC = T20;
|
||||
NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_a<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_a<*> DRIVE = 8;
|
||||
|
||||
|
||||
NET sys_flash_ssram_d<31> LOC = F14;
|
||||
NET sys_flash_ssram_d<30> LOC = F13;
|
||||
NET sys_flash_ssram_d<29> LOC = F12;
|
||||
NET sys_flash_ssram_d<28> LOC = F11;
|
||||
NET sys_flash_ssram_d<27> LOC = F16;
|
||||
NET sys_flash_ssram_d<26> LOC = F15;
|
||||
NET sys_flash_ssram_d<25> LOC = D14;
|
||||
NET sys_flash_ssram_d<24> LOC = D13;
|
||||
NET sys_flash_ssram_d<23> LOC = D15;
|
||||
NET sys_flash_ssram_d<22> LOC = E14;
|
||||
NET sys_flash_ssram_d<21> LOC = C11;
|
||||
NET sys_flash_ssram_d<20> LOC = D11;
|
||||
NET sys_flash_ssram_d<19> LOC = D16;
|
||||
NET sys_flash_ssram_d<18> LOC = C16;
|
||||
NET sys_flash_ssram_d<17> LOC = E13;
|
||||
NET sys_flash_ssram_d<16> LOC = D12;
|
||||
NET sys_flash_ssram_d<15> LOC = AA14;
|
||||
NET sys_flash_ssram_d<14> LOC = AB14;
|
||||
NET sys_flash_ssram_d<13> LOC = AC12;
|
||||
NET sys_flash_ssram_d<12> LOC = AC11;
|
||||
NET sys_flash_ssram_d<11> LOC = AA16;
|
||||
NET sys_flash_ssram_d<10> LOC = AA15;
|
||||
NET sys_flash_ssram_d<9> LOC = AB13;
|
||||
NET sys_flash_ssram_d<8> LOC = AA13;
|
||||
NET sys_flash_ssram_d<7> LOC = AC14;
|
||||
NET sys_flash_ssram_d<6> LOC = AD14;
|
||||
NET sys_flash_ssram_d<5> LOC = AA12;
|
||||
NET sys_flash_ssram_d<4> LOC = AA11;
|
||||
NET sys_flash_ssram_d<3> LOC = AC16;
|
||||
NET sys_flash_ssram_d<2> LOC = AC15;
|
||||
NET sys_flash_ssram_d<1> LOC = AC13;
|
||||
NET sys_flash_ssram_d<0> LOC = AD13;
|
||||
NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_ssram_d<*> DRIVE = 12;
|
||||
NET sys_flash_ssram_d<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_ssram_oe_n LOC = AC6;
|
||||
NET sys_flash_ssram_oe_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_oe_n SLEW = FAST;
|
||||
NET sys_flash_ssram_oe_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ssram_we_n LOC = AB6;
|
||||
NET sys_flash_ssram_we_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_we_n SLEW = FAST;
|
||||
NET sys_flash_ssram_we_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten LOC = N22;
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# SSRAM
|
||||
NET sys_ssram_clk LOC = AF7;
|
||||
NET sys_ssram_clk IOSTANDARD = LVCMOS33;
|
||||
NET sys_ssram_clk DRIVE = 16;
|
||||
NET sys_ssram_clk SLEW = FAST;
|
||||
|
||||
NET "sys_ssram_clk" TNM_NET = "ssram_clk";
|
||||
#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
|
||||
NET sys_ssram_clk_fb LOC = AD17;
|
||||
NET sys_ssram_clk_fb IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Timing Constraint for Feedback Clock
|
||||
NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
|
||||
|
||||
NET sys_ssram_ce_n LOC = V7;
|
||||
NET sys_ssram_ce_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_ce_n SLEW = FAST;
|
||||
NET sys_ssram_ce_n DRIVE = 8;
|
||||
|
||||
NET sys_ssram_bw_n<3> LOC = Y3; #Y4;
|
||||
NET sys_ssram_bw_n<2> LOC = Y4; #Y3;
|
||||
NET sys_ssram_bw_n<1> LOC = Y5; #Y6;
|
||||
NET sys_ssram_bw_n<0> LOC = Y6; #Y5;
|
||||
NET sys_ssram_bw_n<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_bw_n<*> SLEW = FAST;
|
||||
NET sys_ssram_bw_n<*> DRIVE = 8;
|
||||
|
||||
NET sys_ssram_adv LOC = W4;
|
||||
NET sys_ssram_adv IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_adv SLEW = FAST;
|
||||
NET sys_ssram_adv DRIVE = 8;
|
||||
|
||||
NET sys_ssram_mode LOC = V26;
|
||||
NET sys_ssram_mode IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_mode SLEW = FAST;
|
||||
NET sys_ssram_mode DRIVE = 8;
|
||||
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
@@ -0,0 +1,629 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "CLK_O" TNM_NET = "sys_clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET "sdram_clk0" TNM_NET = "sdram_clk";
|
||||
TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
|
||||
|
||||
NET "vga_clk" TNM_NET = "vga_clk";
|
||||
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
|
||||
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
|
||||
|
||||
NET "cpu_clk" TNM_NET = "cpu_clk";
|
||||
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
|
||||
#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "RST_O" TIG;
|
||||
|
||||
#NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
#PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
#NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
#PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4;
|
||||
#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3;
|
||||
|
||||
# ---------------------------------------------------------------------------------
|
||||
# Floor planning
|
||||
# ---------------------------------------------------------------------------------
|
||||
#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ;
|
||||
#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ;
|
||||
#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ;
|
||||
|
||||
#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ;
|
||||
#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ;
|
||||
|
||||
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
|
||||
# GOOD 1
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
|
||||
|
||||
# GOOD 2 (smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
|
||||
|
||||
# GOOD 3 (even smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
|
||||
|
||||
# GOOD 4 (even more smaller)
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
|
||||
|
||||
# TEMP 4
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y54:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
|
||||
|
||||
# TEMP 4.1
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y55:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_uart0_rx LOC = W2;
|
||||
NET sys_uart0_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart0_rx TIG;
|
||||
NET sys_uart0_tx LOC = W1;
|
||||
NET sys_uart0_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart0_tx TIG;
|
||||
|
||||
NET sys_uart1_rx LOC = AF24;
|
||||
NET sys_uart1_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart1_rx TIG;
|
||||
NET sys_uart1_tx LOC = AE24;
|
||||
NET sys_uart1_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart1_tx TIG;
|
||||
|
||||
NET sys_uart2_rx LOC = AD22;
|
||||
NET sys_uart2_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart2_rx TIG;
|
||||
NET sys_uart2_tx LOC = AB21;
|
||||
NET sys_uart2_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart2_tx TIG;
|
||||
|
||||
NET sys_uart3_rx LOC = W20;
|
||||
NET sys_uart3_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart3_rx TIG;
|
||||
NET sys_uart3_tx LOC = W21;
|
||||
NET sys_uart3_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_uart3_tx TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
NET sys_usb_d<*> IOBDELAY = NONE;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_a<24> LOC = T21;
|
||||
NET sys_flash_a<23> LOC = U20;
|
||||
NET sys_flash_a<22> LOC = T19;
|
||||
NET sys_flash_a<21> LOC = AC5;
|
||||
NET sys_flash_a<20> LOC = AB5;
|
||||
NET sys_flash_a<19> LOC = AC4;
|
||||
NET sys_flash_a<18> LOC = AB4;
|
||||
NET sys_flash_a<17> LOC = AB3;
|
||||
NET sys_flash_a<16> LOC = AA4;
|
||||
NET sys_flash_a<15> LOC = AA3;
|
||||
NET sys_flash_a<14> LOC = W5;
|
||||
NET sys_flash_a<13> LOC = W6;
|
||||
NET sys_flash_a<12> LOC = W3;
|
||||
NET sys_flash_a<11> LOC = AF3;
|
||||
NET sys_flash_a<10> LOC = AE3;
|
||||
NET sys_flash_a<9> LOC = AD2;
|
||||
NET sys_flash_a<8> LOC = AD1;
|
||||
NET sys_flash_a<7> LOC = AC2;
|
||||
NET sys_flash_a<6> LOC = AC1;
|
||||
NET sys_flash_a<5> LOC = AB2;
|
||||
NET sys_flash_a<4> LOC = AB1;
|
||||
NET sys_flash_a<3> LOC = AA1;
|
||||
NET sys_flash_a<2> LOC = Y2;
|
||||
NET sys_flash_a<1> LOC = Y1;
|
||||
NET sys_flash_a<0> LOC = T20;
|
||||
|
||||
NET sys_flash_d<31> LOC = F14;
|
||||
NET sys_flash_d<30> LOC = F13;
|
||||
NET sys_flash_d<29> LOC = F12;
|
||||
NET sys_flash_d<28> LOC = F11;
|
||||
NET sys_flash_d<27> LOC = F16;
|
||||
NET sys_flash_d<26> LOC = F15;
|
||||
NET sys_flash_d<25> LOC = D14;
|
||||
NET sys_flash_d<24> LOC = D13;
|
||||
NET sys_flash_d<23> LOC = D15;
|
||||
NET sys_flash_d<22> LOC = E14;
|
||||
NET sys_flash_d<21> LOC = C11;
|
||||
NET sys_flash_d<20> LOC = D11;
|
||||
NET sys_flash_d<19> LOC = D16;
|
||||
NET sys_flash_d<18> LOC = C16;
|
||||
NET sys_flash_d<17> LOC = E13;
|
||||
NET sys_flash_d<16> LOC = D12;
|
||||
NET sys_flash_d<15> LOC = AA14;
|
||||
NET sys_flash_d<14> LOC = AB14;
|
||||
NET sys_flash_d<13> LOC = AC12;
|
||||
NET sys_flash_d<12> LOC = AC11;
|
||||
NET sys_flash_d<11> LOC = AA16;
|
||||
NET sys_flash_d<10> LOC = AA15;
|
||||
NET sys_flash_d<9> LOC = AB13;
|
||||
NET sys_flash_d<8> LOC = AA13;
|
||||
NET sys_flash_d<7> LOC = AC14;
|
||||
NET sys_flash_d<6> LOC = AD14;
|
||||
NET sys_flash_d<5> LOC = AA12;
|
||||
NET sys_flash_d<4> LOC = AA11;
|
||||
NET sys_flash_d<3> LOC = AC16;
|
||||
NET sys_flash_d<2> LOC = AC15;
|
||||
NET sys_flash_d<1> LOC = AC13;
|
||||
NET sys_flash_d<0> LOC = AD13;
|
||||
NET sys_flash_rdn LOC = AC6;
|
||||
NET sys_flash_wrn LOC = AB6;
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_ac97_rstn LOC = AD10;
|
||||
NET sys_flash_byten LOC = N22;
|
||||
|
||||
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_a<*> SLEW = FAST;
|
||||
NET sys_flash_a<*> DRIVE = 8;
|
||||
|
||||
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_d<*> DRIVE = 12;
|
||||
NET sys_flash_d<*> SLEW = FAST;
|
||||
NET sys_flash_d<*> IOBDELAY = NONE;
|
||||
NET sys_flash_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_rdn SLEW = FAST;
|
||||
NET sys_flash_rdn DRIVE = 8;
|
||||
|
||||
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_wrn SLEW = FAST;
|
||||
NET sys_flash_wrn DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_ac97_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_ac97_rstn DRIVE = 8;
|
||||
NET sys_flash_ac97_rstn SLEW = FAST;
|
||||
NET sys_flash_ac97_rstn TIG;
|
||||
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for AC97 Sound Controller
|
||||
#------------------------------------------------------------------------------
|
||||
NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk";
|
||||
TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
|
||||
|
||||
NET sys_ac97_bit_clk LOC = AE10;
|
||||
NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33;
|
||||
NET sys_ac97_bit_clk PERIOD = 80;
|
||||
NET sys_ac97_sdata_in LOC = AD16;
|
||||
NET sys_ac97_sdata_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_ac97_sdata_out LOC = C8;
|
||||
NET sys_ac97_sdata_out SLEW = FAST;
|
||||
NET sys_ac97_ssync LOC = D9;
|
||||
NET sys_ac97_ssync SLEW = FAST;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for PS/2 Ports
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#Keyboard
|
||||
NET sys_ps2_0_clk LOC = D2;
|
||||
NET sys_ps2_0_clk SLEW = SLOW;
|
||||
NET sys_ps2_0_clk DRIVE = 2;
|
||||
NET sys_ps2_0_clk TIG;
|
||||
NET sys_ps2_0_data LOC = G9;
|
||||
NET sys_ps2_0_data SLEW = SLOW;
|
||||
NET sys_ps2_0_data DRIVE = 2;
|
||||
NET sys_ps2_0_data TIG;
|
||||
|
||||
#Mouse
|
||||
NET sys_ps2_1_clk LOC = B14;
|
||||
NET sys_ps2_1_clk SLEW = SLOW;
|
||||
NET sys_ps2_1_clk DRIVE = 2;
|
||||
NET sys_ps2_1_clk TIG;
|
||||
NET sys_ps2_1_data LOC = C14;
|
||||
NET sys_ps2_1_data SLEW = SLOW;
|
||||
NET sys_ps2_1_data DRIVE = 2;
|
||||
NET sys_ps2_1_data TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for Ethernet PHY
|
||||
#------------------------------------------------------------------------------
|
||||
# MDC
|
||||
Net sys_phy_mdc LOC = D1;
|
||||
Net sys_phy_mdc IOSTANDARD = LVCMOS25;
|
||||
|
||||
# MDIO
|
||||
Net sys_phy_mdio LOC = G4;
|
||||
Net sys_phy_mdio IOSTANDARD = LVCMOS25;
|
||||
|
||||
# /RST
|
||||
Net sys_phy_rstn LOC = D10;
|
||||
Net sys_phy_rstn TIG;
|
||||
|
||||
# INT
|
||||
Net sys_phy_int LOC = H4;
|
||||
Net sys_phy_int TIG;
|
||||
|
||||
#### Module Ethernet_MAC constraints
|
||||
|
||||
NET "sys_phy_tx_clk" TNM_NET = "phy_tx_clk";
|
||||
TIMESPEC "TS_phy_tx_clk" = PERIOD "phy_tx_clk" 8.0 ns HIGH 50 %;
|
||||
|
||||
NET "sys_phy_rx_clk" TNM_NET = "phy_rx_clk";
|
||||
TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk" 8.0 ns HIGH 50 %;
|
||||
|
||||
Net sys_phy_crs LOC = D5;
|
||||
Net sys_phy_col LOC = E3;
|
||||
|
||||
Net sys_phy_tx_clk LOC=C15;
|
||||
Net sys_phy_tx_en LOC = F4;
|
||||
Net sys_phy_tx_er LOC=F3;
|
||||
Net sys_phy_gtx_clk LOC=G10;
|
||||
|
||||
Net sys_phy_rx_clk LOC=B15;
|
||||
Net sys_phy_rx_dv LOC=A9;
|
||||
Net sys_phy_rx_er LOC=B9;
|
||||
|
||||
Net sys_phy_tx<0> LOC=H1;
|
||||
Net sys_phy_tx<1> LOC=H2;
|
||||
Net sys_phy_tx<2> LOC=H3;
|
||||
Net sys_phy_tx<3> LOC=G1;
|
||||
Net sys_phy_tx<4> LOC=G2;
|
||||
Net sys_phy_tx<5> LOC=H5;
|
||||
Net sys_phy_tx<6> LOC=H6;
|
||||
Net sys_phy_tx<7> LOC=G3;
|
||||
|
||||
Net sys_phy_rx<0> LOC=F1;
|
||||
Net sys_phy_rx<1> LOC=E1;
|
||||
Net sys_phy_rx<2> LOC=D4;
|
||||
Net sys_phy_rx<3> LOC=C4;
|
||||
Net sys_phy_rx<4> LOC=B4;
|
||||
Net sys_phy_rx<5> LOC=A4;
|
||||
Net sys_phy_rx<6> LOC=B3;
|
||||
Net sys_phy_rx<7> LOC=A3;
|
||||
@@ -0,0 +1,43 @@
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vhdl work "../../src/sys_types.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/ram_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/async_port_wb.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -0,0 +1,43 @@
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
|
||||
@@ -0,0 +1,469 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
# GOOD
|
||||
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_a<24> LOC = T21;
|
||||
NET sys_flash_a<23> LOC = U20;
|
||||
NET sys_flash_a<22> LOC = T19;
|
||||
NET sys_flash_a<21> LOC = AC5;
|
||||
NET sys_flash_a<20> LOC = AB5;
|
||||
NET sys_flash_a<19> LOC = AC4;
|
||||
NET sys_flash_a<18> LOC = AB4;
|
||||
NET sys_flash_a<17> LOC = AB3;
|
||||
NET sys_flash_a<16> LOC = AA4;
|
||||
NET sys_flash_a<15> LOC = AA3;
|
||||
NET sys_flash_a<14> LOC = W5;
|
||||
NET sys_flash_a<13> LOC = W6;
|
||||
NET sys_flash_a<12> LOC = W3;
|
||||
NET sys_flash_a<11> LOC = AF3;
|
||||
NET sys_flash_a<10> LOC = AE3;
|
||||
NET sys_flash_a<9> LOC = AD2;
|
||||
NET sys_flash_a<8> LOC = AD1;
|
||||
NET sys_flash_a<7> LOC = AC2;
|
||||
NET sys_flash_a<6> LOC = AC1;
|
||||
NET sys_flash_a<5> LOC = AB2;
|
||||
NET sys_flash_a<4> LOC = AB1;
|
||||
NET sys_flash_a<3> LOC = AA1;
|
||||
NET sys_flash_a<2> LOC = Y2;
|
||||
NET sys_flash_a<1> LOC = Y1;
|
||||
NET sys_flash_a<0> LOC = T20;
|
||||
|
||||
NET sys_flash_d<31> LOC = F14;
|
||||
NET sys_flash_d<30> LOC = F13;
|
||||
NET sys_flash_d<29> LOC = F12;
|
||||
NET sys_flash_d<28> LOC = F11;
|
||||
NET sys_flash_d<27> LOC = F16;
|
||||
NET sys_flash_d<26> LOC = F15;
|
||||
NET sys_flash_d<25> LOC = D14;
|
||||
NET sys_flash_d<24> LOC = D13;
|
||||
NET sys_flash_d<23> LOC = D15;
|
||||
NET sys_flash_d<22> LOC = E14;
|
||||
NET sys_flash_d<21> LOC = C11;
|
||||
NET sys_flash_d<20> LOC = D11;
|
||||
NET sys_flash_d<19> LOC = D16;
|
||||
NET sys_flash_d<18> LOC = C16;
|
||||
NET sys_flash_d<17> LOC = E13;
|
||||
NET sys_flash_d<16> LOC = D12;
|
||||
NET sys_flash_d<15> LOC = AA14;
|
||||
NET sys_flash_d<14> LOC = AB14;
|
||||
NET sys_flash_d<13> LOC = AC12;
|
||||
NET sys_flash_d<12> LOC = AC11;
|
||||
NET sys_flash_d<11> LOC = AA16;
|
||||
NET sys_flash_d<10> LOC = AA15;
|
||||
NET sys_flash_d<9> LOC = AB13;
|
||||
NET sys_flash_d<8> LOC = AA13;
|
||||
NET sys_flash_d<7> LOC = AC14;
|
||||
NET sys_flash_d<6> LOC = AD14;
|
||||
NET sys_flash_d<5> LOC = AA12;
|
||||
NET sys_flash_d<4> LOC = AA11;
|
||||
NET sys_flash_d<3> LOC = AC16;
|
||||
NET sys_flash_d<2> LOC = AC15;
|
||||
NET sys_flash_d<1> LOC = AC13;
|
||||
NET sys_flash_d<0> LOC = AD13;
|
||||
NET sys_flash_rdn LOC = AC6;
|
||||
NET sys_flash_wrn LOC = AB6;
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_byten LOC = N22;
|
||||
|
||||
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_a<*> SLEW = FAST;
|
||||
NET sys_flash_a<*> DRIVE = 8;
|
||||
|
||||
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_d<*> DRIVE = 12;
|
||||
NET sys_flash_d<*> SLEW = FAST;
|
||||
NET sys_flash_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_rdn SLEW = FAST;
|
||||
NET sys_flash_rdn DRIVE = 8;
|
||||
|
||||
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_wrn SLEW = FAST;
|
||||
NET sys_flash_wrn DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
@@ -0,0 +1,123 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
# Configs
|
||||
vcom -explicit -93 "../src/sdram_config_sim.vhd"
|
||||
|
||||
# Packages
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_util_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../../../lib/JBUS/src/busmaster_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
|
||||
|
||||
# RAMs
|
||||
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd"
|
||||
vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd"
|
||||
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ra_sim.vhd"
|
||||
#vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
|
||||
|
||||
# CPU
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cam.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_tlb.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../../../lib/JBUS/src/busmaster_async.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
|
||||
|
||||
# VGA
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
|
||||
# UART
|
||||
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
|
||||
|
||||
# PS2
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
|
||||
|
||||
# GPIO
|
||||
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
|
||||
|
||||
# LCD
|
||||
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
|
||||
|
||||
# Flash and USB
|
||||
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs_sim.vhd"
|
||||
|
||||
# Sync SRAM
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
|
||||
|
||||
# SDRAM
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
|
||||
# AC-97
|
||||
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
|
||||
|
||||
# Ethernet MAC
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
|
||||
|
||||
# Clock Generator
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
|
||||
# Top and TB
|
||||
vcom -explicit -93 "../src/mips_sys_sim.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_sys.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_mips_sys
|
||||
do {tb_mips_sys.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10 ms
|
||||
@@ -0,0 +1,404 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
|
||||
add wave -noupdate -format Literal /tb_mips_sys/dip
|
||||
add wave -noupdate -format Literal /tb_mips_sys/btn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/led
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
|
||||
add wave -noupdate -format Logic /tb_mips_sys/refresh
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_error
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -divider {Clock Gen}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
|
||||
add wave -noupdate -divider Arbiter
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
|
||||
add wave -noupdate -divider {Ethernet MAC}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
|
||||
add wave -noupdate -divider AC97
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/ac_synced
|
||||
add wave -noupdate -divider {CPU Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
|
||||
add wave -noupdate -divider {VGA Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
|
||||
add wave -noupdate -divider BUI
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle
|
||||
add wave -noupdate -divider VGA-Slave
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/rst_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/clk_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/int_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/cyc_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/srdy_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/mrdy_i
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/sel_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/we_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/stb_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/addr_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/ack_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_dst
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_dst
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_ny
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_const_color
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_func
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_const_color_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request_set
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_ack
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_ack
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_en
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_din
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_avail
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_dst
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_dst
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_nx
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_ny
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_cc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_func
|
||||
add wave -noupdate -divider USB
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
|
||||
add wave -noupdate -divider Flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
|
||||
add wave -noupdate -divider {Sync SRAM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
|
||||
add wave -noupdate -divider {MIPS TOP}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
|
||||
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
|
||||
add wave -noupdate -divider {CPU DMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -divider {CPU IMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -divider {User ROM}
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
|
||||
add wave -noupdate -divider I-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tlb_query_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tlb_query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/debug
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index
|
||||
add wave -noupdate -divider D-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tlb_query_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tlb_query_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/debug
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {4787725085 ps} 0} {{Cursor 100} {539632527 ps} 0} {{Cursor 3} {11823240 ps} 0}
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {11675145 ps} {12107788 ps}
|
||||
@@ -0,0 +1,116 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
# Configs
|
||||
vcom -explicit -93 "../src/sdram_config_sim.vhd"
|
||||
|
||||
# Packages
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
|
||||
|
||||
# RAMs
|
||||
vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
|
||||
|
||||
# CPU
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
|
||||
|
||||
# VGA
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
|
||||
# UART
|
||||
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
|
||||
|
||||
# PS2
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
|
||||
vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
|
||||
|
||||
# GPIO
|
||||
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
|
||||
|
||||
# LCD
|
||||
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
|
||||
|
||||
# Flash and USB
|
||||
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs_sim.vhd"
|
||||
|
||||
# Sync SRAM
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
|
||||
|
||||
# SDRAM
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
|
||||
# AC-97
|
||||
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
|
||||
|
||||
# Ethernet MAC
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/piso.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/sipo.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/crc32.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
|
||||
|
||||
# Clock Generator
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
|
||||
# Top and TB
|
||||
vcom -explicit -93 "../src/mips_sys_sim.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_sys.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_mips_sys
|
||||
do {tb_mips_sys_emac.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 40 ms
|
||||
@@ -0,0 +1,185 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
|
||||
add wave -noupdate -format Literal /tb_mips_sys/dip
|
||||
add wave -noupdate -format Literal /tb_mips_sys/btn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/led
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_dv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_er
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_er
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_gtx_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_crs
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_phy_col
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
|
||||
add wave -noupdate -format Logic /tb_mips_sys/refresh
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_error
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -divider {Clock Gen}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
|
||||
add wave -noupdate -divider Arbiter
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
|
||||
add wave -noupdate -divider {Ethernet MAC}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
|
||||
add wave -noupdate -divider {EMAC TX}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_out
|
||||
add wave -noupdate -divider {EMAC RX}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_out
|
||||
add wave -noupdate -divider {CPU Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
|
||||
add wave -noupdate -divider Flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
|
||||
add wave -noupdate -divider {MIPS TOP}
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_addr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_din
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_dout
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
|
||||
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {2312967085 ps} 0} {{Cursor 100} {4871595869 ps} 0} {{Cursor 3} {4495154370 ps} 0} {{Cursor 7} {6077658830 ps} 0}
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {41227735500 ps}
|
||||
@@ -0,0 +1,4 @@
|
||||
VHDL/projects/mips_sys/src/async_defs.vhd
|
||||
|
||||
VHDL/projects/mips_sys/src/sys_types.vhd
|
||||
VHDL/projects/mips_sys/src/async_defs.vhd
|
||||
@@ -0,0 +1,70 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: MIPS System controller
|
||||
-- This file:
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.async_types.all;
|
||||
|
||||
package async_defs is
|
||||
|
||||
constant ts_flash : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 10.0,
|
||||
T_pulse_rd => 120.0,
|
||||
T_pulse_wr => 70.0,
|
||||
T_leadout => 10.0,
|
||||
T_release => 40.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 30.0,
|
||||
can_page_rd => true,
|
||||
nbits_page_rd => 4,
|
||||
pol_cs => '1',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
constant ts_usb : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 10.0,
|
||||
T_pulse_rd => 60.0,
|
||||
T_pulse_wr => 60.0,
|
||||
T_leadout => 10.0,
|
||||
T_release => 80.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 00.0,
|
||||
can_page_rd => false,
|
||||
nbits_page_rd => 0,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end async_defs;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,363 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: Clock generator (Virtex-4 specific)
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee, work;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
USE WORK.utils_pkg.ALL;
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity clockgen is
|
||||
generic
|
||||
(
|
||||
clk_in_freq : real := 100.0;
|
||||
cpu_clk_out_freq : real := 100.0;
|
||||
vga_clk_out_freq : real := 100.0;
|
||||
sdr0_clk_out_phaseshift : integer := 0;
|
||||
sdr1_clk_out_phaseshift : integer := 0
|
||||
);
|
||||
port
|
||||
(
|
||||
-- Clocks and Reset
|
||||
rst_in : in std_logic; -- external async reset, low active
|
||||
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
|
||||
sys_clk_out : out std_logic;
|
||||
cpu_clk_out : out std_logic;
|
||||
vga_clk_out : out std_logic;
|
||||
sdr0_clk_fb_in : in std_logic; -- feedback clock
|
||||
sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
|
||||
sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
|
||||
sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
|
||||
sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
|
||||
sys_rst_out : out std_logic -- DCM locked status
|
||||
);
|
||||
end;
|
||||
|
||||
architecture tech of clockgen is
|
||||
|
||||
signal dcm_rst : unsigned(2 downto 0);
|
||||
signal vga_clk0 : std_logic;
|
||||
signal vga_clkfx : std_logic;
|
||||
signal vga_clk0_bufg : std_logic;
|
||||
signal sys_clk0 : std_logic;
|
||||
signal sys_clk0_bufg : std_logic;
|
||||
signal cpu_clkfx : std_logic;
|
||||
signal cpu_clkfx_bufg : std_logic;
|
||||
signal sdr0_clk0 : std_logic;
|
||||
signal sdr0_clk270 : std_logic;
|
||||
signal sdr1_clk0 : std_logic;
|
||||
signal sdr1_clk270 : std_logic;
|
||||
signal sdr1_clk0_bufg : std_logic;
|
||||
signal reset_cnt : unsigned(4 downto 0);
|
||||
signal reset_pipe0 : unsigned(19 downto 0);
|
||||
signal reset_pipe1 : unsigned(19 downto 0);
|
||||
signal reset_pipe2 : unsigned(19 downto 0);
|
||||
signal vga_fx_lock : std_logic;
|
||||
signal sys_fx_lock : std_logic;
|
||||
signal sdr0_lock : std_logic;
|
||||
signal sdr1_lock : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
-- Clock generation
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- Compnent instantiation
|
||||
inst_DCM_VGA_FX : DCM_BASE
|
||||
generic map
|
||||
(
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
)
|
||||
port map
|
||||
(
|
||||
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => open, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => vga_fx_lock, -- DCM LOCK status output
|
||||
CLKFB => vga_clk0_bufg, -- DCM clock feedback
|
||||
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(0) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
BUFG_vga_clk0 : BUFG
|
||||
port map
|
||||
(
|
||||
O => vga_clk0_bufg, -- Clock buffer output
|
||||
I => vga_clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
BUFG_vga_clkfx : BUFG
|
||||
port map
|
||||
(
|
||||
O => vga_clk_out, -- Clock buffer output
|
||||
I => vga_clkfx -- Clock buffer input
|
||||
);
|
||||
|
||||
-- Compnent instantiation
|
||||
inst_DCM_CPU_FX : DCM_BASE
|
||||
generic map
|
||||
(
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
)
|
||||
port map
|
||||
(
|
||||
CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => open, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => sys_fx_lock, -- DCM LOCK status output
|
||||
CLKFB => sys_clk0_bufg, -- DCM clock feedback
|
||||
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(0) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
BUFG_sys_clk0 : BUFG
|
||||
port map
|
||||
(
|
||||
O => sys_clk0_bufg, -- Clock buffer output
|
||||
I => sys_clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
BUFG_sys_clkfx : BUFG
|
||||
port map
|
||||
(
|
||||
O => cpu_clkfx_bufg, -- Clock buffer output
|
||||
I => cpu_clkfx -- Clock buffer input
|
||||
);
|
||||
|
||||
sys_clk_out <= sys_clk0_bufg;
|
||||
cpu_clk_out <= cpu_clkfx_bufg;
|
||||
|
||||
inst_DCM_SDRCLK_0 : DCM_BASE
|
||||
generic map
|
||||
(
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
)
|
||||
port map
|
||||
(
|
||||
CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => sdr0_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => sdr0_lock, -- DCM LOCK status output
|
||||
CLKFB => sdr0_clk_fb_in, -- DCM clock feedback
|
||||
CLKIN => sys_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(1) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
bufg_sdr0_clk0: bufg
|
||||
port map
|
||||
(
|
||||
o => sdr0_clk0_out,
|
||||
i => sdr0_clk0
|
||||
);
|
||||
|
||||
bufg_sdr0_clk270: bufg
|
||||
port map (
|
||||
o => sdr0_clk270_out,
|
||||
i => sdr0_clk270
|
||||
);
|
||||
|
||||
inst_DCM_SDRCLK_1 : DCM_BASE
|
||||
generic map
|
||||
(
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
)
|
||||
port map
|
||||
(
|
||||
CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => sdr1_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => sdr1_lock, -- DCM LOCK status output
|
||||
CLKFB => sdr1_clk0_bufg, -- DCM clock feedback
|
||||
CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(2) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
sdr1_clk0_out <= sdr1_clk0_bufg;
|
||||
|
||||
bufg_sdr1_clk0: bufg
|
||||
port map
|
||||
(
|
||||
o => sdr1_clk0_bufg,
|
||||
i => sdr1_clk0
|
||||
);
|
||||
|
||||
|
||||
bufg_sdr1_clk270: bufg
|
||||
port map (
|
||||
o => sdr1_clk270_out,
|
||||
i => sdr1_clk270
|
||||
);
|
||||
|
||||
dcm_rst(0) <= reset_pipe0(reset_pipe0'left);
|
||||
|
||||
dcm_reset0:
|
||||
process(rst_in, clk_in)
|
||||
begin
|
||||
if rst_in = '1' then
|
||||
reset_pipe0 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
dcm_rst(1) <= reset_pipe1(reset_pipe1'left);
|
||||
|
||||
dcm_reset1:
|
||||
process(vga_fx_lock, clk_in)
|
||||
begin
|
||||
if vga_fx_lock = '0' then
|
||||
reset_pipe1 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
dcm_rst(2) <= reset_pipe2(reset_pipe2'left);
|
||||
|
||||
dcm_reset2:
|
||||
process(sdr0_lock, clk_in)
|
||||
begin
|
||||
if sdr0_lock = '0' then
|
||||
reset_pipe2 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
reset_out_logic:
|
||||
process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock)
|
||||
begin
|
||||
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
|
||||
sys_rst_out <= '1';
|
||||
reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
|
||||
reset_cnt <= reset_cnt - 1;
|
||||
else
|
||||
sys_rst_out <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture tech;
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,173 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
ENTITY ram IS
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
COMPONENT dpram_2w2r
|
||||
Generic
|
||||
(
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal jtag_clk : STD_LOGIC;
|
||||
signal jtag_we : unsigned(3 downto 0);
|
||||
signal jtag_addr : unsigned (15 downto 0);
|
||||
signal jtag_dout : unsigned (31 downto 0);
|
||||
signal jtag_din : unsigned (31 downto 0);
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
gen_sram:
|
||||
for i in 0 to 3 generate
|
||||
begin
|
||||
inst_dpram_2w2r : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 11,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
en_a => ce,
|
||||
we_a => we(i),
|
||||
addr_a => addr(12 downto 2),
|
||||
din_a => din((i+1)*8-1 downto i*8),
|
||||
dout_a => dout((i+1)*8-1 downto i*8),
|
||||
|
||||
clk_b => jtag_clk,
|
||||
en_b => jtag_we(i),
|
||||
we_b => jtag_we(i),
|
||||
addr_b => jtag_addr(10 downto 0),
|
||||
din_b => jtag_din((i+1)*8-1 downto i*8),
|
||||
dout_b => jtag_dout((i+1)*8-1 downto i*8)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_addr <= user_regi(user_regi'left downto jtag_dout'length);
|
||||
jtag_din <= user_regi(jtag_dout'length-1 downto 0);
|
||||
jtag_clk <= bs_update1;
|
||||
jtag_we <= (3 downto 0 => bs_sel);
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -0,0 +1,88 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY ram IS
|
||||
Generic
|
||||
(
|
||||
word_addr_width : integer := 6
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
constant depth : natural := 2**word_addr_width;
|
||||
|
||||
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
|
||||
|
||||
function sram_clear return sram_t is
|
||||
|
||||
variable result : sram_t;
|
||||
begin
|
||||
for i in 0 to sram_t'length-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end sram_clear;
|
||||
|
||||
signal sram : sram_t := sram_clear;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
SRAM_RW:
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(0) = '1' then
|
||||
sram(index)(7 downto 0) <= din(7 downto 0);
|
||||
end if;
|
||||
if we(1) = '1' then
|
||||
sram(index)(15 downto 8) <= din(15 downto 8);
|
||||
end if;
|
||||
if we(2) = '1' then
|
||||
sram(index)(23 downto 16) <= din(23 downto 16);
|
||||
end if;
|
||||
if we(3) = '1' then
|
||||
sram(index)(31 downto 24) <= din(31 downto 24);
|
||||
end if;
|
||||
dout <= sram(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -0,0 +1,74 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : real := 20.0; -- precharge command period [ns]
|
||||
constant TRAS : real := 45.0; -- active to precharge delay [ns]
|
||||
constant TRFC : real := 75.0; -- auto refresh command period [ns]
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
|
||||
constant TRCD : real := 20.0; -- active to read or write delay [ns]
|
||||
constant TWR : real := 15.0; -- write recovery time [ns]
|
||||
|
||||
constant PWR_UP_WAIT : real := 220.0E3; -- [ns]
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -0,0 +1,74 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : real := 20.0; -- precharge command period [ns]
|
||||
constant TRAS : real := 45.0; -- active to precharge delay [ns]
|
||||
constant TRFC : real := 75.0; -- auto refresh command period [ns]
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
|
||||
constant TRCD : real := 20.0; -- active to read or write delay [ns]
|
||||
constant TWR : real := 15.0; -- write recovery time [ns]
|
||||
|
||||
constant PWR_UP_WAIT : real := 22.0E3; -- [ns]
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -0,0 +1,70 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: MIPS System controller
|
||||
-- This file:
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.async_types.all;
|
||||
|
||||
package async_defs is
|
||||
|
||||
constant ts_flash : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 00.0,
|
||||
T_pulse_rd => 120.0,
|
||||
T_pulse_wr => 70.0,
|
||||
T_leadout => 00.0,
|
||||
T_release => 40.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 30.0,
|
||||
can_page_rd => true,
|
||||
nbits_page_rd => 4,
|
||||
pol_cs => '1',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
constant ts_usb : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 10.0,
|
||||
T_pulse_rd => 60.0,
|
||||
T_pulse_wr => 60.0,
|
||||
T_leadout => 10.0,
|
||||
T_release => 80.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 00.0,
|
||||
can_page_rd => false,
|
||||
nbits_page_rd => 0,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end async_defs;
|
||||
@@ -0,0 +1,420 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.vga_types.all;
|
||||
|
||||
ENTITY tb_mips_sys IS
|
||||
END tb_mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_sys IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant AC97_CLK_PERIOD : time := 83 ns;
|
||||
constant ETH_CLK_PERIOD : time := 7.7 ns;
|
||||
constant LOOP_BACK_EN : std_logic := '1';
|
||||
signal sys_rst_n_in : std_logic := '0';
|
||||
signal sys_clk_in : std_logic := '1';
|
||||
signal dip : unsigned(7 downto 0) := (others => '0');
|
||||
signal btn : unsigned(4 downto 0) := (others => '0');
|
||||
signal led : unsigned(8 downto 0);
|
||||
signal sys_rx : std_logic := '1';
|
||||
signal sys_tx : std_logic;
|
||||
signal sys_rx1 : std_logic := '1';
|
||||
signal sys_tx1 : std_logic;
|
||||
signal sys_rx2 : std_logic := '1';
|
||||
signal sys_tx2 : std_logic;
|
||||
|
||||
signal sys_lcd_d : unsigned(3 downto 0);
|
||||
signal sys_lcd_e : std_logic;
|
||||
signal sys_lcd_rs : std_logic;
|
||||
signal sys_lcd_rw : std_logic;
|
||||
|
||||
signal refresh : boolean:= true;
|
||||
|
||||
signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock
|
||||
signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock
|
||||
signal sys_sdr_cke_q : std_logic; -- clock enable
|
||||
signal sys_sdr_cs_qn : std_logic; -- /chip select
|
||||
signal sys_sdr_ras_qn : std_logic; -- /ras
|
||||
signal sys_sdr_cas_qn : std_logic; -- /cas
|
||||
signal sys_sdr_we_qn : std_logic; -- /write enable
|
||||
signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
|
||||
signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
|
||||
signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
|
||||
signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
|
||||
signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
|
||||
|
||||
signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors
|
||||
signal sys_sdr_clk_fb : std_logic;
|
||||
|
||||
signal sys_usb_d : unsigned(15 downto 0) := (others => '0');
|
||||
signal sys_usb_a : unsigned(1 downto 0);
|
||||
signal sys_usb_csn : std_logic;
|
||||
signal sys_usb_wrn : std_logic;
|
||||
signal sys_usb_rdn : std_logic;
|
||||
signal sys_usb_rstn : std_logic;
|
||||
signal sys_usb_int : std_logic := '0';
|
||||
|
||||
signal sys_flash_ssram_d : word_t;
|
||||
signal sys_flash_ssram_a : unsigned(24 downto 0);
|
||||
signal sys_flash_ssram_we_n : std_logic;
|
||||
signal sys_flash_ssram_oe_n : std_logic;
|
||||
|
||||
signal sys_flash_ce : std_logic;
|
||||
signal sys_flash_ac97_rstn : std_logic;
|
||||
signal sys_flash_byten : std_logic;
|
||||
|
||||
signal sys_ssram_clk_fb : std_logic;
|
||||
signal sys_ssram_clk : std_logic;
|
||||
signal sys_ssram_cke_n : std_logic;
|
||||
signal sys_ssram_ce_n : std_logic;
|
||||
signal sys_ssram_bw_n : unsigned(3 downto 0);
|
||||
signal sys_ssram_dp : unsigned(3 downto 0);
|
||||
signal sys_ssram_adv : std_logic;
|
||||
signal sys_ssram_mode : std_logic;
|
||||
signal sys_ssram_zz : std_logic;
|
||||
|
||||
SIGNAL sys_ac97_bit_clk : std_logic := '0';
|
||||
SIGNAL sys_ac97_sdata_out : std_logic;
|
||||
SIGNAL sys_ac97_ssync : std_logic;
|
||||
SIGNAL sys_ac97_sdata_in : std_logic;
|
||||
|
||||
SIGNAL sys_ps2_clk : std_logic := 'H';
|
||||
SIGNAL sys_ps2_data : std_logic := 'H';
|
||||
|
||||
SIGNAL sys_phy_rstn : std_logic;
|
||||
SIGNAL sys_phy_mdc : std_logic;
|
||||
SIGNAL sys_phy_mdio : std_logic := 'H';
|
||||
SIGNAL sys_phy_int : std_logic := '0';
|
||||
|
||||
SIGNAL sys_phy_rx_clk : STD_LOGIC := '0';
|
||||
SIGNAL sys_phy_rx_dv : STD_LOGIC := '0';
|
||||
SIGNAL sys_phy_rx_er : STD_LOGIC := '0';
|
||||
SIGNAL sys_phy_rx : unsigned(7 downto 0) := (others => '0');
|
||||
SIGNAL sys_phy_tx_clk : STD_LOGIC := '0';
|
||||
SIGNAL sys_phy_tx_en : STD_LOGIC;
|
||||
SIGNAL sys_phy_tx_er : STD_LOGIC;
|
||||
SIGNAL sys_phy_tx : unsigned(7 downto 0);
|
||||
SIGNAL sys_phy_gtx_clk : STD_LOGIC;
|
||||
SIGNAL sys_phy_crs : STD_LOGIC := '0';
|
||||
SIGNAL sys_phy_col : STD_LOGIC := '0';
|
||||
|
||||
signal flash_reg : word_t;
|
||||
signal eth_tx_reg : unsigned(7 downto 0);
|
||||
|
||||
type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
|
||||
signal flash_data : flash_data_t;
|
||||
|
||||
signal ac_frame_reg : unsigned(255 downto 0) := (others => '0');
|
||||
signal ac_left : unsigned(17 downto 0) := X"0000" & "00";
|
||||
signal ac_right : unsigned(17 downto 0) := X"0000" & "01";
|
||||
signal ac_synced : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: entity work.mips_sys
|
||||
GENERIC MAP
|
||||
(
|
||||
sys_freq_in => 100.000,
|
||||
cpu_freq => 100.000,
|
||||
sdram_phaseshift => 0,
|
||||
tsvga => ts_vga_800_600_72
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst_n_in => sys_rst_n_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
sys_btn => btn,
|
||||
sys_dip => dip,
|
||||
sys_led => led,
|
||||
|
||||
sys_uart0_rx => sys_rx,
|
||||
sys_uart0_tx => sys_tx,
|
||||
sys_uart1_rx => sys_rx1,
|
||||
sys_uart1_tx => sys_tx1,
|
||||
sys_uart2_rx => sys_rx2,
|
||||
sys_uart2_tx => sys_tx2,
|
||||
|
||||
sys_lcd_d => sys_lcd_d,
|
||||
sys_lcd_e => sys_lcd_e,
|
||||
sys_lcd_rs => sys_lcd_rs,
|
||||
sys_lcd_rw => sys_lcd_rw,
|
||||
|
||||
sys_sdr_clk_p => sys_sdr_clk_p,
|
||||
sys_sdr_clk_n => sys_sdr_clk_n,
|
||||
sys_sdr_cke_q => sys_sdr_cke_q,
|
||||
sys_sdr_clk_fb => sys_sdr_clk_fb,
|
||||
sys_sdr_cs_qn => sys_sdr_cs_qn,
|
||||
sys_sdr_ras_qn => sys_sdr_ras_qn,
|
||||
sys_sdr_cas_qn => sys_sdr_cas_qn,
|
||||
sys_sdr_we_qn => sys_sdr_we_qn,
|
||||
sys_sdr_dm_q => sys_sdr_dm_q,
|
||||
sys_sdr_dqs_q => sys_sdr_dqs_q,
|
||||
sys_sdr_ba_q => sys_sdr_ba_q,
|
||||
sys_sdr_a_q => sys_sdr_a_q,
|
||||
sys_sdr_data => sys_sdr_data,
|
||||
|
||||
sys_usb_d => sys_usb_d,
|
||||
sys_usb_a => sys_usb_a,
|
||||
sys_usb_csn => sys_usb_csn,
|
||||
sys_usb_wrn => sys_usb_wrn,
|
||||
sys_usb_rdn => sys_usb_rdn,
|
||||
sys_usb_rstn => sys_usb_rstn,
|
||||
sys_usb_int => sys_usb_int,
|
||||
|
||||
sys_flash_ssram_d => sys_flash_ssram_d,
|
||||
sys_flash_ssram_a => sys_flash_ssram_a,
|
||||
sys_flash_ssram_we_n => sys_flash_ssram_we_n,
|
||||
sys_flash_ssram_oe_n => sys_flash_ssram_oe_n,
|
||||
sys_flash_ce => sys_flash_ce,
|
||||
sys_flash_ac97_rstn => sys_flash_ac97_rstn,
|
||||
sys_flash_byten => sys_flash_byten,
|
||||
|
||||
sys_ssram_clk_fb => sys_ssram_clk_fb,
|
||||
sys_ssram_clk => sys_ssram_clk,
|
||||
sys_ssram_cke_n => sys_ssram_cke_n,
|
||||
sys_ssram_ce_n => sys_ssram_ce_n,
|
||||
sys_ssram_bw_n => sys_ssram_bw_n,
|
||||
sys_ssram_dp => sys_ssram_dp,
|
||||
sys_ssram_adv => sys_ssram_adv,
|
||||
sys_ssram_mode => sys_ssram_mode,
|
||||
sys_ssram_zz => sys_ssram_zz,
|
||||
|
||||
sys_ac97_bit_clk => sys_ac97_bit_clk,
|
||||
sys_ac97_sdata_out => sys_ac97_sdata_out,
|
||||
sys_ac97_ssync => sys_ac97_ssync,
|
||||
sys_ac97_sdata_in => sys_ac97_sdata_in,
|
||||
|
||||
sys_ps2_clk => sys_ps2_clk,
|
||||
sys_ps2_data => sys_ps2_data,
|
||||
|
||||
sys_phy_rstn => sys_phy_rstn,
|
||||
sys_phy_mdc => sys_phy_mdc,
|
||||
sys_phy_mdio => sys_phy_mdio,
|
||||
sys_phy_int => sys_phy_int,
|
||||
|
||||
sys_phy_rx_clk => sys_phy_rx_clk,
|
||||
sys_phy_rx_dv => sys_phy_rx_dv,
|
||||
sys_phy_rx_er => sys_phy_rx_er,
|
||||
sys_phy_rx => sys_phy_rx,
|
||||
sys_phy_tx_clk => sys_phy_tx_clk,
|
||||
sys_phy_tx_en => sys_phy_tx_en,
|
||||
sys_phy_tx_er => sys_phy_tx_er,
|
||||
sys_phy_tx => sys_phy_tx,
|
||||
sys_phy_gtx_clk => sys_phy_gtx_clk,
|
||||
sys_phy_crs => sys_phy_crs,
|
||||
sys_phy_col => sys_phy_col,
|
||||
|
||||
sys_error => sys_error
|
||||
);
|
||||
|
||||
sys_phy_rx <= sys_phy_tx when LOOP_BACK_EN = '1' else X"00";
|
||||
sys_phy_rx_dv <= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0';
|
||||
sys_phy_rx_er <= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0';
|
||||
sys_phy_crs <= '0';
|
||||
sys_phy_col <= '0';
|
||||
|
||||
inst_ssram : entity work.cy7c1354
|
||||
PORT MAP
|
||||
(
|
||||
Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O
|
||||
Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O
|
||||
Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address
|
||||
Mode => sys_ssram_mode, -- Burst Mode
|
||||
Clk => sys_ssram_clk, -- Clk
|
||||
CEN_n => sys_ssram_cke_n, -- CEN#
|
||||
AdvLd_n => sys_ssram_adv, -- Adv/Ld#
|
||||
Bwa_n => sys_ssram_bw_n(0), -- Bwa#
|
||||
Bwb_n => sys_ssram_bw_n(1), -- BWb#
|
||||
Bwc_n => sys_ssram_bw_n(2), -- Bwc#
|
||||
Bwd_n => sys_ssram_bw_n(3), -- BWd#
|
||||
Rw_n => sys_flash_ssram_we_n, -- RW#
|
||||
Oe_n => sys_flash_ssram_oe_n, -- OE#
|
||||
Ce1_n => sys_ssram_ce_n, -- CE1#
|
||||
Ce2 => '1', -- CE2
|
||||
Ce3_n => '0', -- CE3#
|
||||
Zz => sys_ssram_zz
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_1 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
|
||||
);
|
||||
|
||||
sys_sdr_clk_fb <= sys_sdr_clk_p after 1300 ps;
|
||||
sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns;
|
||||
|
||||
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
|
||||
|
||||
sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_in <= not sys_clk_in;
|
||||
end process;
|
||||
|
||||
ETH_CLK_GEN: process
|
||||
begin
|
||||
wait for ETH_CLK_PERIOD/2;
|
||||
sys_phy_rx_clk <= not sys_phy_rx_clk;
|
||||
sys_phy_tx_clk <= not sys_phy_tx_clk;
|
||||
end process;
|
||||
|
||||
ETH_TX_REGISTER:
|
||||
PROCESS(sys_phy_tx_clk)
|
||||
begin
|
||||
if rising_edge(sys_phy_tx_clk) then
|
||||
if (sys_phy_tx_en = '1') then
|
||||
eth_tx_reg <= sys_phy_tx;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
|
||||
|
||||
ac97_data_gen :
|
||||
PROCESS(sys_ac97_bit_clk)
|
||||
begin
|
||||
if rising_edge(sys_ac97_bit_clk) then
|
||||
ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
|
||||
if sys_flash_ac97_rstn = '0' then
|
||||
ac_synced <= '0';
|
||||
elsif sys_ac97_ssync = '1' then
|
||||
if ac_synced = '0' then
|
||||
ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
|
||||
ac_left <= ac_left + 2;
|
||||
ac_right <= ac_right + 2;
|
||||
ac_synced <= '1';
|
||||
end if;
|
||||
else
|
||||
ac_synced <= '0';
|
||||
end if;
|
||||
end if;
|
||||
END PROCESS;
|
||||
|
||||
ac97_clk_gen : PROCESS
|
||||
begin
|
||||
if (sys_flash_ac97_rstn = '0') then
|
||||
sys_ac97_bit_clk <= '0';
|
||||
wait until sys_flash_ac97_rstn = '1';
|
||||
wait for 150 us;
|
||||
end if;
|
||||
wait for AC97_CLK_PERIOD/2;
|
||||
sys_ac97_bit_clk <= not sys_ac97_bit_clk;
|
||||
END PROCESS;
|
||||
|
||||
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
|
||||
type file_t is file of integer;
|
||||
file load_flash : file_t open read_mode is "blittertest_tb.elf.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
begin
|
||||
if sys_rst_n_in = '0' then
|
||||
index := 0;
|
||||
while not endfile(load_flash) loop
|
||||
read(load_flash, instr);
|
||||
temp := to_signed(instr, word_t'length);
|
||||
flash_data(index) <= unsigned(temp);
|
||||
index := index + 1;
|
||||
end loop;
|
||||
else
|
||||
sys_flash_ssram_d <= (others => 'Z') after 10 ns;
|
||||
if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
|
||||
index := to_integer(sys_flash_ssram_a(24 downto 1));
|
||||
sys_flash_ssram_d <= flash_data(index) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
|
||||
begin
|
||||
if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
|
||||
flash_reg <= sys_flash_ssram_d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
dip(7) <= '1'; -- EB
|
||||
btn(0) <= '1';
|
||||
btn(2) <= '1';
|
||||
wait for 3*CLK_PERIOD;
|
||||
sys_rst_n_in <= '1';
|
||||
btn(0) <= '0';
|
||||
btn(2) <= '0';
|
||||
wait for 20000000*CLK_PERIOD;
|
||||
|
||||
loop
|
||||
wait for 251*CLK_PERIOD;
|
||||
btn(4) <= '1';
|
||||
wait for 311*CLK_PERIOD;
|
||||
btn(4) <= '0';
|
||||
end loop;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,46 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
# This file: Insertion of code fragments into templates
|
||||
#
|
||||
# Copyright (C) 2008 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
arg = $*
|
||||
rom_filename = arg[0].to_s
|
||||
tpl_filename = arg[1].to_s
|
||||
|
||||
subst_pattern = "ROM_INSERT_HERE"
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Open file
|
||||
# --------------------------------------------------------
|
||||
romfile = File.open(rom_filename, "r")
|
||||
tplfile = File.open(tpl_filename, "r")
|
||||
re = Regexp.new(subst_pattern)
|
||||
|
||||
while (line = tplfile.gets)
|
||||
puts line
|
||||
line.scan(re).each do |word|
|
||||
romfile.each do |raw_line|
|
||||
puts raw_line
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -0,0 +1,29 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
-- ROM_INSERT_HERE
|
||||
|
||||
@@ -0,0 +1,147 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE loadable OF irom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : unsigned (15 downto 0);
|
||||
signal jtag_ld_dout : unsigned (31 downto 0);
|
||||
signal jtag_ld_din : unsigned (31 downto 0);
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
|
||||
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,50 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -0,0 +1,61 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,117 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define INT8 char
|
||||
#define INT16 short
|
||||
#define INT32 long
|
||||
#define UINT8 unsigned char
|
||||
#define UINT16 unsigned short
|
||||
#define UINT32 unsigned long
|
||||
#define INT int
|
||||
#define UINT unsigned int
|
||||
#define FLOAT32 float
|
||||
#define FLOAT64 double
|
||||
|
||||
#define SDRAM_BASE 0x40000000
|
||||
#define FLASH_OFFSET 0x00000000
|
||||
|
||||
// --------------------------------------------------------------
|
||||
typedef struct _sflash_img_hdr_t
|
||||
{
|
||||
UINT8 magic[4];
|
||||
UINT32 target_addr;
|
||||
UINT32 img_offset;
|
||||
UINT32 img_size;
|
||||
UINT32 hdr_next;
|
||||
UINT8 img_name[128];
|
||||
UINT8 res[108];
|
||||
|
||||
} flash_img_hdr_t;
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
// --------------------------------------------------------------
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_flash[1024];
|
||||
char name_prj[1024];
|
||||
char *pBuf;
|
||||
flash_img_hdr_t img_hdr = {0};
|
||||
|
||||
FILE *pFile;
|
||||
int filesize;
|
||||
long start, end;
|
||||
int i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: flashgen <input file>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
pFile = fopen(pFilenameIn, "rb");
|
||||
if (!pFile)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_flash, "%s.flash.bin", name_prj);
|
||||
|
||||
// determine filesize
|
||||
fseek(pFile, 0, SEEK_SET);
|
||||
start = ftell(pFile);
|
||||
fseek(pFile, 0, SEEK_END);
|
||||
end = ftell(pFile);
|
||||
fseek(pFile, 0, SEEK_SET);
|
||||
filesize = (end-start);
|
||||
|
||||
pBuf = (char*)malloc(filesize);
|
||||
fread(pBuf, 1, filesize, pFile);
|
||||
|
||||
fclose(pFile);
|
||||
|
||||
pFile = fopen(name_flash, "wb");
|
||||
if (!pFile)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", name_flash);
|
||||
return 1;
|
||||
}
|
||||
|
||||
img_hdr.magic[0] = 'J';
|
||||
img_hdr.magic[1] = 'F';
|
||||
img_hdr.magic[2] = 'I';
|
||||
img_hdr.magic[3] = '1';
|
||||
img_hdr.target_addr = SDRAM_BASE;
|
||||
img_hdr.img_size = filesize;
|
||||
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
|
||||
img_hdr.hdr_next = FLASH_OFFSET;
|
||||
|
||||
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
|
||||
fwrite(pBuf, 1, filesize, pFile);
|
||||
|
||||
fclose(pFile);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,385 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define ARCH_NAME "data"
|
||||
#define ENT_NAME "ram"
|
||||
#define JTAG_ADDR_WIDTH 16
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "library UNISIM;\n");
|
||||
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "\n");
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
|
||||
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\telse\n");
|
||||
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, word_addr, filesize, romsize;
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
|
||||
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
|
||||
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
|
||||
fprintf(pFileOut, "# User 2\n");
|
||||
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
|
||||
|
||||
word_addr = 0;
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
word_addr++;
|
||||
}
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
|
||||
fprintf(pFileOut, "exit\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_prj[1024];
|
||||
char name_rom_tcl[1024];
|
||||
char name_rom[1024];
|
||||
char name_rom_v4ld[1024];
|
||||
|
||||
FILE *pFileIn;
|
||||
int filesize, romsize, nbits_addr, nbits_data;
|
||||
long start, end;
|
||||
int word, i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
if (argc == 3)
|
||||
nbits_addr = atoi(argv[2]);
|
||||
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_rom, "%s.vhd", name_prj);
|
||||
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
|
||||
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
||||
|
||||
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,368 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define ARCH_NAME "data"
|
||||
#define ENT_NAME "rom"
|
||||
#define JTAG_ADDR_WIDTH 16
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "library UNISIM;\n");
|
||||
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "\n");
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
|
||||
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\telse\n");
|
||||
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, word_addr, filesize, romsize;
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
|
||||
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
|
||||
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
|
||||
fprintf(pFileOut, "# User 1\n");
|
||||
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
|
||||
|
||||
word_addr = 0;
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
word_addr++;
|
||||
}
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
|
||||
fprintf(pFileOut, "exit\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_prj[1024];
|
||||
char name_rom[1024];
|
||||
char name_rom_v4ld[1024];
|
||||
char name_rom_tcl[1024];
|
||||
|
||||
FILE *pFileIn;
|
||||
int filesize, romsize, nbits_addr, nbits_data;
|
||||
long start, end;
|
||||
int word, i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
if (argc == 3)
|
||||
nbits_addr = atoi(argv[2]);
|
||||
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_rom, "%s.vhd", name_prj);
|
||||
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
|
||||
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
||||
|
||||
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user