Compare commits
1
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
ee1c6d5b39 |
@@ -3,19 +3,14 @@
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##
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_2w2r2c_ra_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_2w2r2c_ro_sim.vhd"
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vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
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vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../../JBUS/src/busmaster_types.vhd"
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vcom -explicit -93 "../../JBUS/src/busmaster_sync.vhd"
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vcom -explicit -93 "../../JBUS/src/dmac.vhd"
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vcom -explicit -93 "../src/piso.vhd"
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vcom -explicit -93 "../src/sipo.vhd"
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vcom -explicit -93 "../src/crc32.vhd"
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@@ -31,4 +26,4 @@ do {tb_emac_top_jb.wdo}
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view structure
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view signals
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run 16000 us
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run 50000 us
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@@ -3,8 +3,6 @@ quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {Ethernet MAC}
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/ram64
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add wave -noupdate -divider Slave
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add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
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@@ -16,18 +14,6 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
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add wave -noupdate -divider Master
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add wave -noupdate -format Logic /tb_emac_top_jb/cyc_o
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add wave -noupdate -format Logic /tb_emac_top_jb/stb_o
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add wave -noupdate -format Logic /tb_emac_top_jb/we_o
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add wave -noupdate -format Literal /tb_emac_top_jb/sel_o
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add wave -noupdate -format Logic /tb_emac_top_jb/ack_i
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add wave -noupdate -format Logic /tb_emac_top_jb/mrdy_o
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add wave -noupdate -format Logic /tb_emac_top_jb/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/addr_o
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add wave -noupdate -format Literal /tb_emac_top_jb/mdat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/mdat_o
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add wave -noupdate -divider MII
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
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@@ -67,25 +53,10 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
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add wave -noupdate -divider RX-DMA
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_req
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_gnt
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_start
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_active
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_end
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rdy
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rw
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_start
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_num_xfers
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_auto_inc
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete_ack
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/s
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add wave -noupdate -divider RX
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_re
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
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add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
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@@ -188,6 +159,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
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@@ -195,11 +168,6 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/p
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re_dly
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
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@@ -219,7 +187,7 @@ add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {15999470765 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461803096 ps} 0} {{Cursor 5} {10000 ps} 0}
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WaveRestoreCursors {{Cursor 1} {11284359462 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {49999529250 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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@@ -233,4 +201,4 @@ configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {379173 ps}
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WaveRestoreZoom {11283753554 ps} {11286295500 ps}
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@@ -50,12 +50,11 @@ begin
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process(clk)
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begin
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if rising_edge(clk) then
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crc32_vld <= not rst and din_vld;
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if rst = '1' then
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crc0 <= crc32_init;
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crc32_vld <= '0';
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elsif din_vld = '1' then
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crc0 <= crc2;
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crc32_vld <= '1';
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end if;
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end if;
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end process;
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@@ -16,7 +16,7 @@ ENTITY emac_rx IS
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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dout_re : in STD_LOGIC;
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dout_vld : out STD_LOGIC;
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dout : out unsigned(31 downto 0);
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ctrl_in : in rx_ctrl_in_t;
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ctrl_out : out rx_ctrl_out_t;
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@@ -47,7 +47,6 @@ ARCHITECTURE behavior OF emac_rx IS
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signal reset_en : std_logic;
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signal host_ptr : word_ptr_t;
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signal host_ptr_next : word_ptr_t;
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signal host_ram_limit : word_ptr_t;
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signal host_ram_base : word_ptr_t;
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@@ -144,7 +143,7 @@ begin
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dout <= ram_dout_b;
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ram_en_b <= '1';
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ram_addr_b <= host_ptr_next;
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ram_addr_b <= host_ptr;
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ram_en_a <= '1';
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ram_din_a <= sipo32_dout;
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@@ -184,16 +183,15 @@ fill_pointer:
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process(clk)
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begin
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if rising_edge(clk) then
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dout_vld <= ctrl_in.pkt_read_en;
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if ctrl_in.pkt_req_en = '1' then
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host_ptr <= cmd_base_out;
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elsif dout_re = '1' then
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host_ptr <= host_ptr_next;
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elsif ctrl_in.pkt_read_en = '1' then
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host_ptr <= host_ptr + 1;
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end if;
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end if;
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end process;
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host_ptr_next <= host_ptr + 1 when dout_re = '1' else host_ptr;
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------------------------------------------------------------------
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-- Transfer stuff
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------------------------------------------------------------------
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@@ -446,7 +444,7 @@ inst_cmd_fifo: entity work.fifo_async
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data_r => cmd_fifo_dout
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);
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inst_ram : entity work.dpram_1w1r2c_ro
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inst_ram : entity work.dpram_1w1r
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GENERIC MAP
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(
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addr_width => RAM_ADDR_WIDTH,
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@@ -454,8 +452,8 @@ inst_ram : entity work.dpram_1w1r2c_ro
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)
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PORT MAP
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(
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clk_a => mii_rx_clk,
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clk_b => clk,
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clka => mii_rx_clk,
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clkb => clk,
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en_a => ram_en_a,
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en_b => ram_en_b,
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we_a => ram_we_a,
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+33
-260
@@ -5,7 +5,6 @@ use std.textio.all; -- Imports the standard textio package.
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use work.emac_types.all;
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use work.utils_pkg.all;
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use work.busmaster_types.all;
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ENTITY emac_top_jb IS
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Generic
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@@ -16,7 +15,6 @@ ENTITY emac_top_jb IS
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);
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Port
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(
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-- JBUS Slave
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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INT_O : out STD_LOGIC;
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@@ -30,20 +28,6 @@ ENTITY emac_top_jb IS
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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-- JBUS Master
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ACK_I : in std_logic;
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SRDY_I : in std_logic;
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MDAT_I : in unsigned(31 downto 0);
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MDAT_O : out unsigned(31 downto 0);
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ADDR_O : out unsigned(31 downto 0);
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SEL_O : out unsigned(3 downto 0);
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WE_O : out std_logic;
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CYC_O : out std_logic;
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STB_O : out std_logic;
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MRDY_O : out std_logic;
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-- MII
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mii_rx_clk : in STD_LOGIC;
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mii_rx_dv : in STD_LOGIC;
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mii_rx_er : in STD_LOGIC;
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@@ -61,12 +45,6 @@ END emac_top_jb;
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ARCHITECTURE behavior OF emac_top_jb IS
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-- Constants
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constant DMA_NUM_CHANNEL : integer := 2;
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constant DMA_CH_WRITE : integer := 0;
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constant DMA_CH_READ : integer := 1;
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constant DMA_RW_CONF : unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
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-- Signals for EMAC connections
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signal tx_ctrl_in : tx_ctrl_in_t;
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signal tx_ctrl_out : tx_ctrl_out_t;
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@@ -77,7 +55,7 @@ ARCHITECTURE behavior OF emac_top_jb IS
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signal rx_ctrl_out : rx_ctrl_out_t;
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signal rx_dout : unsigned(31 downto 0);
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signal rx_dout_re : std_logic;
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signal rx_dout_vld : std_logic;
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signal rx_int_en : std_logic;
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signal tx_int_en : std_logic;
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@@ -86,98 +64,24 @@ ARCHITECTURE behavior OF emac_top_jb IS
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signal ready : std_logic;
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signal read : std_logic;
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signal write : std_logic;
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signal rx_read_en_CPU : std_logic;
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signal rx_req_en_CPU : std_logic;
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signal rx_free_en_CPU : std_logic;
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signal tx_write_en_CPU : std_logic;
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signal reg_read : std_logic;
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signal reg_write : std_logic;
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signal reg_addr : unsigned(3 downto 0);
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-- DMA Controller
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signal dma_master_req : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_master_gnt : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
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signal dma_req_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_req_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
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signal dma_req_addr_auto_inc : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
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signal dma_req_addr : array32_t;
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signal dma_req_num_xfers : array32_t;
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signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
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signal dma_start : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_active : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_end : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
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signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
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signal dma_bus_cmd_we : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
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type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t;
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signal dma_bus_cmd : array_bus_cmd_t;
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||||
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||||
-- Busmaster arbiter
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||||
signal arb_idx : natural range 0 to DMA_NUM_CHANNEL-1;
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||||
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||||
-- BUS Master controller
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||||
signal bus_din_re : std_logic;
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||||
signal bus_cmd_cycle_finished : std_logic;
|
||||
signal bus_cmd_cycle_en : std_logic := '0';
|
||||
signal bus_cmd_rdy : std_logic;
|
||||
signal bus_cmd_we : std_logic := '0';
|
||||
signal bus_cmd : bm_cmd_t;
|
||||
signal bus_din_rdy : std_logic;
|
||||
signal bus_din_vld : std_logic := '0';
|
||||
signal bus_din : unsigned(31 downto 0) := (others => '-');
|
||||
signal bus_dout : unsigned(31 downto 0);
|
||||
signal bus_dout_vld : std_logic;
|
||||
signal bus_dout_re : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
mii_gtx_clk <= '0';
|
||||
SRDY_O <= CYC_I and ready;
|
||||
mii_gtx_clk <= '0';
|
||||
|
||||
SRDY_O <= CYC_I and ready;
|
||||
read <= STB_I and CYC_I and not WE_I;
|
||||
write <= STB_I and CYC_I and WE_I;
|
||||
rx_read_en_CPU <= read and ADDR_I(15);
|
||||
tx_write_en_CPU <= write and ADDR_I(15);
|
||||
reg_read <= read and not ADDR_I(15);
|
||||
reg_write <= write and not ADDR_I(15);
|
||||
reg_addr <= ADDR_I(5 downto 2);
|
||||
|
||||
ready <= not tx_ctrl_in.pkt_alloc_en;
|
||||
|
||||
tx_din_vld <= tx_write_en_CPU;
|
||||
tx_din <= DAT_I;
|
||||
|
||||
rx_ctrl_in.pkt_free_en <= rx_free_en_CPU or dma_end(0);
|
||||
rx_ctrl_in.pkt_req_en <= rx_req_en_CPU or dma_start(0);
|
||||
|
||||
rx_dout_re <= rx_read_en_CPU or (dma_active(DMA_CH_WRITE) and bus_din_rdy);
|
||||
|
||||
bus_din <= rx_dout;
|
||||
bus_din_vld <= dma_active(DMA_CH_WRITE);
|
||||
dma_master_gnt(0) <= SRDY_I;
|
||||
dma_req_en(0) <= rx_ctrl_out.pkt_avail;
|
||||
dma_req_num_xfers(0) <= X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) when rx_ctrl_out.rx_size(1 downto 0) = "00" else X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) + 1;
|
||||
dma_req_addr(0) <= X"00000800";
|
||||
dma_req_addr_auto_inc <= "11";
|
||||
ready <= not tx_ctrl_in.pkt_alloc_en;
|
||||
|
||||
------------------------------------------------------------------
|
||||
registers_write:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
tx_din_vld <= '0';
|
||||
tx_ctrl_in.pkt_alloc_en <= '0';
|
||||
tx_ctrl_in.pkt_commit_en <= '0';
|
||||
tx_ctrl_in.reset <= '0';
|
||||
rx_free_en_CPU <= '0';
|
||||
rx_req_en_CPU <= '0';
|
||||
rx_ctrl_in.pkt_free_en <= '0';
|
||||
rx_ctrl_in.pkt_req_en <= '0';
|
||||
rx_ctrl_in.reset <= '0';
|
||||
if RST_I = '1' then
|
||||
rx_int_en <= '0';
|
||||
@@ -189,24 +93,22 @@ registers_write:
|
||||
rx_ctrl_in.Gbps_en <= '0';
|
||||
tx_ctrl_in.fcs_gen_en <= '0';
|
||||
rx_ctrl_in.fcs_chk_en <= '0';
|
||||
elsif reg_write = '1' then
|
||||
|
||||
-- 0x0000 .. 0x003C
|
||||
case reg_addr is
|
||||
|
||||
elsif (STB_I and CYC_I and WE_I) = '1' then
|
||||
case ADDR_I(5 downto 2) is
|
||||
|
||||
-- 0x0000
|
||||
when "0000" =>
|
||||
rx_ctrl_in.reset <= DAT_I(31);
|
||||
rx_ctrl_in.Gbps_en <= DAT_I(30);
|
||||
rx_ctrl_in.fcs_chk_en <= DAT_I(29);
|
||||
rx_ctrl_in.promiscious <= DAT_I(23);
|
||||
rx_req_en_CPU <= DAT_I(17);
|
||||
rx_free_en_CPU <= DAT_I(16);
|
||||
rx_ctrl_in.pkt_req_en <= DAT_I(17);
|
||||
rx_ctrl_in.pkt_free_en <= DAT_I(16);
|
||||
rx_int_en <= DAT_I(4);
|
||||
|
||||
|
||||
-- 0x0004
|
||||
-- rx_size R/O
|
||||
|
||||
|
||||
-- 0x0008
|
||||
when "0010" =>
|
||||
tx_ctrl_in.reset <= DAT_I(31);
|
||||
@@ -215,14 +117,16 @@ registers_write:
|
||||
tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
|
||||
tx_ctrl_in.pkt_commit_en <= DAT_I(16);
|
||||
tx_int_en <= DAT_I(4);
|
||||
|
||||
|
||||
-- 0x000C
|
||||
when "0011" =>
|
||||
tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
|
||||
|
||||
|
||||
-- 0x0010
|
||||
-- Gap
|
||||
|
||||
when "0100" =>
|
||||
tx_din_vld <= '1';
|
||||
tx_din <= DAT_I;
|
||||
|
||||
-- 0x0014
|
||||
-- Gap
|
||||
|
||||
@@ -232,18 +136,14 @@ registers_write:
|
||||
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
|
||||
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
|
||||
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
|
||||
|
||||
|
||||
-- 0x001C
|
||||
when "0111" =>
|
||||
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
|
||||
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
|
||||
|
||||
-- 0x0020 .. 0x003C
|
||||
-- Gap
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
@@ -252,12 +152,11 @@ registers_read:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
ACK_O <= rx_read_en_CPU;
|
||||
rx_ctrl_in.pkt_read_en <= '0';
|
||||
ACK_O <= rx_dout_vld and CYC_I and not WE_I;
|
||||
DAT_O <= rx_dout;
|
||||
if reg_read = '1' then
|
||||
|
||||
-- 0x0000 .. 0x003C
|
||||
case reg_addr is
|
||||
if (STB_I and CYC_I) = '1' and WE_I = '0' then
|
||||
case ADDR_I(5 downto 2) is
|
||||
|
||||
-- 0x0000
|
||||
when "0000" =>
|
||||
@@ -272,7 +171,7 @@ registers_read:
|
||||
DAT_O(17) <= rx_ctrl_out.pkt_valid;
|
||||
DAT_O(16) <= rx_ctrl_out.pkt_avail;
|
||||
DAT_O(4) <= rx_int_en;
|
||||
|
||||
|
||||
-- 0x0004
|
||||
when "0001" =>
|
||||
ACK_O <= '1';
|
||||
@@ -289,15 +188,16 @@ registers_read:
|
||||
DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
|
||||
DAT_O(16) <= tx_ctrl_out.pkt_armed;
|
||||
DAT_O(4) <= tx_int_en;
|
||||
|
||||
|
||||
-- 0x000C
|
||||
when "0011" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= X"0000" & tx_ctrl_out.tx_size;
|
||||
|
||||
-- 0x0010
|
||||
-- Gap
|
||||
|
||||
when "0100" =>
|
||||
rx_ctrl_in.pkt_read_en <= '1';
|
||||
|
||||
-- 0x0014
|
||||
-- Gap
|
||||
|
||||
@@ -305,18 +205,14 @@ registers_read:
|
||||
when "0110" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
|
||||
|
||||
|
||||
-- 0x001C
|
||||
when "0111" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
|
||||
|
||||
-- 0x0020 .. 0x003C
|
||||
-- Gap
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
@@ -341,7 +237,7 @@ inst_emac_rx : entity work.emac_rx
|
||||
(
|
||||
clk => CLK_I,
|
||||
rst => RST_I,
|
||||
dout_re => rx_dout_re,
|
||||
dout_vld => rx_dout_vld,
|
||||
dout => rx_dout,
|
||||
ctrl_in => rx_ctrl_in,
|
||||
ctrl_out => rx_ctrl_out,
|
||||
@@ -376,128 +272,5 @@ inst_emac_tx : entity work.emac_tx
|
||||
|
||||
);
|
||||
|
||||
gen_dmac:
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 generate
|
||||
|
||||
dma_bus_cmd_cycle_finished(i) <= bus_cmd_cycle_finished;
|
||||
dma_bus_cmd_rdy(i) <= bus_cmd_rdy;
|
||||
|
||||
inst_dmac : entity work.dmac
|
||||
Generic map
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
XFER_CHUNK_SIZE => 32
|
||||
)
|
||||
Port map
|
||||
(
|
||||
clk => CLK_I,
|
||||
rst => RST_I,
|
||||
|
||||
master_req => dma_master_req(i),
|
||||
master_gnt => dma_master_gnt(i),
|
||||
|
||||
req_rdy => dma_req_rdy(i),
|
||||
req_en => dma_req_en(i),
|
||||
req_rw => DMA_RW_CONF(i),
|
||||
req_addr_auto_inc => dma_req_addr_auto_inc(i),
|
||||
req_addr_start => dma_req_addr(i),
|
||||
req_num_xfers => dma_req_num_xfers(i),
|
||||
|
||||
req_complete => dma_req_complete(i),
|
||||
req_complete_ack => dma_req_complete_ack(i),
|
||||
|
||||
dma_start => dma_start(i),
|
||||
dma_active => dma_active(i),
|
||||
dma_end => dma_end(i),
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),
|
||||
bus_cmd_rdy => dma_bus_cmd_rdy(i),
|
||||
bus_cmd_we => dma_bus_cmd_we(i),
|
||||
bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i),
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out => dma_bus_cmd(i)
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
inst_busmaster_sync : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_I,
|
||||
clk => CLK_I,
|
||||
|
||||
cmd_cycle_finished => bus_cmd_cycle_finished,
|
||||
cmd_cycle_en => bus_cmd_cycle_en,
|
||||
|
||||
cmd_rdy => bus_cmd_rdy,
|
||||
cmd_we => bus_cmd_we,
|
||||
cmd_in => bus_cmd,
|
||||
|
||||
din_rdy => bus_din_rdy,
|
||||
din_we => bus_din_vld,
|
||||
din => bus_din,
|
||||
|
||||
dout => bus_dout,
|
||||
dout_vld => bus_dout_vld,
|
||||
dout_re => bus_dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
arbiter_proc:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
dma_master_gnt <= (others => '0');
|
||||
arb_idx <= 0;
|
||||
elsif dma_master_req(arb_idx) = '0' then
|
||||
if arb_idx /= DMA_NUM_CHANNEL-1 then
|
||||
arb_idx <= arb_idx + 1;
|
||||
else
|
||||
arb_idx <= 0;
|
||||
end if;
|
||||
else
|
||||
dma_master_gnt <= (others => '0');
|
||||
dma_master_gnt(arb_idx) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
arbiter_mux:
|
||||
process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
|
||||
variable v_bus_cmd_we : std_logic;
|
||||
variable v_bus_cmd_cycle_en : std_logic;
|
||||
begin
|
||||
v_bus_cmd_we := '0';
|
||||
v_bus_cmd_cycle_en := '0';
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 loop
|
||||
v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
|
||||
v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
|
||||
if dma_master_gnt(i) = '1' then
|
||||
bus_cmd <= dma_bus_cmd(i);
|
||||
end if;
|
||||
end loop;
|
||||
bus_cmd_we <= v_bus_cmd_we;
|
||||
bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
|
||||
+38
-45
@@ -116,9 +116,13 @@ ARCHITECTURE behavior OF emac_tx IS
|
||||
signal mii_fifo_re : std_logic;
|
||||
signal mii_fifo_full : std_logic;
|
||||
signal mii_fifo_empty : std_logic;
|
||||
signal mii_fifo_re_dly : unsigned(23 downto 0);
|
||||
signal mii_fifo_re_dly : unsigned(7 downto 0);
|
||||
|
||||
signal mii_bsy : std_logic;
|
||||
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
|
||||
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
|
||||
|
||||
signal ifg_cnt : ifg_cnt_t;
|
||||
signal ifg_idle : std_logic;
|
||||
|
||||
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
||||
signal host_s, host_sn : host_state_t;
|
||||
@@ -336,7 +340,6 @@ mem_free_counter:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mem_free_mii:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
@@ -353,7 +356,6 @@ mem_free_mii:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mem_free_host:
|
||||
process(clk)
|
||||
begin
|
||||
@@ -371,6 +373,15 @@ mem_free_host:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
host2xfer_sync_register:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
Gbps_en <= ctrl_in.Gbps_en;
|
||||
fcs_gen_en <= ctrl_in.fcs_gen_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Fill stuff
|
||||
------------------------------------------------------------------
|
||||
@@ -400,7 +411,6 @@ fill_counter:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fill_pointer:
|
||||
process(clk)
|
||||
begin
|
||||
@@ -416,14 +426,20 @@ fill_pointer:
|
||||
------------------------------------------------------------------
|
||||
-- Transfer stuff
|
||||
------------------------------------------------------------------
|
||||
host2xfer_sync_register:
|
||||
interframe_gap_counter:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
Gbps_en <= ctrl_in.Gbps_en;
|
||||
fcs_gen_en <= ctrl_in.fcs_gen_en;
|
||||
end if;
|
||||
end process;
|
||||
ifg_idle <= '0';
|
||||
if reset_en = '1' or mii_fifo_empty = '0' then
|
||||
ifg_cnt <= ifg_cnt_t'high;
|
||||
elsif ifg_cnt /= 0 then
|
||||
ifg_cnt <= ifg_cnt - 1;
|
||||
else
|
||||
ifg_idle <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_counter:
|
||||
@@ -449,7 +465,6 @@ xfer_counter:
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_pointer:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
@@ -479,7 +494,7 @@ xfer_state_next:
|
||||
end process;
|
||||
|
||||
xfer_state:
|
||||
process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
|
||||
process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
|
||||
begin
|
||||
|
||||
piso32_din_vld <= '0';
|
||||
@@ -500,12 +515,12 @@ xfer_state:
|
||||
xfer_sn <= xfer_idle;
|
||||
|
||||
when xfer_idle =>
|
||||
if cmd_fifo_empty = '0' and mii_bsy = '0' then
|
||||
if cmd_fifo_empty = '0' then
|
||||
xfer_sn <= xfer_start;
|
||||
end if;
|
||||
|
||||
when xfer_start =>
|
||||
if cmd_fifo_empty = '0' then
|
||||
if cmd_fifo_empty = '0' and ifg_idle = '1' then
|
||||
xfer_sn <= xfer_preamble0;
|
||||
end if;
|
||||
|
||||
@@ -562,7 +577,7 @@ xfer_state:
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_ram : entity work.dpram_1w1r2c_ro
|
||||
inst_ram : entity work.dpram_1w1r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => RAM_ADDR_WIDTH,
|
||||
@@ -570,8 +585,8 @@ inst_ram : entity work.dpram_1w1r2c_ro
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => mii_tx_clk,
|
||||
clka => clk,
|
||||
clkb => mii_tx_clk,
|
||||
en_a => ram_en_a,
|
||||
en_b => ram_en_b,
|
||||
we_a => ram_we_a,
|
||||
@@ -581,7 +596,6 @@ inst_ram : entity work.dpram_1w1r2c_ro
|
||||
dout_b => ram_dout_b
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_cmd_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
@@ -605,7 +619,6 @@ inst_cmd_fifo: entity work.fifo_async
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_piso32 : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -629,7 +642,6 @@ inst_piso32 : entity work.piso
|
||||
|
||||
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fcs_enable_gen:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
@@ -641,8 +653,8 @@ fcs_enable_gen:
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
|
||||
|
||||
inst_fcs: entity work.crc32
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -659,29 +671,17 @@ inst_fcs: entity work.crc32
|
||||
|
||||
);
|
||||
|
||||
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
|
||||
mii_fifo_re_dly_gen:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if mii_fifo_empty = '1' then
|
||||
if Gbps_en = '0' then
|
||||
mii_fifo_re_dly <= X"000000"; -- 100 mbps
|
||||
else
|
||||
mii_fifo_re_dly <= X"000FFF"; -- Gigabit
|
||||
end if;
|
||||
else
|
||||
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
|
||||
end if;
|
||||
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left);
|
||||
mii_fifo_re <= mii_fifo_re_dly(mii_fifo_re_dly'left) when Gbps_en = '1' else (piso8_din_rdy and mii_fifo_re_dly(mii_fifo_re_dly'left));
|
||||
mii_fifo_we <= piso32_dout_vld;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_mii_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
@@ -704,10 +704,6 @@ inst_mii_fifo: entity work.fifo_sync
|
||||
data_r => piso8_din
|
||||
);
|
||||
|
||||
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
|
||||
mii_fifo_we <= piso32_dout_vld;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_piso8 : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -728,10 +724,8 @@ inst_piso8 : entity work.piso
|
||||
dout => piso8_dout
|
||||
|
||||
);
|
||||
|
||||
piso8_din_vld <= not mii_fifo_empty and mii_bsy;
|
||||
piso8_din_vld <= not mii_fifo_empty and mii_fifo_re_dly(mii_fifo_re_dly'left);
|
||||
|
||||
------------------------------------------------------------------
|
||||
mii_output_register:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
@@ -747,5 +741,4 @@ mii_output_register:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
end behavior;
|
||||
|
||||
@@ -36,6 +36,7 @@ package emac_types is
|
||||
Gbps_en : std_logic;
|
||||
reset : std_logic;
|
||||
fcs_chk_en : std_logic;
|
||||
pkt_read_en : std_logic;
|
||||
pkt_req_en : std_logic;
|
||||
pkt_free_en : std_logic;
|
||||
mac_addr : mac_addr_t;
|
||||
|
||||
@@ -53,18 +53,6 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
|
||||
signal status_reg : unsigned(31 downto 0) := (others => '0');
|
||||
signal size_reg : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
-- Master
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '1';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
-- MII signals
|
||||
signal mii_rx_clk_board : std_logic := '1';
|
||||
signal mii_tx_clk_board : std_logic := '1';
|
||||
@@ -100,88 +88,10 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
|
||||
constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
|
||||
constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
|
||||
constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
|
||||
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000";
|
||||
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010";
|
||||
|
||||
|
||||
-- 64Bit RAM
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
type ram_t is array (0 to 511) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
process(CLK)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
variable data8: unsigned(7 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
data8 := X"00";
|
||||
for i in 0 to 255 loop
|
||||
ram_data(7 downto 0) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(15 downto 8) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(23 downto 16) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(31 downto 24) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(39 downto 32) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(47 downto 40) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(55 downto 48) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(63 downto 56) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram64(i) <= ram_data;
|
||||
end loop;
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
else -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
-- ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_emac_top_jb : entity work.emac_top_jb
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -191,7 +101,6 @@ inst_emac_top_jb : entity work.emac_top_jb
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- JBUS Slave signals
|
||||
CLK_I => CLK,
|
||||
RST_I => RST,
|
||||
INT_O => INT_O,
|
||||
@@ -205,19 +114,6 @@ inst_emac_top_jb : entity work.emac_top_jb
|
||||
ADDR_I => ADDR_I,
|
||||
DAT_I => DAT_I,
|
||||
DAT_O => DAT_O,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O,
|
||||
|
||||
mii_rx_clk => mii_rx_clk_board,
|
||||
mii_rx_dv => mii_rx_dv,
|
||||
mii_rx_er => mii_rx_er,
|
||||
@@ -492,7 +388,6 @@ STIMULUS: process
|
||||
variable size, num_words : natural;
|
||||
begin
|
||||
|
||||
return;
|
||||
emac_action <= emac_wait_data;
|
||||
|
||||
-- check if data available
|
||||
@@ -578,7 +473,6 @@ STIMULUS: process
|
||||
procedure emac_free is
|
||||
begin
|
||||
|
||||
return;
|
||||
-- RX- DEALLOCATION
|
||||
emac_action <= emac_free;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user